Prosecution Insights
Last updated: July 17, 2026
Application No. 18/659,350

METHOD FOR OBTAINING ENGINEERING CHANGE ORDER POINT BASED ON COMPARISON OF DESIGN FILES

Final Rejection §103§112
Filed
May 09, 2024
Priority
Apr 23, 2024 — CN 202410491064.X
Examiner
LEE, ERIC D
Art Unit
2851
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Easy-Logic Technology (Shenzhen) Co. Ltd.
OA Round
2 (Final)
81%
Grant Probability
Favorable
3-4
OA Rounds
3m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
531 granted / 653 resolved
+13.3% vs TC avg
Strong +20% interview lift
Without
With
+19.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
11 currently pending
Career history
662
Total Applications
across all art units

Statute-Specific Performance

§101
12.0%
-28.0% vs TC avg
§103
57.5%
+17.5% vs TC avg
§102
22.4%
-17.6% vs TC avg
§112
5.3%
-34.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 653 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Previous rejection of Claims 1-2, 4, and 6 under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, are withdrawn in view of Applicant’s Amendments filed 6/4/2023. Claims 1, 2, 4, and 6 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The term “very intuitive” in claim 1 is a relative term which renders the claim indefinite. The term “very intuitive” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The limitation “translation” is therefore rendered indefinite by the use of the term “very intuitive”. The term “basically” in claim 1 is a relative term which renders the claim indefinite. The term “basically” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. The limitation “correspond” is therefore rendered indefinite by the use of the term “basically”. Claim 1 recites the limitation "the elaboration" in line 10. There is insufficient antecedent basis for this limitation in the claim. Claim 1 recites the limitation "the logic synthesis process" in line 10. There is insufficient antecedent basis for this limitation in the claim. Claims 2, 4, and 6 are rejected based on their dependency to Claim 1 for the reasons stated above. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-2, 4, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Satapathy et al., hereinafter Satapathy, US Publication No. 2005/0091627 in view of Dupenloup, US Patent No. 6,836,877. Regarding Claim 1, Satapathy teaches a method for obtaining an engineering change order (ECO) point based on a comparison of design files, for finding difference ECO points between a revision design and an original design in a chip design (Satapathy paragraph [0009], wherein a reference netlist and a modified version of the netlist are compared to determine differences to implement an engineering change order), wherein the method uses a generic technology (GTECH) file for comparison without using a logic equivalence check (LEC) tool (Satapathy paragraphs [0002]-[0003] and [0009], wherein the netlists are produced through synthesis and are compared without a logic equivalence tool), the method comprises: Step S1, finding an old GTECH file corresponding to the original design and a new GTECH file corresponding to the revision design (Satapathy paragraph [0020], wherein a reference netlist and a modified netlist are acquired and input into a comparator tool); Step S2, comparing the old GTECH file and the new GTECH file to find key point information (Satapathy paragraphs [0028]-[0037], wherein a reference netlist and a modified netlist are compared by comparator tool which generates information including the differences between the netlists); and Step S3, based on the key point information, analyzing a component composition of a circuit and connection of components in the circuit, to find the difference ECO points (Satapathy paragraph [0037], wherein the ECOs are generated for both differences in cells and nets in a circuit); wherein the analyzing the component composition of the circuit and connection of the components in the circuit comprises: comparing functions of the circuits of the original design and the revision design based on the key point information (Satapathy paragraph [0037], wherein the cells of the reference and modified netlists are compared based upon the discovery of a difference, which is comparing functions of the circuits); analyzing overall circuit architectures and functional description of the original design and the revision design (Satapathy paragraph [0037], wherein the information associated with the cells, e.g. cell type, name, etc…, is analyzed in the comparison); comparing a connection relationship and a signal flow of each component in the original design and the revision design (Satapathy paragraph [0043], wherein nets are compared between the reference and modified netlists); checking whether there are new or deleted component connections and changes in the connection relationships (Satapathy paragraphs [0043]-[0051], wherein the comparison of the nets includes determining if there are new or removed pins); and marking the key point information where there are differences as the difference ECO points (Satapathy paragraphs [0037] and [0052], wherein ECOs are generated which marks locations of the differences). Satapathy does not explicitly teach wherein GTECH is a special netlist, GTECH is a Register Transfer Level (RTL) -> netlist, a very intuitive translation, without any optimization, its hierarchical structure and that of RTL basically correspond exactly to each other, and the special netlist is directly outputted after the elaboration in the logic synthesis process. Dupenloup teaches GTECH is a special netlist, GTECH is a Register Transfer Level (RTL) -> netlist, a very intuitive translation, without any optimization, its hierarchical structure and that of RTL basically correspond exactly to each other (Dupenloup Col. 28, lines 21-26 and Col. 29, Lines 1-45, wherein netlists are generated by synthesis from a GTECH library without optimization, and are hierarchical and correspond to the RTL), and the special netlist is directly outputted after the elaboration in the logic synthesis process (Dupenloup Col. 18, Lines 20-44, wherein the generic netlist is available after the elaborate operation). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Satapathy and Dupenloup to apply the known technique of GTECH libraries when synthesizing netlists as taught by Dupenloup to improve on the netlists of Satapathy to yield the predictable results of improved netlist analysis as taught in Dupenloup Col. 29, Lines 22-40. Regarding Claim 2, Satapathy further teaches wherein in the step S2, the comparing the old GTECH file and the new GTECH file comprises: comparing based on a component and a logic, respectively, to find the key point information (Satapathy paragraphs [0021] and [0037], wherein components and their logic function are compared to determine differences); based on the component, analyzing structures of the old GTECH file and the new GTECH file, and finding types, numbers and connection relationships of components contained in the old GTECH file and the new GTECH file respectively (Satapathy paragraphs [0021] and [0037], wherein the components are analyzed and include the type of the component, the number of instances of the components, and how they are connected in each of the reference and modified netlists); comparing the type, number and connection relationship of each component in the old GTECH file and the new GTECH file to see whether they are changed, and when one thereof is not the same in the old GTECH file and the new GTECH file, then it is determined that the component is changed (Satapathy paragraphs [0037], wherein the comparison determines if there are changes); marking the changed component as the key point information (Satapathy paragraphs [0037], wherein the differences are identified based on the comparison); and based on the logic, determining whether logical functionality implemented in the old GTECH file and the new GTECH file are consistent, marking a part of the logical functionality that is changed as the key point information (Satapathy paragraphs [0022]-[0023], and [0037], wherein the comparison also determines changes based on the types of cells and their configuration, i.e. their logical functionality). Regarding Claim 4, Satapathy further teaches wherein the comparing the type, number and connection relationship of each component in the old GTECH file and the new GTECH file to see whether they are changed comprises: determining whether the type of each component in the old GTECH file and the new GTECH file is the same, whether there are new or deleted types of components, or whether any types of components are replaced (Satapathy paragraphs [0037]-[0042], wherein the comparison determines the differences between the components present in the reference and modified netlists, including differences in type of cells and whether cells have been added, deleted, or swapped); and determining whether the number of components of the same type in the old GTECH file and the new GTECH file are the same, wherein any increase or decrease in the number is considered to be a change (Satapathy paragraphs [0037]-[0042], wherein cell-type mismatches are determined and the changes marked). Regarding Claim 6, Satapathy further teaches wherein the comparing a consistency of logical functionality implemented in the old GTECH file and the new GTECH file is to check whether the old GTECH file and the new GTECH file are functionally equivalent, at least comprising checks of the signal flow and interface compatibility (Satapathy paragraph [0043], wherein the net map is compared which is a check on signal flow and interface compatibility); the check of the signal flow refers to check whether a flow path of signals in the old GTECH file and the new GTECH file are the same, comprising a transmission, processing and output of the signals (Satapathy paragraphs [0043]-[0044], wherein the net maps are compared to determine any differences, which compares pin to net connections and net names, i.e. signal flow); and the check of the interface compatibility refers to verify that interfaces in the old GTECH file and the new GTECH file are compatible to ensure that there are no problems with connections to other modules (Satapathy paragraphs [0043]-[0044], wherein pin-to net connections are generated and checked to ensure compatibility). Response to Arguments Applicant's arguments filed 6/4/2026 have been fully considered but they are not persuasive. In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, while Applicant argues that “a person skilled in the art has no reasonable motivation to apply Dupenloup’s unoptimized netlist feature designed for logic synthesis and hierarchical analysis to modify Satapathy’s ECO difference comparison workflow,” Examiner respectfully disagrees. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Satapathy and Dupenloup to apply the known technique of GTECH libraries when synthesizing netlists as taught by Dupenloup to improve on the netlists of Satapathy to yield the predictable results of improved netlist analysis as taught in Dupenloup Col. 29, Lines 22-40. Specifically in Dupenloup Col. 29, Lines 1-40, the use of a generic library, such as GTECH, to produce a netlist provides numerous advantages (e.g. faster synthesis, better gate-count and fan-out estimates, able to track technology specific issues, etc…). Since Satapathy uses netlist analysis to determine ECOs, the application of the GTECH library as taught by Dupenloup would improve the netlist analysis in a known way, yielding predictable results. Applicant’s arguments are therefore not persuasive and the rejection is maintained. Applicant’s remaining arguments regarding the remaining dependent claims are not persuasive for the reasons stated above. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC D LEE whose telephone number is (571)270-7098. The examiner can normally be reached Monday-Thursday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERIC D LEE/Primary Examiner, Art Unit 2851
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Prosecution Timeline

May 09, 2024
Application Filed
Feb 05, 2026
Response after Non-Final Action
Mar 20, 2026
Response after Non-Final Action
Apr 29, 2026
Non-Final Rejection mailed — §103, §112
Jun 04, 2026
Response Filed
Jun 22, 2026
Final Rejection mailed — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
81%
Grant Probability
99%
With Interview (+19.5%)
2y 5m (~3m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 653 resolved cases by this examiner. Grant probability derived from career allowance rate.

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