DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 5-6, 10-14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by O’Leary et al. (USPGPUB 2022/0352651, from hereinafter “O’Leary”).
Regarding claims 1 and 13-14, O’Leary teaches a host device (module 10) comprising: a Printed Circuit Board (PCB) (PCBA18) including a first side with multiple rows of Ball Grid Array (BGA) contacts (BGA components 22 on secondary side 14 of the PCBA, for interpretation there are two sides, there is a first and second which can be interchanged, for this interpretation the first side of instant application is the “secondary side 14” of the invention); and a first socket interface (interface components) including a receptacle configured to receive a pluggable optical module (pluggable module 202) for communication therewith, the socket interface further including multiple electrical conductors (electrical components) configured for electrical connection with the BGA contacts (see Figures 1-4, paragraphs 2, 5-6, 22-27). Further regarding claim 13, O’Leary teaches a network element (see paragraph 52) comprising: one or more modules each includes a Printed Circuit Board (PCB) including a first side with multiple rows of Ball Grid Array (BGA) contacts; and a first socket interface including a receptacle configured to receive a pluggable optical module for communication therewith, the socket interface further including multiple electrical conductors configured for electrical connection with the BGA contacts.
Regarding claims 2 and 5-6, O’Leary teaches wherein each row of the BGA contacts on the first side includes multiple first sets of contacts offset from each other in a first direction with respect to a planar surface of the first side of the PCB (see Figure 1A) and further, wherein the PCB includes a second side with multiple second rows of second BGA contacts, and the host device further includes a second socket interface including a second receptacle configured to receive a second pluggable module for communication therewith, the second socket interface further including multiple second electrical conductors configured for electrical connection with the second BGA contacts (see Figures 1-4, paragraphs 5-6).
Regarding claim 10, O’Leary teaches wherein the pluggable optical module is any of a Small Form-factor Pluggable (SFP) transceiver, a Quad SFP (QSFP) transceiver, a QSFP Double-Density (QSFP-DD) transceiver, an Octal SFP (OSFP) transceiver, a C (100) Form-factor Pluggable (CFP) transceiver, and variants thereof when it is taught that In an embodiment and in the description herein, the pluggable module 202 is a CFP2-DCO module (C Small Form Factor Pluggable Digital Coherent Optics). Of course, other types of pluggable optical modules are also contemplated, such as, for example, CFP, CFP2, CFP4, QSFP, QSFP2, QSFP-DD, etc. For example, CFP2-DCO is described in OIF IA #OIF-CFP2-DCO-01.0 “Implementation Agreement for CFP2-Digital Coherent Optics Module,” Oct. 17, 2018, the contents of which are incorporated herein by reference ( see paragraph 42).
Regarding claim 11, O’Leary teaches wherein the pluggable optical module electrically connects to the receptacle, apart from the BGA contacts, via a standards-based implementation when it is taught that with the addition of the secondary side heatsink 212, the module, rather than sliding between cage bottom and primary side heatsink 214, will now slide up against both the primary and secondary side heatsinks 214, 212. To not exceed the MSA standard insertion force requirements while now having more heatsink surface and potential pressure increase on the module 202, a pivot point mounting approach is used. The pivot point is towards the center of the primary side heatsink 214 and allows for easy insertion (normal insertion force) at the beginning of the insertion and enough and appropriate contact to both the primary and secondary side heatsinks 214, 212 once the module 202 is fully inserted. That is, the present disclosure supports heatsinks 212, 214 on both sides of the pluggable module 202 while conforming to MSA standards Further regarding claim 12, O’Leary teaches the standards implementation in which conduction rate is at least 100 Gbps (see paragraph 50).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 and 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over O’Leary in view of Leclair et al. (USPGPUB 202/0341218, from hereinafter “Leclair”).
Regarding claims 7 and 16-18, O’Leary teaches a Printed Circuit Board (PCB) for use in networking hardware, the PCB comprises: a first side and a second side, each with multiple rows of Ball Grid Array (BGA) contacts; and a plurality of socket interfaces, each including a receptacle configured to receive a pluggable optical module for communication therewith, each socket interface further including multiple electrical conductors configured for electrical connection with the BGA contacts (see citations above and see Figures 1-4, paragraphs 2, 5-6, 22-27).
O’Leary fails to specifically teach hardware to support a belly- to-belly configuration of pluggable optical modules wherein the belly-to-belly configuration includes at least one pair socket interfaces being disposed near one another of the first side and the second.
Leclair teaches that FIG. 13 is a side diagram of the USS 10C that has 12×Small Form-factor Pluggable (SFP) interfaces. The USS 10C includes two rows of 6 SFP interfaces on the faceplate 30. Here, the PCB 12 that includes the SFP+ cages 100 has a fixed thickness specified by the cage vendor for belly-to-belly mounting. The PCB 12 placement is then fixed by the USS faceplate 30 space. A second PCB 102 in the assembly has a fixed position with the second PCB 102 located on the motherboard and used to provide interconnect from the PCB 12 to the connectors 14 via a fixed height connector 104. The spacing between the first PCB 12 and the second PCB 102 is now an odd number that cannot be used for the fixed height connector 104 (see paragraph 62).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize a belly to belly configuration to minimize space and shorten signal paths, and hence imparts better effectiveness for the PCB.
Regarding claim 18, O’Leary teaches wherein each row of the BGA contacts on the first side and the second includes multiple sets of contacts offset from each other in a first direction with respect to a planar surface of the first side of the PCB, and further offset from adjacent contacts on the other side (see Figures 1-4, paragraphs 5-6).
Allowable Subject Matter
Claims 3-4, 8-9, 15, 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The best prior art of record fails to specifically teach the specific arrangement of solder balls for the arrangement of multiple sets of contacts, for example in claim 3, the best prior art of record does not teach wherein the multiple first sets of contacts include a first set of solder balls, a second set of solder balls, and a third set of solder balls, and wherein the second set of solder balls is offset from the first set of solder balls in the first direction and the third set of solder balls is offset from the second set of solder balls in the first direction
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US Patent No. 10,866,376 to Ghiasi which teaches a method and system for co-packaging photonics IC with an application specific IC.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LISA M CAPUTO whose telephone number is (571)272-2388. The examiner can normally be reached Monday-Friday 9-5 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at 571-272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LISA M CAPUTO/Primary Patent Examiner, Art Unit 2874
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