DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor Package Including Insulating Layers with Different Coefficients of Thermal Expansion and Method of Manufacturing Thereof.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, and 11-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lan et al (US 2015/0001729).
Regarding Claim 1, Lan et al discloses a semiconductor package (semiconductor die package 240 [0079] Fig 6i), comprising:
a package substrate (portion of substrate 200 [0079] shown in annotated Fig 6i) including a first region (area 216 [0070] Fig 6i) and a second region (area 218 [0070] Fig 6i) surrounding the first region (216 Fig 6i), the package substrate (portion of 200 shown in annotated Fig 6i) including a first insulation layer (portion of insulating layer 206 [0067] shown in annotated Fig 6i) on an upper surface thereof;
an outermost insulation layer (insulating layer 220 [0071] Fig 6i) on the first insulation layer (portion of 206 shown in annotated Fig 6i) of the package substrate (portion of 200 shown in annotated Fig 6i), the outermost insulation layer (220 Fig 6i) defining a window that exposes the first region (216 Fig 6i) of the package substrate (portion of 200 shown in annotated Fig 6i);
a first electronic device (semiconductor die 144 [0048] Fig 6i) on the first region (216 Fig 6i) of the package substrate (portion of 200 shown in annotated Fig 6i);
an underfill member (underfill material 230 [0075] Fig 6i) in the window of the outermost insulation layer (220 Fig 6i) on the first region (216 Fig 6i) of the package substrate (portion of 200 shown in annotated Fig 6i), the underfill member (230 Fig 6i) at least partially filling a gap between the first electronic device (144 Fig 6i) and the package substrate (portion of 200 shown in annotated Fig 6i); and
a second electronic device (semiconductor die 124 [0074] Fig 6i) on the outermost insulation layer (220 Fig 6i).
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Regarding Claim 2, Lan et al discloses the limitations of claim 1 as explained above. Lan et al further discloses
wherein the window of the outermost insulation layer (220 Fig 6i) includes a first inner surface (shown in annotated Fig 6d and Fig 6i), a second inner surface (shown in annotated Fig 6d and Fig 6i), a third inner surface (shown in annotated Fig 6d) and a fourth inner surface (shown in annotated Fig 6d), and the first to fourth inner surfaces (shown in the combination of annotated Fig 6d and Fig 6i) surround the first region (216 Fig 6i).
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Regarding Claim 11, Lan et al discloses a semiconductor package (semiconductor die package 240 [0079] Fig 6i), comprising:
a package substrate (portion of substrate 200 [0079] shown in annotated Fig 6i) including a first region (area 216 [0070] Fig 6i) and a second region (area 218 [0070] Fig 6i) surrounding the first region (216 Fig 6i), the package substrate (portion of 200 shown in annotated Fig 6i) including a first insulation layer (portion of insulating layer 206 [0067] shown in annotated Fig 6i) on an upper surface thereof;
the first insulation layer (206 Fig 6i) exposing a plurality of first substrate pads (contact pads 210a [0069] corresponding to area 216 Fig 6i) in the first region (216 Fig 6i) and a plurality of second substrate pads (contact pads 210b [0069] corresponding to area 218 Fig 6i) in the second region (218 Fig 6i);
an outermost insulation layer (insulating layer 220 [0071] Fig 6i) on the first insulation layer (portion of 206 shown in annotated Fig 6i) of the package substrate (portion of 200 shown in annotated Fig 6i), the outermost insulation layer (220 Fig 6i) defining a window that exposes the first region (216 Fig 6i) of the package substrate (portion of 200 shown in annotated Fig 6i);
the outermost insulation layer (220 Fig 6i) including a plurality of third substrate pads (lower portion of bumps 134 [0045] shown in annotated Fig 6i) that are electrically connected to the plurality of second substrate pads (210b in area 218 Fig 6i), respectively;
a first electronic device (semiconductor die 144 [0048] Fig 6i) on the first region (216 Fig 6i) of the package substrate (portion of 200 shown in annotated Fig 6i);
a plurality of first conductive connection members (bumps 224 [0073] Fig 6i) between the package substrate (portion of 200 shown in annotated Fig 6i) and the first electronic device (144 Fig 6i), the plurality of first conductive connection members (224 Fig 6i) electrically connecting the plurality of first substrate pads (210a in area 216 Fig 6i) and the first electronic device (144 Fig 6i);
an underfill member (underfill material 230 [0075] Fig 6i) in the window of the outermost insulation layer (220 Fig 6i) on the first region (216 Fig 6i) of the package substrate (portion of 200 shown in annotated Fig 6i), the underfill member (230 Fig 6i) at least partially filling a gap between the first electronic device (144 Fig 6i) and the package substrate (portion of 200 shown in annotated Fig 6i); and
a second electronic device (semiconductor die 124 [0074] Fig 6i) on the outermost insulation layer (220 Fig 6i).
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Regarding Claim 12, Lan et al discloses the limitations of claim 11 as explained above. Lan et al further discloses
wherein the window of the outermost insulation layer (220 Fig 6i) includes a first inner surface (shown in annotated Fig 6d and Fig 6i), a second inner surface (shown in annotated Fig 6d and Fig 6i), a third inner surface (shown in annotated Fig 6d) and a fourth inner surface (shown in annotated Fig 6d), and the first to fourth inner surfaces (shown in the combination of annotated Fig 6d and Fig 6i) surround the first region (216 Fig 6i).
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3-6, 8, 10, 13-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lan et al (US 2015/0001729) in view of Huang et al (US 2022/0367334).
Regarding Claim 3, Lan et al discloses the limitations of claim 1 as explained above. Lan et al does not directly disclose
wherein a distance between a side surface of the first electronic device and an inner surface of the window of the outermost insulation layer is at least 100 μm.
However, Huang et al, in the related art of semiconductor devices that include semiconductor packaging, discloses
wherein a width of the pillar (pillar 10P [0062]/[Table 1] Fig 1A and Fig 1C) is about 80 microns to 90 microns (the examiner notes that, although not drawn to scale, the width of pillar 10P is approximately the distance between a side surface of the first electronic device (die [0039] Fig 1A) and an inner surface of the window (area where the underfill UF [0042] is present)).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lan et al to include wherein a distance between a side surface of the first electronic device and an inner surface of the window of the outermost insulation layer is at least 100 μm as taught by Huang et al in order to meet dimensional tolerances [0003] while optimizing the support that the underfill can give to the first electronic device and because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05). Further, a person of ordinary skill in the art would have recognized that having an optimized underfill would help prevent damage from mechanical stress (see MPEP 2143.I(D)).
Regarding Claim 4, Lan et al discloses the limitations of claim 1 as explained above. Lan et al does not directly disclose
wherein a thickness of the first insulation layer is smaller than a thickness of the outermost insulation layer.
Huang et al, in the related art of semiconductor devices that include semiconductor packaging, discloses
wherein a thickness of the first insulation layer (solder mask 10A which includes dielectric material [0107]-[0108] Fig 1A) is smaller than a thickness of the outermost insulation layer (solder mask 10B which includes dielectric material [0107]-[0108] Fig 1A).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lan et al to include wherein a thickness of the first insulation layer is smaller than a thickness of the outermost insulation layer as taught by Huang et al in order for the package to better utilize the underfill [0042]. Further, a person of ordinary skill in the art would have recognized that the insulating material would provide reinforcement to the underfill and would prevent damage from mechanical stress (see MPEP 2143.I(D)).
Regarding Claim 5, the combination of Lan et al and Huang et al discloses the limitations of claim 4 as explained above. The combination of Lan et al and Huang et al, as applied to claim 4, does not directly disclose
wherein the thickness of the first insulation layer is within a range of 8 µm to 12 µm, and the thickness of the outermost insulation layer is within a range of 15 µm to 18 µm.
However, Huang et al, in the related art of semiconductor devices that include semiconductor packaging, discloses
wherein the thickness of the first insulation layer (solder mask 10A which includes dielectric material [0107]-[0108] Fig 1A) is within a range of 8 µm to 12 µm (thickness T10A-1 is within 5 and 15 microns [0113] Fig 1C), and the thickness of the outermost insulation layer (solder mask 10B which includes dielectric material [0107]-[0108] Fig 1A) is within a range of 15 µm to 18 µm (thickness T10-2-T10-1 = 25 microns – 12 microns = 13 microns [0062] Fig 1C).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Lan et al and Huang et al, as applied to claim 4, to include wherein the thickness of the first insulation layer is within a range of 8 µm to 12 µm, and the thickness of the outermost insulation layer is within a range of 15 µm to 18 µm as taught by Huang et al in order to better utilize the underfill [0042] and because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05). Further, a person of ordinary skill in the art would have recognized that the insulating material would provide reinforcement to the underfill and would prevent damage from mechanical stress (see MPEP 2143.I(D)).
Regarding Claim 6, Lan et al discloses the limitations of claim 1 as explained above. Lan et al does not directly disclose
wherein the first insulation layer has a first coefficient of thermal expansion,
the outermost insulation layer has a second coefficient of thermal expansion, and
the package substrate has a third coefficient of thermal expansion,
wherein the first coefficient of thermal expansion and the second coefficient of thermal expansion are greater than the third coefficient of thermal expansion.
Huang et al, in the related art of semiconductor devices that include semiconductor packaging, discloses
wherein a thickness of the first insulation layer (solder mask 10A which includes dielectric material [0107]-[0108] Fig 1A) is smaller than a thickness of the outermost insulation layer (solder mask 10B which includes dielectric material [0107]-[0108] Fig 1A).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lan et al to include wherein a thickness of the first insulation layer is smaller than a thickness of the outermost insulation layer as taught by Huang et al in order for the package to better utilize the underfill [0042]. Further, a person of ordinary skill in the art would have recognized that the insulating material would provide reinforcement to the underfill and would prevent damage from mechanical stress (see MPEP 2143.I(D)).
The combination of Lan et al and Huang et al now discloses
wherein a thickness of the first insulation layer (SM10A Fig 1A Huang et al) is smaller than a thickness of the outermost insulation layer (SM10B Fig 1A Huang et al),
wherein a first coefficient of thermal expansion of the first insulation layer (SM10A Fig 1A Huang et al) and a second coefficient of thermal expansion of the outermost insulation layer (SM10B Fig 1A Huang et al) are greater than a third coefficient of thermal expansion of the package substrate (portion of 200 shown in annotated Fig 6i Lan et al/dielectric layers D1, D2, D3 and solder mask SMB [0048] Fig 1A Huang et al) (the thermal expansion formula α = δL/(L0(T1-T2)) is well known in the art and it can be observed that the coefficient of thermal expansion α of the thinner layers (smaller L0), SM10A and SM10B, would be greater than the coefficient of thermal expansion α of the thicker substrate (larger L0)).
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Regarding Claim 8, the combination of Lan et al and Huang et al discloses the limitations of claim 6 as explained above. The combination of Lan et al and Huang et al further discloses
wherein the underfill member (underfill material 230 [0075] Fig 6i Lan et al) has a fourth coefficient of thermal expansion (coefficient of thermal expansion for underfill 230 Lan et al), and
the first coefficient of thermal expansion (coefficient of thermal expansion for SM10A Fig 1A Huang et al) and the second coefficient of thermal expansion (coefficient of thermal expansion for SM10B Fig 1A Huang et al) are greater than the fourth coefficient of thermal expansion (the thermal expansion formula α = δL/(L0(T1-T2)) is well known in the art and it can be observed that the coefficient of thermal expansion α of the thinner layers (smaller L0), SM10A and SM10B, would be greater than the coefficient of thermal expansion α of the thicker underfill layer (larger L0)).
Regarding Claim 10, Lan et al discloses the limitations of claim 1 as explained above. Lan et al does not directly disclose
further comprising: a plurality of external connection members respectively on a plurality of lower substrate pads on a lower surface of the package substrate.
Huang et al, in the related art of semiconductor devices that include semiconductor packaging, discloses
further comprising: a plurality of external connection members (connectors CT [0048] Fig 1A) respectively on a plurality of lower substrate pads (pads PB [0048] Fig 1A) on a lower surface of the package substrate (dielectric layers D1, D2, D3 and solder mask SMB [0048] Fig 1A).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lan et al to include further comprising: a plurality of external connection members respectively on a plurality of lower substrate pads on a lower surface of the package substrate as taught by Huang et al in order to provide electrical connection to conductive traces TR1 through a via (not shown) [0048] Fig 1A. Further, a person of ordinary skill in the art would have recognized that optimizing electrically conductive capabilities would be advantageous in improving the electrical performance and functionality of the device (see MPEP 2143.I(D)).
Regarding Claim 13, Lan et al discloses the limitations of claim 11 as explained above. Lan et al does not directly disclose
wherein a distance between a side surface of the first electronic device and an inner surface of the window of the outermost insulation layer is at least 100 μm.
However, Huang et al, in the related art of semiconductor devices that include semiconductor packaging, discloses
wherein a width of the pillar (pillar 10P [0062]/[Table 1] Fig 1A and Fig 1C) is about 80 microns to 90 microns (the examiner notes that, although not drawn to scale, the width of pillar 10P is approximately the distance between a side surface of the first electronic device (die [0039] Fig 1A) and an inner surface of the window (area where the underfill UF [0042] is present)).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lan et al to include wherein a distance between a side surface of the first electronic device and an inner surface of the window of the outermost insulation layer is at least 100 μm as taught by Huang et al in order to meet dimensional tolerances [0003] while optimizing the support that the underfill can give to the first electronic device and because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05). Further, a person of ordinary skill in the art would have recognized that having an optimized underfill would help prevent damage from mechanical stress (see MPEP 2143.I(D)).
Regarding Claim 14, Lan et al discloses the limitations of claim 11 as explained above. Lan et al does not directly disclose
wherein a thickness of the first insulation layer is smaller than a thickness of the outermost insulation layer.
Huang et al, in the related art of semiconductor devices that include semiconductor packaging, discloses
wherein a thickness of the first insulation layer (solder mask 10A which includes dielectric material [0107]-[0108] Fig 1A) is smaller than a thickness of the outermost insulation layer (solder mask 10B which includes dielectric material [0107]-[0108] Fig 1A).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lan et al to include wherein a thickness of the first insulation layer is smaller than a thickness of the outermost insulation layer as taught by Huang et al in order for the package to better utilize the underfill [0042]. Further, a person of ordinary skill in the art would have recognized that the insulating material would provide reinforcement to the underfill and would prevent damage from mechanical stress (see MPEP 2143.I(D)).
Regarding Claim 15, the combination of Lan et al and Huang et al discloses the limitations of claim 14 as explained above. The combination of Lan et al and Huang et al, as applied to claim 14, does not directly disclose
wherein the thickness of the first insulation layer is within a range of 8 µm to 12 µm, and the thickness of the outermost insulation layer is within a range of 15 µm to 18 µm.
However, Huang et al, in the related art of semiconductor devices that include semiconductor packaging, discloses
wherein the thickness of the first insulation layer (solder mask 10A which includes dielectric material [0107]-[0108] Fig 1A) is within a range of 8 µm to 12 µm (thickness T10A-1 is within 5 and 15 microns [0113] Fig 1C), and the thickness of the outermost insulation layer (solder mask 10B which includes dielectric material [0107]-[0108] Fig 1A) is within a range of 15 µm to 18 µm (thickness T10-2-T10-1 = 25 microns – 12 microns = 13 microns [0062] Fig 1C).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Lan et al and Huang et al, as applied to claim 14, to include wherein the thickness of the first insulation layer is within a range of 8 µm to 12 µm, and the thickness of the outermost insulation layer is within a range of 15 µm to 18 µm as taught by Huang et al in order to better utilize the underfill [0042] and because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05). Further, a person of ordinary skill in the art would have recognized that the insulating material would provide reinforcement to the underfill and would prevent damage from mechanical stress (see MPEP 2143.I(D)).
Regarding Claim 16, Lan et al discloses the limitations of claim 11 as explained above. Lan et al does not directly disclose
wherein the first insulation layer has a first coefficient of thermal expansion,
the outermost insulation layer has a second coefficient of thermal expansion, and
the package substrate has a third coefficient of thermal expansion,
wherein the first coefficient of thermal expansion and the second coefficient of thermal expansion are greater than the third coefficient of thermal expansion.
Huang et al, in the related art of semiconductor devices that include semiconductor packaging, discloses
wherein a thickness of the first insulation layer (solder mask 10A which includes dielectric material [0107]-[0108] Fig 1A) is smaller than a thickness of the outermost insulation layer (solder mask 10B which includes dielectric material [0107]-[0108] Fig 1A).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lan et al to include wherein a thickness of the first insulation layer is smaller than a thickness of the outermost insulation layer as taught by Huang et al in order for the package to better utilize the underfill [0042]. Further, a person of ordinary skill in the art would have recognized that the insulating material would provide reinforcement to the underfill and would prevent damage from mechanical stress (see MPEP 2143.I(D)).
The combination of Lan et al and Huang et al now discloses
wherein a thickness of the first insulation layer (SM10A Fig 1A Huang et al) is smaller than a thickness of the outermost insulation layer (SM10B Fig 1A Huang et al),
wherein a first coefficient of thermal expansion of the first insulation layer (SM10A Fig 1A Huang et al) and a second coefficient of thermal expansion of the outermost insulation layer (SM10B Fig 1A Huang et al) are greater than a third coefficient of thermal expansion of the package substrate (portion of 200 shown in annotated Fig 6i Lan et al/dielectric layers D1, D2, D3 and solder mask SMB [0048] Fig 1A Huang et al) (the thermal expansion formula α = δL/(L0(T1-T2)) is well known in the art and it can be observed that the coefficient of thermal expansion α of the thinner layers (smaller L0), SM10A and SM10B, would be greater than the coefficient of thermal expansion α of the thicker substrate (larger L0)).
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Regarding Claim 18, the combination of Lan et al and Huang et al discloses the limitations of claim 16 as explained above. The combination of Lan et al and Huang et al further discloses
wherein the underfill member (underfill material 230 [0075] Fig 6i Lan et al) has a fourth coefficient of thermal expansion (coefficient of thermal expansion for underfill 230 Lan et al), and
the first coefficient of thermal expansion (coefficient of thermal expansion for SM10A Fig 1A Huang et al) and the second coefficient of thermal expansion (coefficient of thermal expansion for SM10B Fig 1A Huang et al) are greater than the fourth coefficient of thermal expansion (the thermal expansion formula α = δL/(L0(T1-T2)) is well known in the art and it can be observed that the coefficient of thermal expansion α of the thinner layers (smaller L0), SM10A and SM10B, would be greater than the coefficient of thermal expansion α of the thicker underfill layer (larger L0)).
Regarding Claim 19, Lan et al discloses the limitations of claim 11 as explained above. Lan et al does not directly disclose
further comprising: a plurality of external connection members respectively on a plurality of lower substrate pads on a lower surface of the package substrate.
Huang et al, in the related art of semiconductor devices that include semiconductor packaging, discloses
further comprising: a plurality of external connection members (connectors CT [0048] Fig 1A) respectively on a plurality of lower substrate pads (pads PB [0048] Fig 1A) on a lower surface of the package substrate (dielectric layers D1, D2, D3 and solder mask SMB [0048] Fig 1A).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lan et al to include further comprising: a plurality of external connection members respectively on a plurality of lower substrate pads on a lower surface of the package substrate as taught by Huang et al in order to provide electrical connection to conductive traces TR1 through a via (not shown) [0048] Fig 1A. Further, a person of ordinary skill in the art would have recognized that optimizing electrically conductive capabilities would be advantageous in improving the electrical performance and functionality of the device (see MPEP 2143.I(D)).
Regarding Claim 20, Lan et al discloses a semiconductor package (semiconductor die package 240 [0079] Fig 6i), comprising:
a package substrate (portion of substrate 200 [0079] shown in annotated Fig 6i) including a first region (area 216 [0070] Fig 6i) and a second region (area 218 [0070] Fig 6i) surrounding the first region (216 Fig 6i), the package substrate (portion of 200 shown in annotated Fig 6i) including a first insulation layer (portion of insulating layer 206 [0067] shown in annotated Fig 6i) on an upper surface thereof;
an outermost insulation layer (insulating layer 220 [0071] Fig 6i) on the first insulation layer (portion of 206 shown in annotated Fig 6i) of the package substrate (portion of 200 shown in annotated Fig 6i), the outermost insulation layer (220 Fig 6i) including a window that exposes the first region (216 Fig 6i) of the package substrate (portion of 200 shown in annotated Fig 6i);
a first electronic device (semiconductor die 144 [0048] Fig 6i) on the first region (216 Fig 6i) of the package substrate (portion of 200 shown in annotated Fig 6i);
an underfill member (underfill material 230 [0075] Fig 6i) in the window of the outermost insulation layer (220 Fig 6i) on the first region (216 Fig 6i) of the package substrate (portion of 200 shown in annotated Fig 6i) and at least partially filling a gap between the first electronic device (144 Fig 6i) and the package substrate (portion of 200 shown in annotated Fig 6i); and
a second electronic device (semiconductor die 124 [0074] Fig 6i) on the outermost insulation layer (220 Fig 6i),
wherein the window of the outermost insulation layer (220 Fig 6i) includes a first inner surface (shown in annotated Fig 6d and Fig 6i), a second inner surface (shown in annotated Fig 6d and Fig 6i), a third inner surface (shown in annotated Fig 6d) and a fourth inner surface (shown in annotated Fig 6d), and the first to fourth inner surfaces (shown in the combination of annotated Fig 6d and Fig 6i) surround the first region (216 Fig 6i),
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Lan et al does not directly disclose
wherein a thickness of the first insulation layer is smaller than a thickness of the outermost insulation layer, wherein a first coefficient of thermal expansion of the first insulation layer and a second coefficient of thermal expansion of the outermost insulation layer are greater than a third coefficient of thermal expansion of the package substrate.
Huang et al, in the related art of semiconductor devices that include semiconductor packaging, discloses
wherein a thickness of the first insulation layer (solder mask 10A which includes dielectric material [0107]-[0108] Fig 1A) is smaller than a thickness of the outermost insulation layer (solder mask 10B which includes dielectric material [0107]-[0108] Fig 1A).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Lan et al to include wherein a thickness of the first insulation layer is smaller than a thickness of the outermost insulation layer as taught by Huang et al in order for the package to better utilize the underfill [0042]. Further, a person of ordinary skill in the art would have recognized that the insulating material would provide reinforcement to the underfill and would prevent damage from mechanical stress (see MPEP 2143.I(D)).
The combination of Lan et al and Huang et al now discloses
wherein a thickness of the first insulation layer (SM10A Fig 1A Huang et al) is smaller than a thickness of the outermost insulation layer (SM10B Fig 1A Huang et al),
wherein a first coefficient of thermal expansion of the first insulation layer (SM10A Fig 1A Huang et al) and a second coefficient of thermal expansion of the outermost insulation layer (SM10B Fig 1A Huang et al) are greater than a third coefficient of thermal expansion of the package substrate (portion of 200 shown in annotated Fig 6i Lan et al/dielectric layers D1, D2, D3 and solder mask SMB [0048] Fig 1A Huang et al) (the thermal expansion formula α = δL/(L0(T1-T2)) is well known in the art and it can be observed that the coefficient of thermal expansion α of the thinner layers (smaller L0), SM10A and SM10B, would be greater than the coefficient of thermal expansion α of the thicker substrate (larger L0)).
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Claims 7, 9, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Lan et al (US 2015/0001729) in view of Huang et al (US 2022/0367334), and in further view of Kim et al (US 2022/0352059).
Regarding Claim 7, the combination of Lan et al and Huang et al discloses the limitations of claim 6 as explained above. The combination of Lan et al and Huang et al does not directly disclose
wherein the first coefficient of thermal expansion and the second coefficient of thermal expansion are within a range of 35 ppm/°C to 45 ppm/°C.
Kim et al, in the related art of semiconductor devices that include semiconductor packaging, discloses
wherein the first coefficient of thermal expansion (coefficient of thermal expansion of the first insulating layer 131a [0112] Fig 2) and the second coefficient of thermal expansion (coefficient of expansion of the second insulating layer 132a [0112] Fig 2) are within a range of 35 ppm/°C to 45 ppm/°C (from 7 ppm/degree C to 40 ppm/degree C [0112]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Lan et al and Huang et al to include wherein the first coefficient of thermal expansion and the second coefficient of thermal expansion are within a range of 35 ppm/°C to 45 ppm/°C as taught by Kim et al in order to optimize the thermal expansion such that it avoids a sharp difference in thermal expansion between the insulating layers and a board on which the semiconductor package is mounted to reduce cracks that may occur in the external connection terminal [0110] and because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05).
Regarding Claim 9, the combination of Lan et al and Huang et al discloses the limitations of claim 8 as explained above. The combination of Lan et al and Huang et al does not directly disclose
wherein the fourth coefficient of thermal expansion is within a range of 4 ppm/°C to 7 ppm/°C.
Kim et al, in the related art of semiconductor devices that include semiconductor packaging, discloses
wherein the first coefficient of thermal expansion (coefficient of thermal expansion of the first insulating layer 131a [0112] Fig 2) and the second coefficient of thermal expansion (coefficient of expansion of the second insulating layer 132a [0112] Fig 2) are within a range of 35 ppm/°C to 45 ppm/°C (from 7 ppm/degree C to 40 ppm/degree C [0112]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Lan et al and Huang et al to include wherein the fourth coefficient of thermal expansion is within a range of 4 ppm/°C to 7 ppm/°C as taught by Kim et al in order to optimize the thermal expansion such that it avoids a sharp difference in thermal expansion between the insulating layers and a board on which the semiconductor package is mounted to reduce cracks that may occur in the external connection terminal [0110] and because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05).
The combination of Lan et al, Huang et al, and Kim et al now discloses
wherein the fourth coefficient of thermal expansion (coefficient of thermal expansion for underfill 230 Fig 6i Lan et al) is within a range of 4 ppm/°C to 7 ppm/°C (from 4 ppm/degree C to 7 ppm/degree C [0112] Kim et al).
Regarding Claim 17, the combination of Lan et al and Huang et al discloses the limitations of claim 16 as explained above. The combination of Lan et al and Huang et al does not directly disclose
wherein the first coefficient of thermal expansion and the second coefficient of thermal expansion are within a range of 35 ppm/°C to 45 ppm/°C.
Kim et al, in the related art of semiconductor devices that include semiconductor packaging, discloses
wherein the first coefficient of thermal expansion (coefficient of thermal expansion of the first insulating layer 131a [0112] Fig 2) and the second coefficient of thermal expansion (coefficient of expansion of the second insulating layer 132a [0112] Fig 2) are within a range of 35 ppm/°C to 45 ppm/°C (from 7 ppm/degree C to 40 ppm/degree C [0112]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Lan et al and Huang et al to include wherein the first coefficient of thermal expansion and the second coefficient of thermal expansion are within a range of 35 ppm/°C to 45 ppm/°C as taught by Kim et al in order to optimize the thermal expansion such that it avoids a sharp difference in thermal expansion between the insulating layers and a board on which the semiconductor package is mounted to reduce cracks that may occur in the external connection terminal [0110] and because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05).
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lee et al (US 2018/0122749) which discloses a semiconductor package for a MEMS device [0019], and Uematsu et al (US 2016/0099197) which discloses having a coefficient of thermal expansion of 3 to 10 ppm/K [0037].
Conclusion
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/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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