Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
35 USC 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 9 is rejected under 35 USC 101 for being directed towards non-statutory subject matter.
Claim 9 which is dependent on claim 8, states the computer program can be stored on a computer readable storage medium, however there may be a signal embodied within the computer readable storage medium, which is non-statutory.
35 USC 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 9 are rejected under 35 USC 103 as being unpatentable over Ryu et al. (US Pub. No. 2019/0137776) in view of Ryu et al. (LEE - KR 20210176268 A).
With respect to claim 1, the Ryu et al. reference teaches receiving a set of measured variables from the semiconductor chips of the at least one wafer ([0047] – When the measured sample 310 has a complicated structure, since a variation of each variable in the measurement region influences the reflectance and the phase of the first reflected beam Rp1, a set or a combination of the polarization angles of the first and second polarizers 130 and 510, which influences the variation of each variable and/or the incident beam on the detector 530 most sensitively, may be obtained).
The Ryu et al. reference does not teach defining sub-areas on the at least one wafer, each of which comprises a plurality of semiconductor chips of the at least one wafer for which measured variables have been received, wherein the sub-areas are defined in a circular or grid-like manner; and outputting a set of measured variables which is reduced in comparison with the received set of measured variables and which comprises only the measured variables of subsets of the semiconductor chips of the respective sub-areas, wherein the semiconductor chips of the respective sub-areas whose measured variables are assigned to the reduced set of measured variables are determined at least partially at random.
The LEE reference teaches defining sub-areas on the at least one wafer, each of which comprises a plurality of semiconductor chips of the at least one wafer for which measured variables have been received, wherein the sub-areas are defined in a circular or grid-like manner (page 6, lines 13-20 - determine the alignment status of patterns formed on the overlay keys 200, 200A, and 200B separately from the alignment status of patterns formed on the semiconductor chip region of the wafer. there is. As an example, the semiconductor measuring device includes a first sensor unit for determining alignment of patterns formed in a semiconductor chip region and a second sensor for determining alignment of patterns formed on overlay keys 200, 200A, and 200B); and outputting a set of measured variables which is reduced in comparison with the received set of measured variables and which comprises only the measured variables of subsets of the semiconductor chips of the respective sub-areas, wherein the semiconductor chips of the respective sub-areas whose measured variables are assigned to the reduced set of measured variables are determined at least partially at random (page 6, lines 27-35 - determine the alignment status of patterns formed on the overlay keys 200, 200A, and 200B separately from the alignment status of patterns formed on the semiconductor chip region of the wafer. there is. As an example, the semiconductor measuring device includes a first sensor unit for determining alignment of patterns formed in a semiconductor chip region and a second sensor for determining alignment of patterns formed on overlay keys 200, 200A, and 200B).
Thus, it would have been obvious at a time prior to the effective filing date of Applicant’s claimed invention to have combined the references Ryu et al. and LEE to incorporate the limitations defining sub-areas on the at least one wafer, each of which comprises a plurality of semiconductor chips of the at least one wafer for which measured variables have been received, wherein the sub-areas are defined in a circular or grid-like manner; and outputting a set of measured variables which is reduced in comparison with the received set of measured variables and which comprises only the measured variables of subsets of the semiconductor chips of the respective sub-areas, wherein the semiconductor chips of the respective sub-areas whose measured variables are assigned to the reduced set of measured variables are determined at least partially at random into the claimed invention.
One skilled in the art would have been motivated to by the proposed combination of the Ryu et al. and LEE references for improving the yield (page 4, lines 41-42 - LEE).
With respect to claim 2, all of the limitations of claim 1 have been addressed.
The Ryu et al. reference does not teach wherein the semiconductor chips of the respective sub-areas whose measured variables are assigned to the reduced set of measured variables are determined at least partially according to a predetermined pattern.
The LEE reference teaches wherein the semiconductor chips of the respective sub-areas whose measured variables are assigned to the reduced set of measured variables are determined at least partially according to a predetermined pattern (page 6, lines 27-35 - determine the alignment status of patterns formed on the overlay keys 200, 200A, and 200B separately from the alignment status of patterns formed on the semiconductor chip region of the wafer. there is. As an example, the semiconductor measuring device includes a first sensor unit for determining alignment of patterns formed in a semiconductor chip region and a second sensor for determining alignment of patterns formed on overlay keys 200, 200A, and 200B).
Thus, it would have been obvious at a time prior to the effective filing date of Applicant’s claimed invention to have combined the references Ryu et al. and LEE to incorporate the limitations wherein the semiconductor chips of the respective sub-areas whose measured variables are assigned to the reduced set of measured variables are determined at least partially according to a predetermined pattern into the claimed invention.
One skilled in the art would have been motivated to by the proposed combination of the Ryu et al. and LEE references for improving the yield (page 4, lines 41-42 - LEE).
With respect to claim 3, all of the limitations of claim 1 have been addressed.
The Ryu et al. reference does not teach wherein the sub-areas are defined on the basis of properties of the at least one wafer and/or on the basis of photomask positions and/or exposure schemes from a manufacturing process of the at least one wafer.
The LEE reference teaches wherein the sub-areas are defined on the basis of properties of the at least one wafer and/or on the basis of photomask positions and/or exposure schemes from a manufacturing process of the at least one wafer ([0041] - For example, the detector 530 may be implemented as a charge coupled device (CCD) or a photodiode array (PDA)).
Thus, it would have been obvious at a time prior to the effective filing date of Applicant’s claimed invention to have combined the references Ryu et al. and LEE to incorporate the limitations wherein the sub-areas are defined on the basis of properties of the at least one wafer and/or on the basis of photomask positions and/or exposure schemes from a manufacturing process of the at least one wafer into the claimed invention.
One skilled in the art would have been motivated to by the proposed combination of the Ryu et al. and LEE references for improving the yield (page 4, lines 41-42 - LEE).
With respect to claim 4, all of the limitations of claim 1 have been addressed.
The Ryu et al. reference does not teach wherein a probability distribution for a presence of an anomaly on the at least one wafer is determined and the sub-areas on the at least one wafer are defined as a function of the determined probability distribution.
The LEE reference teaches wherein a probability distribution for a presence of an anomaly on the at least one wafer is determined and the sub-areas on the at least one wafer are defined as a function of the determined probability distribution ([0051] – database of the reflectance graphs may be constructed, e.g., using simulations, and a scanning electron microscope (SEM) or a transmission electron microscope (TEM) using an electron microscope may be used for data verification of the database).
Thus, it would have been obvious at a time prior to the effective filing date of Applicant’s claimed invention to have combined the references Ryu et al. and LEE to incorporate the limitations wherein a probability distribution for a presence of an anomaly on the at least one wafer is determined and the sub-areas on the at least one wafer are defined as a function of the determined probability distribution into the claimed invention.
One skilled in the art would have been motivated to by the proposed combination of the Ryu et al. and LEE references for improving the yield (page 4, lines 41-42 - LEE).
With respect to claim 5, the Ryu et al. reference teaches defining sub-areas on the at least one wafer, each of which comprises a plurality of semiconductor chips of the at least one wafer ([0047] – When the measured sample 310 has a complicated structure, since a variation of each variable in the measurement region influences the reflectance and the phase of the first reflected beam Rp1, a set or a combination of the polarization angles of the first and second polarizers 130 and 510, which influences the variation of each variable and/or the incident beam on the detector 530 most sensitively, may be obtained).
The Ryu et al. reference does not teach measuring only a subset of the semiconductor chips in the respective sub-areas; and outputting a set of measured variables.
The LEE reference teaches measuring only a subset of the semiconductor chips in the respective sub-areas (page 6, lines 13-20 - determine the alignment status of patterns formed on the overlay keys 200, 200A, and 200B separately from the alignment status of patterns formed on the semiconductor chip region of the wafer. there is. As an example, the semiconductor measuring device includes a first sensor unit for determining alignment of patterns formed in a semiconductor chip region and a second sensor for determining alignment of patterns formed on overlay keys 200, 200A, and 200B); and outputting a set of measured variables (page 6, lines 27-35 - determine the alignment status of patterns formed on the overlay keys 200, 200A, and 200B separately from the alignment status of patterns formed on the semiconductor chip region of the wafer. there is. As an example, the semiconductor measuring device includes a first sensor unit for determining alignment of patterns formed in a semiconductor chip region and a second sensor for determining alignment of patterns formed on overlay keys 200, 200A, and 200B).
Thus, it would have been obvious at a time prior to the effective filing date of Applicant’s claimed invention to have combined the references Ryu et al. and LEE to incorporate the limitations defining measuring only a subset of the semiconductor chips in the respective sub-areas; and outputting a set of measured variables into the claimed invention.
One skilled in the art would have been motivated to by the proposed combination of the Ryu et al. and LEE references for improving the yield.
With respect to claim 6, the Ryu et al. reference teaches A method for teaching a machine learning algorithm for anomaly detection with a training data set, provided with at least the method according to claim 1 ([0003] – SE or SR, the thickness of each layer may be measured by comparing a variation in a spectrum of a polarized component reflected from a sample, to a theoretical spectrum obtained through optical simulations, and a variation in the thickness of each layer between before and after a process may be detected without cutting or additionally processing the sample).
With respect to claim 7, the Ryu et al. reference teaches A system for providing wafer test data and/or for teaching a machine learning algorithm, comprising a computing device which is configured to execute at least the method according to claim 1. ([0003] – SE or SR, the thickness of each layer may be measured by comparing a variation in a spectrum of a polarized component reflected from a sample, to a theoretical spectrum obtained through optical simulations, and a variation in the thickness of each layer between before and after a process may be detected without cutting or additionally processing the sample).
With respect to claim 8, the Ryu et al. reference teaches A computer program with program code, comprising instructions which, when the program code is executed by a computer, cause the computer to execute at least the method according to claim 1 ([0051] – database of the reflectance graphs may be constructed, e.g., using simulations, and a scanning electron microscope (SEM) or a transmission electron microscope (TEM) using an electron microscope may be used for data verification of the database).
With respect to claim 9, the Ryu et al. reference teaches A computer-readable storage medium on which the computer program according to claim 8 is stored ([0032] – For example, the sample 310 may be a 3D semiconductor device including a multilayer structure therein, e.g., a vertical-NAND (VNAND) flash memory. However, the type of the sample 310 is not limited to the VNAND flash memory).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Enam Ahmed whose telephone number is 571-270-1729. The examiner can normally be reached on Mon-Fri from 8:30 A.M. to 5:30 P.M.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Albert Decady, can be reached on 571-272-3819.
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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EA
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
6/27/26
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