CTNF 18/659,807 CTNF 72172 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Herein after “it would have been obvious” should be read as “it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention”. Response to Arguments 07-37 AIA Applicant's arguments filed 4/22 /26 have been fully considered but they are not persuasive. In re gards to applicants argument that “MacDonald's factor list does not include the number of cores that are active”. While Pagarkar et al not MacDonald et al was relied on for teaching the number of active cores. MacDonald et al does teach ([0067] “ This performance gain is achieved primarily due to the following observations: (i) when fewer cores are active , they are able to run at higher frequencies ; (ii) certain cores may be allowed to run—or may be capable of running—at higher frequencies than others; and (iii) the TEC 414 cooling capabilities perform better , and realize power headroom benefits, when less than all processor cores are active ”). The claim language as originally presented stated “decrease the voltage applies” … based on … a number of cores that are active. Pagarkar et al was relied upon for teaching (Claim 2: “ obtain a particular voltage value from the voltage table based on the number of processor cores that are online and the frequency of the processor cores; and adjust the rail voltage to the particular voltage value "). The claim language however has been amended to read. “the temperature range selected based on (1) a number of cores that are active” and (2) a first user input” and now only requires “decreasing the voltage” … based on a voltage offset” and increase the frequency of the clock” … “based on a second user input” without any mention of the number of cores or the temperature. MacDonald et al does teach the a ([0062] “ user-specified target minimum and/or maximum temperatures ” [0070] “ user input to specify various overclocking parameters to control the performance/frequency and thermal conditions of the processor ” … “ Moreover, whenever the current processor temperature is less than or equal to the maximum processor temperature specified by the user , the processor may be configured to run at the target frequency and voltage specified by the user ”). A minimum temperature and a maximum temperature together is a user specified temperature range. Applicants amendment removes the reason Pagarkar et al was cited but includes a limitation of “ the temperature range selected based on (1) a number of cores that are active ”. While MacDonald teaches “([0067] “ This performance gain is achieved primarily due to the following observations: (i) when fewer cores are active , they are able to run at higher frequencies ; (ii) certain cores may be allowed to run—or may be capable of running—at higher frequencies than others; and (iii) the TEC 414 cooling capabilities perform better , and realize power headroom benefits, when less than all processor cores are active ”). This only indicates the relationship between temperature and the number of cores it does not expressly teach an operating temperature based on the number of cores active/ Therefore the examiner is citing multiple reference that teach the temperature range is based on the number of active cores such as Bearden et al PN 2011/0191602 ([0056] " In FIG. 7, the Y axis indicates the relationship to operating temperature of an integrated circuit based on the number of cores operating. T4core represents the approximate range in temperature where 4 cores are operating , T3core represents the approximate range in temperature where 3 cores are operating , T2core represents the approximate range in temperature where 2 cores are operating , and T1core represents the approximate range in temperature where 1 core are operating ") . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 39, 41, 43-44, 46, 48-49, 51, 53-54, 56 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cancel PN 2006/0004538 in view of Ragland et al PN 2014/0136823, MacDonald et al PN 2020/0363104, Bacha PN 2014/0281696 and Beardon et al PN 2011/0191602 . In regards to claims 39, 44, 49, 54: Cancel teaches a processor (102) comprising: at least one core ([0014] " More than one processor 102 may be part of system 100 (e.g., a dual processor system, or a dual core processor system) ") to be powered by a voltage (230 "core voltage"), the at least one core to operate at a frequency associated with a clock (clock rate); a sensor to sense a temperature (110) of the at least one core (dual core processor); and circuitry to, based on the sensed temperature being within a temperature range ([0025] " The performance margining range may be a temperature range below the threshold level that allows for the increase in the clock rate of the processing component, and may be predetermined based on the type of processor, listed operating temperatures, and listed processing speed. If the measured temperatures fall within the performance margining range, the processing speed of the component is automatically maximized or increased "): adjust the voltage (230 alter core voltage) applied to the at least one core (core voltage); and increase the frequency of the clock applied to the at least one core (225 " increase clock rate of components "). Cancel only states "alter core voltage” and ([0021] "increase or decrease the CPU core voltage") without an indication of whether the alteration is an increase or a decrease. Ragland et al teaches ([0014] " In general overclocking theory seeks to maximize frequency and minimize voltage/current while removing as much heat as possible such that stability requirements are met " ). It would have been obvious to decrease voltage because overclocking theory seeks to "maximize frequency and minimize voltage". Cancel also does not teach user controlling the voltage and/or frequency or temperature range or the temperature range being based upon the number of active cores. MacDonald et al teaches ([0070] “ When the overclocking mode is active, the TEC 414 may be configured to operate at the maximum cooling level or cooling power. Moreover, whenever the current processor temperature is less than or equal to the maximum processor temperature specified by the user , the processor may be configured to run at the target frequency and voltage specified by the user. Whenever the current processor temperature is greater than the maximum processor temperature specified by the user , however, the processor may be configured to run at a reduced frequency and/or voltage lower than those specified by the user "). It would have been obvious to allow the user to specify the temperature range and voltage/frequency levels because this would have given the user control of the system. Cancel does not state the temperature range is based on the number of cores. Bearden et al teaches ([0056] “ In FIG. 7, the Y axis indicates the relationship to operating temperature of an integrated circuit based on the number of cores operating. T4core represents the approximate range in temperature where 4 cores are operating , T3core represents the approximate range in temperature where 3 cores are operating , T2core represents the approximate range in temperature where 2 cores are operating , and T1core represents the approximate range in temperature where 1 core are operating "). It would have been obvious to have also based the temperature range upon the number of cores because this would have allowed for recognizing the relationship between the number of cores and the temperature. MacDonald teaches the user specifying the voltage as opposed to a voltage offset which is an amount to change the voltage. Bacha teaches ([0025] “ Upon receipt of the successful completion from the core under test, the monarch core, executing the system firmware, may instruct the voltage regulator supplying voltage to the core under test to reduce the voltage. For example, the voltage may be decreased by a set amount , such as 5 millivolts (mV). Once the voltage adjustment is complete, the monarch may instruct the core under test to re-execute the stress test "). It would have been obvious to have the voltage decrease be by a voltage offset because this is basic math. Bacha teaches volatile and non-volatile memories. It would have been obvious to use both volatile and non-volatile memories because volatile memories are faster than non-volatile while non-volatile maintain data when powered off. In regards to claims 41, 46, 51: Cancel teaches thermal thresholds" [0019]. In regards to claims 43, 48, 53: Cancel teaches (Claim 14 "comprising decreasing a clock rate of the CPU based on the thermal margin"). Cancel only expressly teaches returning the frequency to normal. Cancel teaches "normal operation" non-overclocked. It would have been obvious to return the voltage and frequency to normal when the temperature is no longer in range because this would have prevented overheating while providing maximum performance. In regards to claim 56: all of Cancel, Ragland et al, and MacDonald teach stored configurations. Ragland et al [0023] " For example an overclocking lock indicator may be associated with each register or other storage that stores processor performance configuration ") . 07-22-aia AIA Claim (s) 42, 47, 52 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cancel PN 2006/0004538 in view of Ragland et al PN 2014/0136823, MacDonald et al PN 2020/0363104, Bacha PN 2014/0281696 and Beardon et al PN 2011/0191602 as applied to claim 39 above, and further in view of Cerny et al PN 2016/0246343 . In regards to claims 42, 47, 52: Cancel teaches [0020] " A set of performance margining instruction s (e.g., a program) may be encoded in a firmware (e.g., BIOS) or a motherboard utility which includes monitoring the temperature readings from various thermal sensors (e.g., sensors 104, 105) disposed on the motherboard, block 205 ."). These instructions are executed. However Cancel does not state these instructions are "based on a clock rate corresponding to the frequency. Cerny et al teaches ([0020] " The CPU and GPU clocks 156.sub.C, 156.sub.G may be configured to allow the CPU and GPU to execute instructions based on a clock rate that is different from a standard clock rate of the system 100 "). It would have been obvious to execute instructions based on clock rate because this would have allowed more complicated instructions to be executed while at higher frequencies without causing undue delay . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL R MYERS whose telephone number is (571)272-3639. The examiner can normally be reached telework M-F start 7-8 leave 4-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at 571-270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Paul R. MYERS/ Primary Examiner, Art Unit 2176 Application/Control Number: 18/659,807 Page 2 Art Unit: 2176 Application/Control Number: 18/659,807 Page 3 Art Unit: 2176 Application/Control Number: 18/659,807 Page 4 Art Unit: 2176 Application/Control Number: 18/659,807 Page 5 Art Unit: 2176 Application/Control Number: 18/659,807 Page 6 Art Unit: 2176 Application/Control Number: 18/659,807 Page 7 Art Unit: 2176
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