DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
2. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1, 3, 7-9, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Aksin (U.S. Patent No. 11,496,103) in view of Nguyen et al. (U.S. Patent Application Publication No. 2002/0050861 A1).
Regarding claim 1:
Aksin discloses, in Figure 3, an input stage circuit comprising a first input transistor (MP) configured to receive a first portion of a differential input signal (VIP) at a first gate terminal and provide a first portion of an output signal (IOP) at a first drain terminal of the first input transistor, and a second input transistor (MM) configured to receive a second portion of the differential input signal (VIM) at a second gate terminal and provide a second portion of the output signal (IOM) at a second drain terminal of the second input transistor (Fig. 3; see also the description of transconductance circuit 312).
Aksin further discloses a degeneration stage circuit including a first degeneration transistor (MDP) and a second degeneration transistor (MDM). As shown in Figure 3, the source terminal of the first input transistor (MP) is coupled to the source terminal of the first degeneration transistor (MDP); the drain terminal of the first degeneration transistor (MDP) is coupled to the drain terminal of the second degeneration transistor (MDM) at an intermediate node (NCM); and the source terminal of the second degeneration transistor (MDM) is coupled to the source terminal of the second input transistor (MM). Accordingly, the first and second degeneration transistors (MDP and MDM) are coupled in series along a signal path extending between the source terminals of the first and second input transistors (MP and MM), with their respective drain terminals coupled together at the intermediate node (NCM) (Fig.3).
Aksin further discloses that the gate terminal of the first degeneration transistor (MDP) receives the first input voltage (VIP), while the gate terminal of the second degeneration transistor (MDM) receives the second input voltage (VIM). The first and second degeneration transistors (MDP and MDM) function as nonlinear resistors between their respective drain and source terminals. Consequently, the drain-source resistances of the degeneration transistors, and thus the equivalent impedance of the signal path coupling the source terminals of the first and second input transistors (MP and MM), vary according to the voltage difference between the first and second input voltages (VIP and VIM). In particular, the equivalent resistance is smallest when the first and second input voltages (VIP and VIM) are substantially equal and increases as the magnitude of their difference increases (Fig. 3).
For purposes of this and the following rejections, the term “coupled” is given its broadest reasonable interpretation consistent with the specification. The specification does not define “coupled” as requiring a direct connection, and the term is therefore construed as encompassing coupling through intervening circuit elements. See MPEP § 2111.
Aksin does not expressly disclose a bias generator circuit configured to provide respective first and second bias signals to the gate terminals of the first and second degeneration transistors.
However, Nguyen et al. disclose a bias generator circuit comprising a current source (Ios), a control voltage (Vc), and a voltage-offset ladder circuit (8089) formed by offset resistors (Ros1–Ros(n−1)). The current source (Ios) supplies current to the voltage-offset ladder circuit (8089) to generate respective offset-bias signals at different ladder nodes. A first ladder node is coupled to the gate terminal of a first degeneration-control transistor (M1) and provides a first offset-bias signal thereto, while a second ladder node is coupled to the gate terminal of a second degeneration-control transistor (M2) and provides a second offset-bias signal thereto. Nguyen et al. further disclose that the respective gate-bias signals control the channel resistances of the transistors (M1–Mn), thereby varying the equivalent impedance (RE) between the source nodes (n1 and n2) of the differential pair and controlling the transconductance and gain of the amplifier (Fig. 80F; paras. [0856]–[0864]). Accordingly, Nguyen et al.’s current source (Ios), control voltage (Vc), and voltage-offset ladder circuit (8089) collectively teach a bias generator circuit configured to provide respective first and second bias signals to gate terminals of first and second degeneration-control transistors.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Aksin’s degeneration stage circuit by incorporating Nguyen et al.’s voltage-offset bias-generator arrangement to provide respective bias signals to the gate terminals of the first and second degeneration transistors. One of ordinary skill in the art would have been motivated to make this modification to electronically control the degeneration-path impedance and transconductance, thereby providing adjustable gain and improved gain-control linearity, as taught by Nguyen et al.
Regarding claim 3:
Aksin further discloses that the first degeneration transistor (MDP) and the second degeneration transistor (MDM) are arranged in series along the signal path between the source terminals of the first and second input transistors (MP and MM). As shown in Figure 3, the source terminal of the first degeneration transistor (MDP) is coupled to the source terminal of the first input transistor (MP), and the source terminal of the second degeneration transistor (MDM) is coupled to the source terminal of the second input transistor (MM). The drain terminal of the first degeneration transistor (MDP) is directly coupled to the drain terminal of the second degeneration transistor (MDM) at the common node NCM. Because node NCM is located between the first and second degeneration transistors along the signal path, NCM constitutes an intermediate node. Accordingly, Aksin discloses that the drain terminals of the first and second degeneration transistors are coupled at an intermediate node, as required by claim 3 (Fig. 3).
Regarding claim 7:
Aksin discloses a first tail current source (342-1) coupled to the source terminal of the first input transistor (MP) and a second tail current source (342-2) coupled to the source terminal of the second input transistor (MM). As shown in Figure 3, the source terminal of the first degeneration transistor (MDP) is coupled to the first tail current source (342-1) at the source terminal of the first input transistor (MP), while the source terminal of the second degeneration transistor (MDM) is coupled to the second tail current source (342-2) at the source terminal of the second input transistor (MM). The drain terminals of the first and second degeneration transistors (MDP and MDM) are coupled together at the intermediate node (NCM).
Applying the construction of “coupled” set forth above, the first tail current source (342-1) is coupled to the drain terminal of the first degeneration transistor (MDP) through the source-drain conduction path of that transistor, and the second tail current source (342-2) is coupled to the drain terminal of the second degeneration transistor (MDM) through the source-drain conduction path of that transistor. Each tail current source is therefore coupled to the drain terminal of its respective degeneration transistor at the intermediate node (NCM), as recited in claim 7 (Fig. 3).
Regarding claim 8:
Aksin discloses that the first and second tail current sources (342-1 and 342-2) provide respective portions of a total tail current (IT) for the differential pair formed by the first and second input transistors (MP and MM). The first tail current source (342-1) is coupled to the source terminal of the first input transistor (MP) and establishes a first operating current through the first input transistor (MP), while the second tail current source (342-2) is coupled to the source terminal of the second input transistor (MM) and establishes a second operating current through the second input transistor (MM). These respective tail-current signals bias the first and second input transistors (MP and MM) for operation in their respective saturation regions (Fig. 3).
Regarding claim 9:
Aksin discloses a system comprising first and second portions of a transconductance circuit. As shown in Figure 3, the first portion includes a first input transistor (MP) having a gate terminal coupled to a first input node that receives a first portion of a differential input signal (VIP). In response to the first portion of the differential input signal (VIP), the first input transistor (MP) generates a first output current (IOP) at its drain terminal, which constitutes a first output node. The first portion further includes a first degeneration transistor (MDP). The gate terminal of the first degeneration transistor (MDP) receives the same first input signal (VIP) as the gate terminal of the first input transistor (MP) and is therefore coupled to the gate terminal of the first input transistor through the first input node (VIP) (Fig. 3).
Aksin further discloses that the second portion of the transconductance circuit includes a second input transistor (MM) having a gate terminal coupled to a second input node that receives a second portion of the differential input signal (VIM). In response to the second portion of the differential input signal (VIM), the second input transistor (MM) generates a second output current (IOM) at its drain terminal, which constitutes a second output node. The second portion further includes a second degeneration transistor (MDM). The gate terminal of the second degeneration transistor (MDM) receives the same second input signal (VIM) as the gate terminal of the second input transistor (MM) and is therefore coupled to the gate terminal of the second input transistor through the second input node (VIM) (Fig. 3).
Aksin further discloses that the source terminal of the first degeneration transistor (MDP) is coupled to the source terminal of the first input transistor (MP), the source terminal of the second degeneration transistor (MDM) is coupled to the source terminal of the second input transistor (MM), and the drain terminals of the first and second degeneration transistors (MDP and MDM) are coupled together at the intermediate node (NCM). Accordingly, the second degeneration transistor (MDM) is coupled to the first degeneration transistor (MDP), and the two degeneration transistors form a signal path between the respective source terminals of the first and second input transistors (MP and MM) (Fig. 3).
Aksin does not expressly disclose a first bias circuit configured to provide a first bias signal at the gate terminal of the first degeneration transistor and a second bias circuit configured to provide a second bias signal at the gate terminal of the second degeneration transistor.
However, Nguyen et al. disclose a bias generator comprising a current source (Ios), a control voltage (Vc), and a voltage-offset ladder circuit (8089) formed by offset resistors (Ros1–Ros(n−1)). The current source (Ios) supplies current to the voltage-offset ladder circuit (8089), thereby generating respective offset-bias signals at different ladder nodes. A first portion of the voltage-offset ladder circuit provides a first offset-bias signal to the gate terminal of a first degeneration-control transistor (M1), while a second portion of the voltage-offset ladder circuit provides a second offset-bias signal to the gate terminal of a second degeneration-control transistor (M2). These respective portions of the voltage-offset ladder circuit therefore constitute first and second bias circuits configured to provide respective first and second gate-bias signals (Fig. 80F; paras. [0856]–[0860]).
Nguyen et al. further disclose that the respective gate-bias signals control the channel resistances of the transistors (M1–Mn), thereby varying the equivalent impedance (RE) between the source nodes (n1 and n2) of the differential pair and controlling the transconductance and gain of the amplifier (paras. [0861]–[0864]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the control of Aksin’s first and second degeneration transistors (MDP and MDM) by incorporating Nguyen et al.’s voltage-offset bias-generator arrangement to provide respective bias signals at the gate terminals of the first and second degeneration transistors. One of ordinary skill in the art would have been motivated to make this modification to electronically control the channel resistances of the respective degeneration transistors and thereby provide adjustable control of the degeneration-path impedance and the transconductance of the amplifier, including adjustable gain and improved gain-control linearity, as taught by Nguyen et al.
It is further noted that incorporation of the bias arrangement of Nguyen et al. does not sever the coupling between the first input transistor (MP) and the gate terminal of the first degeneration transistor (MDP), or between the second input transistor (MM) and the gate terminal of the second degeneration transistor (MDM). Applying the construction of “coupled” set forth above, each input transistor remains coupled to the gate terminal of its corresponding degeneration transistor through the shared input node and the intervening bias circuit.
Regarding claim 12:
As shown in Figure 3, Aksin discloses a first degeneration transistor (MDP) having a source terminal coupled to the source terminal of the first input transistor (MP) and a second degeneration transistor (MDM) having a source terminal coupled to the source terminal of the second input transistor (MM). The drain terminal of the first degeneration transistor (MDP) and the drain terminal of the second degeneration transistor (MDM) are directly coupled together at the common intermediate node (NCM). Accordingly, the first and second degeneration transistors (MDP and MDM) are coupled to one another at their respective drain terminals, as required by claim 12 (Fig. 3).
4. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Aksin in view of Nguyen et al. as applied to claim 1 above, and further in view of Venkatesan et al. (U.S. Patent No. 10,637,695 B1).
Regarding claim 2:
The combination of Aksin and Nguyen et al. as applied to claim 1 above does not expressly state that the bias generator circuit is configured to provide the first bias signal at a source terminal of the first input transistor and the second bias signal at a source terminal of the second input transistor.
Venkatesan et al. further evidence that biasing at the source terminals of the input transistors of a differential pair was known in the art. Venkatesan et al. disclose a first input transistor (M3+) and a second input transistor (M3−) having respective source nodes (N7+ and N7−), and a first current-source transistor (M4+) and a second current-source transistor (M4−) configured to establish respective biasing conditions at the source nodes (N7+ and N7−) (Fig. 1C; col. 6, lines 39–53). Thus, the first current-source transistor (M4+) provides a first bias signal at the source terminal (N7+) of the first input transistor (M3+), while the second current-source transistor (M4−) provides a second bias signal at the source terminal (N7−) of the second input transistor (M3−).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify the biasing arrangement of Aksin and Nguyen et al. to include the paired current-source arrangement taught by Venkatesan et al., for the purpose of establishing respective biasing conditions at the source terminals of the input transistors while maintaining source degeneration between the source terminals.
5. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Aksin in view of Nguyen et al., as applied to claim 1 above, and further in view of Afsahi et al. (U.S. Patent No. 8,072,270).
Regarding claim 4:
The combination of Aksin and Nguyen et al. does not expressly disclose that the bias generator circuit includes first and second current mirrors coupled to respective input transistors, degeneration transistors, and cascode transistors, wherein the first and second cascode transistors are coupled to the respective drain terminals of the first and second input transistors.
Afsahi et al. is analogous art. Although Afsahi et al. is directed to a radio-frequency power amplifier, it is reasonably pertinent to a problem with which the present inventors were concerned — namely, protecting lower-voltage bias devices from drain-to-source breakdown in an amplifier operating from an elevated supply voltage (see the present specification at para. [0055]) — and would therefore logically have commended itself to the attention of one of ordinary skill in the art in considering that problem. See MPEP § 2141.01(a).
Afsahi et al. disclose bias circuitry (500) including first, second, and third current mirrors (504, 506, and 508) configured to generate a bias voltage for an amplifier circuit (Fig. 5; col. 7, lines 40–67; col. 8, lines 1–39).
Afsahi et al. further disclose a differential amplifier having first and second amplifier branches (702 and 704), wherein the first branch includes a first transconductance stage (706) and a first cascode stage (708), and the second branch includes a second transconductance stage (710) and a second cascode stage (712). The cascode stages receive bias voltages from bias circuitry (714), and the respective cascode stages are coupled in series with the respective transconductance stages at their output sides, such that each cascode stage is coupled to the output-side terminal of the transconductance device of its branch (Fig. 7; col. 10, lines 60–67; see also Figs. 4–6B and col. 7, lines 12–39).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify each of the two corresponding branches of the Aksin and Nguyen et al. circuit to include the mirrored bias and cascode arrangement taught by Afsahi et al. In the resulting combination, the current mirror of each branch is coupled to the input transistor of that branch, to the bias node that drives the gate terminal of the degeneration transistor of that branch, and to the cascode transistor of that branch, and the cascode transistor of each branch is coupled to the drain terminal of the corresponding input transistor. One of ordinary skill in the art would have been motivated to make this modification to provide stable and corresponding bias conditions in the two differential branches, to permit the amplifier to operate from a relatively high supply voltage, and to reduce the drain-to-source voltages sustained by the lower-voltage bias transistors, as expressly taught by Afsahi et al.
6. Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Aksin in view of Nguyen et al. and Afsahi et al., as applied to claim 4 above.
Regarding claim 5:
Aksin discloses that when the first and second portions of the differential input signal (VIP and VIM) are substantially equal in magnitude, substantially equal voltages are applied to the respective gate terminals of the first and second degeneration transistors (MDP and MDM). Under this condition, both degeneration transistors (MDP and MDM) operate in their linear regions and function as nonlinear degeneration resistors having their smallest equivalent resistance. Because the degeneration transistors are coupled in series between the source nodes (NCMP and NCMM) of the input transistors (MP and MM), this minimum equivalent resistance establishes a low-impedance signal path through the degeneration-stage circuit between the source nodes (NCMP and NCMM) (Fig. 3).
Regarding claim 6:
Aksin discloses that when the first and second portions of the differential input signal (VIP and VIM) are not substantially equal in magnitude, the degeneration transistor receiving the lower input voltage operates in its saturation region, while the complementary degeneration transistor remains in its linear region. For example, when the first input voltage (VIP) is lower than the second input voltage (VIM), the first degeneration transistor (MDP) operates in its saturation region and the second degeneration transistor (MDM) remains in its linear region. Operation of one degeneration transistor in saturation increases the equivalent resistance of the series-connected degeneration transistors between the source nodes (NCMP and NCMM), thereby establishing a high-impedance signal path through the degeneration-stage circuit (Fig. 3).
7. Claims 17, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Aksin in view of Nguyen et al. and further in view of Venkatesan et al.
Regarding claim 17:
Aksin discloses receiving a first input-stage input signal (VIP) at the gate terminal of a first input transistor (MP) and receiving a second input-stage input signal (VIM) at the gate terminal of a second input transistor (MM). In response to the respective input-stage input signals (VIP and VIM), the first and second input transistors (MP and MM) generate respective first and second input-stage output-current signals (IOP and IOM) at their corresponding drain terminals (Fig. 3).
Aksin further discloses first and second degeneration transistors (MDP and MDM) disposed in a signal path between the source terminals of the first and second input transistors (MP and MM). The source terminal of the first degeneration transistor (MDP) is coupled to the source terminal of the first input transistor (MP), the source terminal of the second degeneration transistor (MDM) is coupled to the source terminal of the second input transistor (MM), and the drain terminals of the degeneration transistors are coupled together at the intermediate node (NCM). The gate terminals of the first and second degeneration transistors (MDP and MDM) receive the respective input signals (VIP and VIM). Consequently, their drain-source resistances, and thus the equivalent impedance of the signal path between the source terminals of the input transistors, vary according to the difference between the input signals. The equivalent impedance is smallest when the input signals (VIP and VIM) are substantially equal and increases as the magnitude of their difference increases (Fig. 3).
Aksin does not expressly disclose using a first bias circuit to provide a first bias signal both to a gate terminal of a first degeneration transistor and to a source terminal of the first input transistor, or using a second bias circuit to provide a second bias signal both to a gate terminal of a second degeneration transistor and to a source terminal of the second input transistor.
However, Nguyen et al. disclose a bias generator comprising a current source (Ios), a control voltage (Vc), and a voltage-offset ladder circuit (8089) formed by offset resistors (Ros1–Ros(n−1)). The voltage-offset ladder circuit (8089) generates respective offset-bias signals at different ladder nodes. A first ladder node provides a first gate-bias signal to a first degeneration-control transistor (M1), while a second ladder node provides a second gate-bias signal to a second degeneration-control transistor (M2). The respective gate-bias signals control the channel resistances of the transistors (M1–Mn), thereby varying the equivalent impedance (RE) between the source nodes (n1 and n2) of the differential pair and controlling the transconductance and gain of the amplifier (Fig. 80F; paras. [0856]–[0864]).
Venkatesan et al. further evidence that establishing a bias condition at the source terminal of an input transistor of a differential pair was known in the art. Venkatesan et al. disclose a first current-source transistor (M4+) coupled to a source terminal (N7+) of a first input transistor (M3+) and a second current-source transistor (M4−) coupled to a source terminal (N7−) of a second input transistor (M3−). The first current-source transistor (M4+) establishes a first source-bias signal at the source terminal (N7+) of the first input transistor (M3+), while the second current-source transistor (M4−) establishes a second source-bias signal at the source terminal (N7−) of the second input transistor (M3−) (Fig. 1C; col. 6, lines 39–53).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to perform Aksin’s method using Nguyen et al.’s respective gate-bias control signals and Venkatesan et al.’s respective source-bias arrangement. One of ordinary skill in the art would have been motivated to make this modification to electronically control the degeneration-path impedance while establishing desired operating conditions at the source terminals of the input transistors, thereby providing adjustable transconductance and gain.
Regarding claim 19:
In the combination of Aksin and Nguyen et al. as applied to claim 17 above, the first and second bias signals are applied to the gate terminals of the first and second degeneration transistors (MDP and MDM), whose source terminals are coupled to the respective source nodes (NCMP and NCMM) of the first and second input transistors (MP and MM). The first bias signal and the voltage at the first source node (NCMP) together establish the gate-to-source voltage of the first degeneration transistor (MDP), and the second bias signal and the voltage at the second source node (NCMM) together establish the gate-to-source voltage of the second degeneration transistor (MDM).
When the first and second bias signals exceed the applicable threshold voltages of the respective degeneration transistors, both degeneration transistors conduct in their linear regions and the signal path coupling the source terminals of the first and second input transistors exhibits a lower impedance characteristic. When at least one of the first and second bias signals does not exceed the applicable threshold voltage of its corresponding degeneration transistor, conduction through that transistor is reduced and the signal path coupling the source terminals of the first and second input transistors exhibits a higher impedance characteristic (Aksin, Fig. 3; Nguyen et al., paras. [0861]–[0864]).
Regarding claim 20:
Aksin discloses receiving the first and second input-stage input signals (VIP and VIM) at the respective gate terminals of the first and second input transistors (MP and MM). As shown in Figure 3, the first input transistor (MP) and the second input transistor (MM) form the differential input pair of the transconductance circuit (312), and their respective drain terminals provide the first and second input-stage output-current signals (IOP and IOM). Aksin further identifies the first and second input transistors (MP and MM) as respective laterally diffused metal-oxide-semiconductor (LDMOS) devices configured to accommodate the high-voltage input range of the transconductance circuit. Accordingly, the first and second input-stage input signals (VIP and VIM) are received at the respective gate terminals of first and second LDMOS input transistors (MP and MM) (Fig. 3; see also the description of transconductance circuit 312).
Allowable Subject Matter
8. Claims 10, 11, 13–16, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 10, none of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
wherein the first bias circuit comprises a voltage source configured to provide the first bias signal at the gate terminal of the first degeneration transistor and a source terminal of the first input transistor.
Regarding claim 13, none of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
wherein the first bias circuit comprises a current mirror coupled between gate and source terminals of the first degeneration transistor.
Regarding claim 18, none of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims:
comprising receiving the first and second input stage input signals at respective first and second cascode transistors, wherein the first cascode transistor is coupled between the first output terminal and the first bias circuit, and wherein the second cascode transistor is coupled between the second output terminal and the second bias circuit.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SIAM SADMAN whose telephone number is (571)270-0921. The examiner can normally be reached Monday through Thursday from 8:00 a.m. to 4:00 p.m.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han, can be reached at telephone number 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S.S./Examiner, Art Unit 2843
/Jessica Han/Supervisory Patent Examiner, Art Unit 2843
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