DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1, 11 and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-7 and 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0284323 to Neugebauer et al.; in view of US 6,282,625 to Porterfield; in view of US 2013/0227198 to Lee; further in view of US 2011/0252187 to Segal et al.
As per claim 1, Neugebauer et al. teach a display device, comprising:
a display panel including a plurality of subpixels (paragraph 13);
a flash memory system (Fig. 3, Flash Memory)
a timing controller configured to control data reading operation and data writing operation of the memory system (paragraph 64, the means for performing the read/write operations will be construed as the timing controller),
a data processor (Fig. 3, 301)
Neugebauer et al. do not explicitly teach the memory system configured to process input data in unit of sector.
Porterfield teaches the memory system configured to process input data in unit of sector (column 7, line 64 – column 8, line 14, “the virtual page number field 204 comprises the upper 20 bits and the offset field 206 comprises the lower 12 bits of a 32 bit virtual address 200. Thus, each page includes 2.sup.12 =4096 (4K) addresses and the lower 12 bits of the offset field 206 locate the desired information within a page referenced by the upper 20 bits of the virtual page number field 204”).
It would have been obvious to one of ordinary skill in the art, to modify the device of Neugebauer et al., so that the memory system is configured to process input data in unit of sector, such as taught by Porterfield, for the purpose of optimizing memory space.
Neugebauer and Porterfied et al. do not necessarily teach the data processor configured to maintain sector data already stored in a first area within a sector and store the input data in a second area within the sector, based on an address of the input data, wherein the sector has a fixed size between a starting point and an end point.
Lee teaches the data processor configured to maintain sector data already stored in a first area within a sector (Figs. 7 and 9, data 1-7 is maintained/padded onto a buffer before writing into sector areas 1-7) and store the input data in a second area within the sector (Figs. 7 and 9, new data 8-15 is stored in a buffer before writing into sector areas 8-15), based on an address of the input data (paragraph 32, “Through an address mapping algorithm, the controller 102, which comprises hardware such as a processor or microprocessor, controls data read/write operations and the like between the data register 108 temporarily storing data and the plurality of NAND flash arrays 106”), wherein the sector has a fixed size between a starting point and an end point (Figs. 7-9, data blocks are stored into pages of the memory, each of said pages comprises 15 sectors (1-15), it is implicitly disclosed wherein the size of each of said sectors = page size / 16, see also paragraph 65, for example, “the NAND flash memory device records new data in sectors 8 to 15 of a buffer 700 and then, reads (730) data from sectors 0 to 7”).
It would have been obvious to one of ordinary skill in the art, to modify the device of Neugebauer and Porterfield et al., so that the data processor is configured to maintain sector data already stored in a first area within a sector and store the input data in a second area within the sector, based on an address of the input data, wherein the sector has a fixed size between a starting point and an end point, such as taught by Lee, for the purpose of optimizing memory space.
Neugebauer, Porterfield and Lee et al. do not explicitly teach wherein only a portion of the input data is written in the second area.
Segal et al. teach wherein only a portion of the input data is written in the second area (paragraph 32, “if the data stream has a data size different than an integer number of pages 124, the data may have a remaining dataset that only partially fills a page 124 and the operation to write the data to MLC memory blocks 110 may be referred to as a partial write operation”, in other words, instead of the entirety of the input data, only a remaining portion of said input data is written into the second area using a partial write operation. The Office respectfully submits that said partial write operation of the remaining dataset is analogous to the write operation performed by Lee).
It would have been obvious to one of ordinary skill in the art, to modify the device of Neugebauer, Porterfield and Lee et al., so that only a portion of the input data is written in the second area, such as taught by Segal et al., for the purpose of operating with input data datasets that are both larger than the physical page size and a non-0integer multiple of said page size.
As per claim 3, Neugebauer, Porterfield, Lee and Segal et al. teach the display device of claim 1, wherein the sector has a fixed size of 4KB (Porterfield, column 7, line 64 – column 8, line 14, “these processors may include PTEs referencing 4K pages”, when the unit memory address is a byte, 4K pages = 4 KB; Lee, Figs. 7-9, data blocks are stored into pages of the memory, each of said pages comprises 15 sectors (1-15), it is implicitly disclosed wherein the size of each of said sectors = page size / 16, see also paragraph 65, for example, “the NAND flash memory device records new data in sectors 8 to 15 of a buffer 700 and then, reads (730) data from sectors 0 to 7”).
As per claim 4, Neugebauer, Porterfield, Lee and Segal et al. teach the display device of claim 1, wherein the address of the input data includes: a location digit corresponding to a location of the sector; and a size digit corresponding to the fixed size of the sector (Porterfield, column 7, line 64 – column 8, line 14, “the virtual page number field 204 comprises the upper 20 bits and the offset field 206 comprises the lower 12 bits of a 32 bit virtual address 200. Thus, each page includes 2.sup.12 =4096 (4K) addresses and the lower 12 bits of the offset field 206 locate the desired information within a page referenced by the upper 20 bits of the virtual page number field 204”).
As per claim 5, Neugebauer, Porterfield, Lee and Segal et al. teach the display device of claim 4, wherein the address of the input data consists of 8 hexadecimal digits, the location digit is upper 5 digits of the 8 hexadecimal digits, and the size digit is lower 3 digits of the 8 hexadecimal digits (Porterfield, column 7, line 64 – column 8, line 14, “the virtual page number field 204 comprises the upper 20 bits and the offset field 206 comprises the lower 12 bits of a 32 bit virtual address 200. Thus, each page includes 2.sup.12 =4096 (4K) addresses and the lower 12 bits of the offset field 206 locate the desired information within a page referenced by the upper 20 bits of the virtual page number field 204”).
As per claim 6, Neugebauer, Porterfield, Lee and Segal et al. teach the display device of claim 1, wherein the data processor includes:
a data input unit configured to receive the input data (Lee, Fig. 7, means for receiving new data);
an address input unit configured to receive the address of the input data (Porterfield, column 7, line 64 – column 8, line 14, “the virtual page number field 204 comprises the upper 20 bits and the offset field 206 comprises the lower 12 bits of a 32 bit virtual address 200. Thus, each page includes 2.sup.12 =4096 (4K) addresses and the lower 12 bits of the offset field 206 locate the desired information within a page referenced by the upper 20 bits of the virtual page number field 204”, means for receiving upper and lower address bits);
an address counter configured to determine the first area and the second area using the address of the input data (Porterfield, column 7, line 64 – column 8, line 14, “the virtual page number field 204 comprises the upper 20 bits and the offset field 206 comprises the lower 12 bits of a 32 bit virtual address 200. Thus, each page includes 2.sup.12 =4096 (4K) addresses and the lower 12 bits of the offset field 206 locate the desired information within a page referenced by the upper 20 bits of the virtual page number field 204”, means for decomposing received bits onto upper and lower addresses);
a reading buffer configured to transmit the sector data supplied from the memory system (Lee, Fig. 7, sector data 1-7 is transmitted from an existing block into buffer 700 and received from buffer 700 by a temporary block 720);
a switching circuit configured to transmit the input data or the sector data according to control of the address counter (Lee, Fig. 7, 740, paragraph 65, “the NAND flash memory device writes all the data of the buffer 700 into a temporary block 720”); and
a writing buffer configured to write data transmitted from the switching circuit to the memory system (Lee, Fig. 5 and 7, paragraph 54, “the existing physical block 0 is replaced with the temporary block”, in other words, data write is finalized by moving the data in the temporary block onto a final physical memory block).
As per claim 7, Neugebauer, Porterfield, Lee and Segal et al. teach the display device of claim 6, wherein the data processor further includes a concatenator configured to combine the sector data in unit of sector extracted from the memory system and transmit the sector data to the reading buffer (Lee, Fig. 7, the means for merging the sector data 1-7 with the new data 8-15 will be construed as the claimed concatenator).
As per claim 10, Neugebauer, Porterfield, Lee and Segal et al. teach the display device of claim 1, wherein the data processor (Neugebauer, 301) is positioned within the timing controller (Neugebauer, 300/301/302/304).
As per claim 11, Neugebauer et al. teach a data processor (Fig. 3, 301) incorporated to a memory system processing data in unit of sector.
Neugebauer et al. do not teach an address input unit configured to receive an address of the input data, an address counter configured to determine a first area of a sector for maintaining sector data already stored in the sector of the memory system and a second area of the sector for writing the input data based on the address of the input data.
Porterfield teaches an address input unit configured to receive an address of the input data; (column 7, line 64 – column 8, line 14, “the virtual page number field 204 comprises the upper 20 bits and the offset field 206 comprises the lower 12 bits of a 32 bit virtual address 200. Thus, each page includes 2.sup.12 =4096 (4K) addresses and the lower 12 bits of the offset field 206 locate the desired information within a page referenced by the upper 20 bits of the virtual page number field 204”, means for receiving upper and lower address bits).
an address counter configured to determine a first area of a sector for maintaining sector data already stored in the sector of the memory system and a second area of the sector for writing the input data based on the address of the input data; (column 7, line 64 – column 8, line 14, “the virtual page number field 204 comprises the upper 20 bits and the offset field 206 comprises the lower 12 bits of a 32 bit virtual address 200. Thus, each page includes 2.sup.12 =4096 (4K) addresses and the lower 12 bits of the offset field 206 locate the desired information within a page referenced by the upper 20 bits of the virtual page number field 204”, means for decomposing received bits onto upper and lower addresses).
It would have been obvious to one of ordinary skill in the art, to modify the device of Neugebauer et al., to include an address input unit configured to receive an address of the input data, an address counter configured to determine a first area of a sector for maintaining sector data already stored in the sector of the memory system and a second area of the sector for writing the input data based on the address of the input data, such as taught by Porterfield, for the purpose of optimizing memory space.
Neugebauer and Porterfield et al. do not teach a data input unit configured to receive an input data, a reading buffer configured to transmit the sector data supplied from the memory system, a switching circuit configured to transmit the input data or the sector data according to control of the address counter, a writing buffer configured to write data transmitted from the switching circuit to the memory system, wherein the sector has a fixed size between a starting point and an end point.
Lee teaches a data input unit configured to receive an input data; (Lee, Fig. 7, means for receiving new data);
a reading buffer configured to transmit the sector data supplied from the memory system; (Lee, Fig. 7, sector data 1-7 is transmitted from an existing block into buffer 700 and received from buffer 700 by a temporary block 720)
a switching circuit configured to transmit the input data or the sector data according to control of the address counter; (Lee, Fig. 7, 740, paragraph 65, “the NAND flash memory device writes all the data of the buffer 700 into a temporary block 720”)
a writing buffer configured to write data transmitted from the switching circuit to the memory system (Lee, Fig. 5 and 7, paragraph 54, “the existing physical block 0 is replaced with the temporary block”, in other words, data write is finalized by moving the data in the temporary block onto a final physical memory block) , wherein the sector has a fixed size between a starting point and an end point (Figs. 7-9, data blocks are stored into pages of the memory, each of said pages comprises 15 sectors (1-15), it is implicitly disclosed wherein the size of each of said sectors = page size / 16, see also paragraph 65, for example, “the NAND flash memory device records new data in sectors 8 to 15 of a buffer 700 and then, reads (730) data from sectors 0 to 7”).
It would have been obvious to one of ordinary skill in the art, to modify the device of Neugebauer and Porterfield et al., by including a data input unit configured to receive an input data, a reading buffer configured to transmit the sector data supplied from the memory system, a switching circuit configured to transmit the input data or the sector data according to control of the address counter, a writing buffer configured to write data transmitted from the switching circuit to the memory system, so that the sector has a fixed size between a starting point and an end point, such as taught by Lee, for the purpose of optimizing memory space.
Neugebauer, Porterfield and Lee et al. do not explicitly teach wherein only a portion of the input data is written in the second area.
Segal et al. teach wherein only a portion of the input data is written in the second area (paragraph 32, “if the data stream has a data size different than an integer number of pages 124, the data may have a remaining dataset that only partially fills a page 124 and the operation to write the data to MLC memory blocks 110 may be referred to as a partial write operation”, in other words, instead of the entirety of the input data, only a remaining portion of said input data is written into the second area using a partial write operation. The Office respectfully submits that said partial write operation of the remaining dataset is analogous to the write operation performed by Lee).
It would have been obvious to one of ordinary skill in the art, to modify the device of Neugebauer, Porterfield and Lee et al., so that only a portion of the input data is written in the second area, such as taught by Segal et al., for the purpose of operating with input data datasets that are both larger than the physical page size and a non-0integer multiple of said page size.
As per claim 12, Neugebauer, Porterfield, Lee and Segal et al. teach the data processor of claim 11, further includes a concatenator configured to combine the sector data in unit of sector extracted from the flash memory system and transmit the sector data to the reading buffer (Lee, Fig. 7, the means for merging the sector data 1-7 with the new data 8-15 will be construed as the claimed concatenator).
Claims 8, 9, 13 and 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0284323 to Neugebauer et al.; in view of US 6,282,625 to Porterfield; in view of US 2013/0227198 to Lee; further in view of US 2011/0252187 to Segal et al.; in view of US 2021/0255977 to Kiyota et al.
As per claim 8, Neugebauer, Porterfield, Lee and Segal et al. teach the display device of claim 6.
Neugebauer, Porterfield, Lee and Segal et al. do not explicitly disclose wherein the address counter is configured to generate: a global count indicating a number of sectors for processing data by comparing a start address and an end address of the input data; a front count indicating a range between a starting point of the sector and the start address; a rear count indicating a range between the end address and an end point of the sector; and a write count indicating the second area.
Kiyota et al. teach wherein the address counter is configured to generate:
a global count (paragraph 35, “transfer unit size”) indicating a number of sectors for processing data by comparing a start address (paragraph 49, “destination address”) and an end address of the input data (paragraph 49, notice that given 2 parameters, chosen out of 3 including either: start address, termination address and data transfer size, the calculation of the 3rd parameter for a transfer of contiguous data is a trivial mathematical operation considering the memory architecture. In other words, given start and termination address, calculating the data size/number of sectors, is a trivial mathematical operation; given a start address and transfer size, calculating a termination address, is a trivial mathematical operation; given a termination address and transfer size, calculating a start address, is a trivial mathematical operation);
a front count indicating a range between a starting point of the sector and the start address (Fig. 2, paragraph 35, “56 bytes of a head in the transfer of the data 10B”; paragraph 49, “a destination address, and a transfer size are designated as transfer parameters”, in other words, given 2 out of 3 linear parameters, a calculation of a 3rd parameter is a trivial mathematical operation);
a rear count indicating a range between the end address and an end point of the sector (Fig. 2, paragraph 35, “16 bytes of a tail in the transfer of the data 10B”; paragraph 49, “a destination address, and a transfer size are designated as transfer parameters”, in other words, given 2 out of 3 linear parameters, a calculation of a 3rd parameter is a trivial mathematical operation); and
a write count indicating the second area (Fig. 2, paragraph 35, “56 bytes of a head in the transfer of the data 10B … 16 bytes of a tail in the transfer of the data 10B”; paragraph 49, “a destination address, and a transfer size are designated as transfer parameters”, in other words, given 2 out of 3 linear parameters, a calculation of a 3rd parameter is a trivial mathematical operation).
It would have been obvious to one of ordinary skill in the art, to modify the device of Neugebauer, Porterfield, Lee and Segal et al., so that the address counter is configured to generate: a global count indicating a number of sectors for processing data by comparing a start address and an end address of the input data; a front count indicating a range between a starting point of the sector and the start address; a rear count indicating a range between the end address and an end point of the sector; and a write count indicating the second area, such as taught by Kiyota et al., for the purpose of optimizing memory access utilization.
As per claim 9, Neugebauer, Porterfield, Lee, Segal and Kiyota teach the display device of claim 8, wherein the front count and the rear count indicate the first area (Fig. 2, paragraph 35, “16 bytes of a tail in the transfer of the data 10B”; paragraph 49, “a destination address, and a transfer size are designated as transfer parameters”, in other words, given 2 out of 3 linear parameters, a calculation of a 3rd parameter is a trivial mathematical operation).
As per claim 13, Neugebauer, Porterfield, Lee and Segal et al. teach the data processor of claim 11.
Neugebauer, Porterfield, Lee and Segal et al. do not teach wherein the address counter generates: a global count indicating a number of sectors for processing data by comparing a start address and an end address of the input data; a front count indicating a range between a starting point of the sector and the start address; a rear count indicating a range between the end address and an end point of the sector; and a write count indicating the second area.
Kiyota et al. teach wherein the address counter generates:
a global count (paragraph 35, “transfer unit size”) indicating a number of sectors for processing data by comparing a start address (paragraph 49, “destination address”) and an end address of the input data (paragraph 49, notice that given 2 parameters, chosen out of 3 including either: start address, termination address and data transfer size, the calculation of the 3rd parameter for a transfer of contiguous data is a trivial mathematical operation considering the memory architecture. In other words, given start and termination address, calculating the data size/number of sectors, is a trivial mathematical operation; given a start address and transfer size, calculating a termination address, is a trivial mathematical operation; given a termination address and transfer size, calculating a start address, is a trivial mathematical operation);
a front count indicating a range between a starting point of the sector and the start address (Fig. 2, paragraph 35, “56 bytes of a head in the transfer of the data 10B”; paragraph 49, “a destination address, and a transfer size are designated as transfer parameters”, in other words, given 2 out of 3 linear parameters, a calculation of a 3rd parameter is a trivial mathematical operation);
a rear count indicating a range between the end address and an end point of the sector (Fig. 2, paragraph 35, “16 bytes of a tail in the transfer of the data 10B”; paragraph 49, “a destination address, and a transfer size are designated as transfer parameters”, in other words, given 2 out of 3 linear parameters, a calculation of a 3rd parameter is a trivial mathematical operation); and
a write count indicating the second area (Fig. 2, paragraph 35, “56 bytes of a head in the transfer of the data 10B … 16 bytes of a tail in the transfer of the data 10B”; paragraph 49, “a destination address, and a transfer size are designated as transfer parameters”, in other words, given 2 out of 3 linear parameters, a calculation of a 3rd parameter is a trivial mathematical operation).
It would have been obvious to one of ordinary skill in the art, to modify the device of Neugebauer, Porterfield, Lee and Segal et al., so that the address counter is configured to generate: a global count indicating a number of sectors for processing data by comparing a start address and an end address of the input data; a front count indicating a range between a starting point of the sector and the start address; a rear count indicating a range between the end address and an end point of the sector; and a write count indicating the second area, such as taught by Kiyota et al., for the purpose of optimizing memory access utilization.
As per claim 14, Neugebauer, Porterfield, Lee, Segal and Kiyota et al. teach the data processor of claim 13, wherein the front count and the rear count indicate the first area (Fig. 2, paragraph 35, “56 bytes of a head in the transfer of the data 10B … 16 bytes of a tail in the transfer of the data 10B”; paragraph 49, “a destination address, and a transfer size are designated as transfer parameters”, in other words, given 2 out of 3 linear parameters, a calculation of a 3rd parameter is a trivial mathematical operation).
As per claim 15, Neugebauer teaches a data processing method of a display device (Fig. 3).
Neugebauer does not explicitly teach the method comprising receiving input data and an address, determining a location digit and a size digit of the address using sector information of a memory system, determining a location digit and a size digit of the address using sector information of a memory system, the processing data including maintaining sector data already stored in a first area within a sector and writing input data in a second area within the sector based on an address of the input data.
Porterfield teaches receiving input data and an address (column 7, line 64 – column 8, line 14, “the virtual page number field 204 comprises the upper 20 bits and the offset field 206 comprises the lower 12 bits of a 32 bit virtual address 200. Thus, each page includes 2.sup.12 =4096 (4K) addresses and the lower 12 bits of the offset field 206 locate the desired information within a page referenced by the upper 20 bits of the virtual page number field 204”, means for receiving upper and lower address bits)
determining a location digit and a size digit of the address using sector information of a memory system, the processing data including maintaining sector data already stored in a first area within a sector and writing input data in a second area within the sector based on an address of the input data (column 7, line 64 – column 8, line 14, “the virtual page number field 204 comprises the upper 20 bits and the offset field 206 comprises the lower 12 bits of a 32 bit virtual address 200. Thus, each page includes 2.sup.12 =4096 (4K) addresses and the lower 12 bits of the offset field 206 locate the desired information within a page referenced by the upper 20 bits of the virtual page number field 204”, means for decomposing received bits onto upper and lower digits)
It would have been obvious to one of ordinary skill in the art, to modify the device of Neugebauer et al., by receiving input data and an address, determining a location digit and a size digit of the address using sector information of a memory system, determining a location digit and a size digit of the address using sector information of a memory system, the processing data including maintaining sector data already stored in a first area within a sector and writing input data in a second area within the sector based on an address of the input data such as taught by Porterfield, for the purpose of optimizing memory space.
Neugebauer and Porterfied et al. do not explicitly teach processing data in unit of sector which has a fixed size between a starting point and an end point.
Lee teaches processing data in unit of sector which has a fixed size between a starting point and an end point (Figs. 7-9, data blocks are stored into pages of the memory, each of said pages comprises 15 sectors (1-15), it is implicitly disclosed wherein the size of each of said sectors = page size / 16, see also paragraph 65, for example, “the NAND flash memory device records new data in sectors 8 to 15 of a buffer 700 and then, reads (730) data from sectors 0 to 7”).
It would have been obvious to one of ordinary skill in the art, to modify the device of Neugebauer and Porterfield et al., so that the data processor is configured to maintain sector data stored in a first area within a sector and store the input data in a second area within the sector, based on an address of the input data, and processing data in unit of sector which has a fixed size between a starting point and an end point, such as taught by Lee, for the purpose of optimizing memory space.
Neugebauer, Porterfield and Lee et al. do not explicitly teach wherein only a portion of the input data is written in the second area.
Segal et al. teach wherein only a portion of the input data is written in the second area (paragraph 32, “if the data stream has a data size different than an integer number of pages 124, the data may have a remaining dataset that only partially fills a page 124 and the operation to write the data to MLC memory blocks 110 may be referred to as a partial write operation”, in other words, instead of the entirety of the input data, only a remaining portion of said input data is written into the second area using a partial write operation. The Office respectfully submits that said partial write operation of the remaining dataset is analogous to the write operation performed by Lee).
It would have been obvious to one of ordinary skill in the art, to modify the device of Neugebauer, Porterfield and Lee., so that only a portion of the input data is written in the second area, such as taught by Segal et al., for the purpose of operating with input data datasets that are both larger than the physical page size and a non-integer multiple of said page size.
Neugebauer, Porterfield, Lee and Segal et al. do not teach extracting count information for processing data in unit of sector corresponding to the input data; and processing data in unit of sector using the count information.
Kiyota et al. teach extracting count information for processing data in unit of sector corresponding to the input data; and processing data in unit of sector using the count information (Fig. 2, paragraph 35, “56 bytes of a head in the transfer of the data 10B … 16 bytes of a tail in the transfer of the data 10B”; paragraph 49, “a destination address, and a transfer size are designated as transfer parameters”, in other words, given 2 out of 3 linear parameters, a calculation of a 3rd parameter is a trivial mathematical operation).
It would have been obvious to one of ordinary skill in the art, to modify the device of Neugebauer, Porterfield, Lee and Segal, by extracting count information for processing data in unit of sector corresponding to the input data; and processing data in unit of sector using the count information, such as taught by Kiyota et al., for the purpose of improving memory space utilization.
As per claim 16, Neugebauer, Porterfield, Lee, Segal and Kiyota et al. teach the data processing method of claim 15, wherein the address of the input data consists of 8 hexadecimal digits, the location digit is upper 5 digits of the 8 hexadecimal digits, and the size digit is lower 3 digits of the 8 hexadecimal digits (Porterfield, column 7, line 64 – column 8, line 14, “the virtual page number field 204 comprises the upper 20 bits and the offset field 206 comprises the lower 12 bits of a 32 bit virtual address 200. Thus, each page includes 2.sup.12 =4096 (4K) addresses and the lower 12 bits of the offset field 206 locate the desired information within a page referenced by the upper 20 bits of the virtual page number field 204”, means for receiving upper and lower address bits).
As per claim 17, Neugebauer, Porterfield, Lee, Segal and Kiyota et al. teach the data processing method of claim 15, wherein the count information includes: a global count (Kiyota, paragraph 35, “transfer unit size”) indicating a number of sectors for processing data by comparing a start address (Kiyota, paragraph 49, “destination address”) and an end address of the input data (Kiyota, paragraph 49, notice that given 2 parameters, chosen out of 3 including either: start address, termination address and data transfer size, the calculation of the 3rd parameter for a transfer of contiguous data is a trivial mathematical operation considering the memory architecture. In other words, given start and termination address, calculating the data size/number of sectors, is a trivial mathematical operation; given a start address and transfer size, calculating a termination address, is a trivial mathematical operation; given a termination address and transfer size, calculating a start address, is a trivial mathematical operation);
a front count indicating a range between a starting point of the sector and the start address (Kiyota, Fig. 2, paragraph 35, “56 bytes of a head in the transfer of the data 10B”; paragraph 49, “a destination address, and a transfer size are designated as transfer parameters”, in other words, given 2 out of 3 linear parameters, a calculation of a 3rd parameter is a trivial mathematical operation);
a rear count indicating a range between the end address and an end point of the sector (Kiyota, Fig. 2, paragraph 35, “16 bytes of a tail in the transfer of the data 10B”; paragraph 49, “a destination address, and a transfer size are designated as transfer parameters”, in other words, given 2 out of 3 linear parameters, a calculation of a 3rd parameter is a trivial mathematical operation); and
a write count indicating an area for writing the input data (Kiyota, Fig. 2, paragraph 35, “56 bytes of a head in the transfer of the data 10B … 16 bytes of a tail in the transfer of the data 10B”; paragraph 49, “a destination address, and a transfer size are designated as transfer parameters”, in other words, given 2 out of 3 linear parameters, a calculation of a 3rd parameter is a trivial mathematical operation).
As per claim 18, Neugebauer, Porterfield, Lee, Segal and Kiyota et al. teach the data processing method of claim 17, wherein the front count and the rear count indicate an area for maintaining data in the sector (Kiyota, Fig. 2, paragraph 35, “56 bytes of a head in the transfer of the data 10B … 16 bytes of a tail in the transfer of the data 10B”, in other words, given 2 out of 3 linear parameters, a calculation of a 3rd parameter is a trivial mathematical operation, notice that the head and tail of Kiyota indicate, at least indirectly, the memory section that will not be modified during a current writing operation).
As per claim 19, Neugebauer, Porterfield, Lee, Segal and Kiyota et al. teach the data processing method of claim 15, further comprising: converting the address to binary number (Porterfield, column 7, line 64 – column 8, line 14, “the virtual page number field 204 comprises the upper 20 bits and the offset field 206 comprises the lower 12 bits of a 32 bit virtual address 200. Thus, each page includes 2.sup.12 =4096 (4K) addresses and the lower 12 bits of the offset field 206 locate the desired information within a page referenced by the upper 20 bits of the virtual page number field 204”).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE R SOTO LOPEZ whose telephone number is (571)270-5689. The examiner can normally be reached Monday-Friday, from 8 am - 5 pm.
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/JOSE R SOTO LOPEZ/Primary Examiner, Art Unit 2622