DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Claims 1-4, 6-12, 14-17, 19 and 20 are pending.
3. This office action is in response to the Applicant’s communication filed 09/18/2025 in response to PTO Office Action mailed 06/18/2025. The Applicant’s remarks and amendments to the claims and/or the specification were considered with the results that follow.
Information Disclosure Statement
4. The information disclosure statement (IDS) submitted on 08/04/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the Examiner.
Response to Arguments
5. Applicant’s arguments with respect to the amended independent claims have been considered but are moot in view of the new ground(s) of rejection in which the Examiner has cited previously presented prior art, Odom (US Pub. No. 2006/0184335 A1 hereinafter “Odom”), as necessitated by the amended independent claims.
Claim Rejections - 35 USC § 102
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
7. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
8. Claims 1-4, 6 and 14-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Odom (US Pub. No. 2006/0184335 A1 hereinafter “Odom”).
Referring to claim 1, Odom discloses an apparatus (Odom – Fig. 33F discloses a measurement module 108.) comprising:
a serial peripheral interface (SPI) enabling the apparatus to communicate with an external component over an SPI bus (Odom – Fig. 33F & par. [0362] disclose SPI signal lines (SPI bus) enabling the measurement module 108 to communicate with a SPI communication logic 3384 within a RIO FPGA 308.);
an analog to digital (A/D) converter connected to the SPI and communicates with the external component over the SPI bus (Odom – Fig. 33F & par. [0362] disclose SPI signal lines (SPI bus) enabling the measurement module 108 to communicate with a SPI communication logic 3384 within a RIO FPGA 308. The measurement module 108 may receive analog signals through any of 4 analog inputs 3335 which may be converted to digital signals via ADC 304 and transmitted to the RIO FPGA.); and
a memory connected to the SPI (Odom – Fig. 33A discloses an EEPROM 3308 connected to SPI signal lines (SPI bus).), the memory having a predetermined storage area for initialization and configuration data enabling operation of the A/D converter with the external component over the SPI bus, wherein the initialization and configuration data enabling operation is uniquely associated with the A/D converter (Odom – Fig. 33F & par. [0116] disclose the programmable hardware element of the measurement module 108, e.g., the FPGA 308, may retrieve the interface protocol information from memory, as represented by the DAQ-EDS 307, and communicate the interface protocol information to the carrier 110. In one embodiment, the memory storing the DAQ-EDS 307 may also store configuration information, e.g., a hardware description, for the FPGA 308. The configuration information may be usable to configure or program the FPGA 308 to implement the measurement module side of the interface and/or to manage operations of the measurement module 108B. Par. [0440] discloses a set of factory default power-up settings may be stored in the identification EEPROM of each measurement module. These settings may include the static default values (0 or 1) of a DIO mode digital module or the configuration register settings, default output data values, and/or an initialization method for an SPI mode module.).
Referring to claim 2, Odom discloses the apparatus of Claim 1, wherein the memory comprises an electrically erasable programmable read only memory (EEPROM) (Odom – Fig. 33A discloses an EEPROM 3308 connected to SPI signal lines (SPI bus).).
Referring to claim 3, Odom discloses the apparatus of Claim 1, wherein the external component comprises a field programmable gate array (Odom – Fig. 33F discloses a RIO FPGA 308.).
Referring to claim 4, Odom discloses the apparatus of Claim 1, wherein the external component comprises software (Odom – Par. [0230] discloses the netlist may be compiled into an FPGA program file, also referred to as a software bit stream or hardware configuration program, which can be readily downloaded to program the FPGA. After the netlist has been compiled into an FPGA program file the FPGA program file may be transferred to the FPGA, thereby producing a programmed hardware equivalent to the program.).
Referring to claim 6, Odom discloses the apparatus of Claim 1, wherein responsive to initialization of the external component with the apparatus the initialization and configuration data enabling operation is transmitted from the memory to the external component and further wherein the A/D converter receives the initialization and configuration data enabling operation from the external component prior to enable operation of the A/D converter with respect to the external component (Odom – Fig. 33F & par. [0116] disclose the programmable hardware element of the measurement module 108, e.g., the FPGA 308, may retrieve the interface protocol information from memory, as represented by the DAQ-EDS 307, and communicate the interface protocol information to the carrier 110. In one embodiment, the memory storing the DAQ-EDS 307 may also store configuration information, e.g., a hardware description, for the FPGA 308. The configuration information may be usable to configure or program the FPGA 308 to implement the measurement module side of the interface and/or to manage operations of the measurement module 108B. Par. [0440] discloses a set of factory default power-up settings may be stored in the identification EEPROM of each measurement module. These settings may include the static default values (0 or 1) of a DIO mode digital module or the configuration register settings, default output data values, and/or an initialization method for an SPI mode module.).
Referring to claim 14, note the rejection of claims 1 and 6 above. The Instant Claim recites substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
Referring to claims 15, note the rejection of claim 2 above. The Instant Claim recites substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
Referring to claims 16, note the rejection of claim 3 above. The Instant Claim recites substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
Referring to claim 17, note the rejection of claim 4 above. The Instant Claim recites substantially same limitations as the above-rejected and is therefore rejected under same prior-art teachings.
Allowable Subject Matter
9. Claims 7-12 are allowed.
The examiner finds that the prior art of record taken alone or in combination fails to teach and/or fairly suggest “wherein the data enabling operation from the memory is transmitted from the memory and stored in the buffer and transmitted from the buffer to the A/D converter responsive to initialization of the external component with the electronic device.”, in combination with other recited limitations in independent claim 7.
Claims 8-12 would be allowable based on its dependency of claim 7.
10. Claims 19 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The examiner finds that the prior art of record taken alone or in combination fails to teach and/or fairly suggest “storing the transmitted initialization and configuration data enabling operation from the memory location in a buffer associated with the external component; and transmitting the initialization and configuration data enabling operation from the buffer to the A/D converter.”, in combination with other recited limitations in dependent claim 19.
Claim 20 would be allowable based on its dependency of claim 19.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAYTON LEWIS-TAYLOR whose telephone number is (571)270-7754. The examiner can normally be reached on Monday through Thursday, 8AM TO 4PM, EASTERN TIME.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye, can be reached on 571-270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DAYTON LEWIS-TAYLOR/
Examiner, Art Unit 2181
/Farley Abad/Primary Examiner, Art Unit 2181