NON-FINAL OFFICE ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/25/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to the claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 6-8, 10, 13-15, 17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Pub. No. 2020/0327024 to Alkalay et al. (hereinafter Alkalay) in view of U.S. Patent Pub. No. 2018/0018231 to Okada et al. (hereinafter Okada).
Alkalay discloses:
1. An article of manufacture comprising:
a non-transitory memory including machine-readable instructions that, when executed by a processor, cause the processor to:
send a first command to a first storage device and a second storage device to trigger the first and second storage devices to write strip data to a memory in an accelerator engine (paras. [0030], [0034], [0118]-[0121] – data pages and parity written to memory 316 of processing device 312);
the accelerator engine to perform an operation on the written strip data, the operation to reconstruct data stored on a third failed storage device, wherein the first, second, and third storage devices are part of a RAID volume (paras. [0122] – processing device 112 rebuilds stripe); and
receive an output of the operation from the accelerator engine (paras. [0123]-[0124] – rebuilt stripe obtained and stored).
Alkalay does not disclose expressly in response to a message from at least one of the first storage device or the second storage device, sending a second command to the accelerator engine.
Okada teaches a storage device that, in response to a message from at least one of the first storage device or the second storage device, sends a second command to a storage device processor (paras. [0095]-[0099] and Fig. 13, steps 1304, 1305, 1306).
Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art to modify Alkalay by sending a second command to the accelerator engine in response to a message from a storage device, as taught by Okada. A person of ordinary skill in the art would have been motivated to do so in order to reduce the number of data transfers that are necessary, as discussed by Okada, therefore reducing load and improving performance (para. [0009]).
Modified Alkalay discloses:
2. The article of manufacture of Claim 1, wherein the processor is to send the first command, send the second command, and receive the output using a Peripheral Component Interconnect Express (PCIe) bus including a PCIe root complex (Alkalay - para. [0022]).
3. The article of manufacture of Claim 1, wherein the operation is an XOR operation on the written strip data (Alkalay -para. [0110]).
6. The article of manufacture of Claim 1, wherein the processor is to receive a message from the first and second storage devices indicating that the first and second storage devices have finished writing strip data to the memory in the accelerator engine (Alkalay -para. [0119]); and
wherein the message triggers the processor to send the second command (Alkalay -para. [0123]).
Claims 7, 8, 10, and 13 are a method comprising steps identical to the steps performed by the article of manufacture of claims 1, 2, 3, and 6, and are rejected under the same rationale.
Claims 14, 15, 17, and 20 are a system for performing steps identical to the steps performed by the article of manufacture of claims 1, 2, 3, and 6, and are rejected under the same rationale.
Claims 4, 5, 11, 12, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Alkalay in view of Okada and further in view of U.S. Patent Pub. No. 2021/0271547 to Bates et al. (hereinafter Bates).
Alkalay does not disclose expressly:
4. The article of manufacture of Claim 1, wherein the first and second storage devices and the accelerator engine communicate using peer-to-peer direct memory access.
Bates teaches wherein the first and second storage devices and the accelerator engine communicate using peer-to-peer direct memory access (para. [0011]).
Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art to modify Alkalay by using peer-to-peer direct memory access, as taught by Bates. A person of ordinary skill in the art would have been motivated to do so in order to directly transfer data and bypass a central processing unit of the storage node, as discussed by Bates (para. [0011]).
Modified Alkalay discloses:
5. The article of manufacture of Claim 4, wherein the accelerator engine and the first and second storage devices are PCIe end points (Alkalay – para. [0022] and Bates – paras. [0017], [0028]).
Claims 11 and 12 are a method comprising steps identical to the steps performed by the article of manufacture of claims 4 and 5, and are rejected under the same rationale.
Claims 18 and 19 are a system for performing steps identical to the steps performed by the article of manufacture of claims 4 and 5, and are rejected under the same rationale.
Claims 9 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Alkalay in view of Okada and further in view of U.S. Patent Pub. No. 2020/0104252 to Subbarao.
Alkalay does not disclose expressly:
9. The method of Claim 8, wherein the PCIe root complex is to route communications from the first and second storage devices and the memory in the accelerator engine based on a based address register (BAR) of the memory in the accelerator engine.
Subbarao teaches wherein the PCIe root complex is to route communications from the first and second storage devices and the memory in the accelerator engine based on a based address register (BAR) of the memory in the accelerator engine (paras. [0047], [0049]).
Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art to modify Alkalay by routing communications as taught by Subbarao. A person of ordinary skill in the art would have been motivated to do so in order to allow for local access of remote DSDs, making a system significantly more cost effective, as discussed by Subbarao (para. [0047]).
Claim 16 is a system for performing steps identical to the steps performed by the method of claim 9, and is rejected under the same rationale.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Philip Guyton whose telephone number is (571)272-3807. The examiner can normally be reached M-F 8:00-4:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bryce Bonzo can be reached at (571)272-3655. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PHILIP GUYTON/ Primary Examiner, Art Unit 2113
Prosecution Insights