DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
Applicant’s amendments filed on 5/10/2024 have been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 4, and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi et al’117 (TW 515117) in view of Yamamoto et al (US 2021/0132575).
Regarding Claim 1, Kobayashi et al discloses a method of manufacturing a semiconductor wafer including a step of performing an RTA treatment (a method for manufacturing a semiconductor wafer 18 [page 3, lines 1-44] using a RT device 10 [page 3, lines 1-44] to perform a heat treatment process on a semiconductor wafer [page 1, lines 9-24] Fig 2).
Kobayashi et al’117 does not disclose
a step of performing a first correction using a first offset which is a temperature correction value for eliminating temperature variations over the entire wafer surface throughout the entire processes from heating to cooling in the RTA treatment; and
a step of further performing a second correction using a second offset in the cooling process, which is a temperature correction value being set so that the temperature correction value for a wafer outer circumference,
which is the outer circumferential region including the wafer periphery, is set to be relatively +0.1°C or more and +5.0°C or less, compared to the temperature correction values for the wafer regions other than the wafer outer circumference.
Yamamoto et al, in the related art of semiconductor devices that include temperature control methods, discloses
a step of performing a first correction (correction table, center region 2040 [0084] Fig 6/center region corresponds to division region 60a [0065] Fig 5) using a first offset which is a temperature correction value (Δ degree C/sec, center region, shown in Fig 9/60a Fig 5) for eliminating temperature variations [0007] over the entire wafer (semiconductor wafer W [0049] Fig 2) surface throughout the entire processes from heating [0007] to cooling [0076] in the treatment process; and
a step of further performing a second correction (correction table, edge region, 2040 [0084] Fig 6/edge region corresponds to division region 60b [0065] Fig 3) using a second offset in the cooling process [0076], which is a temperature correction value (claim 8 and Δ degree C/sec, edge region, shown in Fig 9/60b Fig 3) being set so that the temperature correction value (claim 8 and Δ degree C/sec, edge region, shown in Fig 9/60b Fig 3) for a wafer (W Fig 2) outer circumference (edge region shown in Fig 9/60b Fig 3),
which is the outer circumferential region (edge region Fig 6 and Fig 9/60b Fig 3) including the wafer (W Fig 2) periphery, is set to be relatively +0.1°C or more and +5.0°C or less (0.21 -0.43 Fig 6 and Fig 9), compared to the temperature correction values (correction table, center region, 2040 [0084] Fig 6/60a Fig 3) for the wafer regions other than the wafer outer circumference (edge region shown in Fig 9/60b Fig 3).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Kobayashi et al’117 to include a step of performing a first correction using a first offset which is a temperature correction value for eliminating temperature variations over the entire wafer surface throughout the entire processes from heating to cooling in the RTA treatment; and a step of further performing a second correction using a second offset in the cooling process, which is a temperature correction value being set so that the temperature correction value for a wafer outer circumference, which is the outer circumferential region including the wafer periphery, is set to be relatively +0.1°C or more and +5.0°C or less, compared to the temperature correction values for the wafer regions other than the wafer outer circumference as taught by Yamamoto et al in order to have the temperature feedback-controlled in order to affect characteristics of the semiconductor device [0003]. Further, a person of ordinary skill in the art would have recognized that having more control over the temperature of the device would be advantageous in suppressing the slip indexing occurrence as indicated by Kobayashi et al [page 1, lines 9-24] (see MPEP 2143.I(D)).
Regarding Claim 2, the combination of Kobayashi et al’117 and Yamamoto et al discloses the limitations of claim 1 as explained above. The combination of Kobayashi et al’117 and Yamamoto further discloses
wherein the second correction of +0.1˚C or more and +5.0˚C or less (correction table, edge region, 2040 [0084] Fig 6/edge region corresponds to division region 60b [0065] Fig 3 Kobayashi et al’117) is performed to part or the entire wafer outer circumference (circumference of 60b is shown in Fig 3 Kobayashi et al’117).
Regarding Claim 4, the combination of Kobayashi et al’117 and Yamamoto et al discloses the limitations of claim 1 as explained above. The combination of Kobayashi et al’117 and Yamamoto further discloses
wherein the second correction (correction table, edge region, 2040 [0084] Fig 6/edge region corresponds to division region 60b [0065] Fig 3 Kobayashi et al’117) is performed within a period of at least 5 s of the elapsed time from the time of the start of cooling in the cooling process (wherein Δt may be 5 seconds [0094]/cooling process is illustrated in Fig 8A-C Kobayashi et al’117).
Regarding Claim 8, Kobayashi et al’117 discloses a method of manufacturing a semiconductor device, comprising: a step of an RTA treatment comprising a heating process and a cooling process on a semiconductor wafer (a method for manufacturing a semiconductor wafer 18 [page 3, lines 1-44] using a RT device 10 [page 3, lines 1-44] to perform a heat treatment process on a semiconductor wafer [page 1, lines 9-24] Fig 2);
Kobayashi et al’117 does not disclose
a step of performing a first correction using a first offset which is a temperature correction value for eliminating temperature variations over the entire wafer surface throughout the entire processes from heating to cooling in the RTA treatment; and
a step of further performing a second correction using a second offset in the cooling process, which is a temperature correction value being set so that the temperature correction value for a wafer outer circumference,
which is the outer circumferential region including the wafer periphery, is set to be relatively +0.1°C or more and +5.0°C or less, compared to the temperature correction values for the wafer regions other than the wafer outer circumference.
Yamamoto et al, in the related art of semiconductor devices that include temperature control methods, discloses
a step of performing a first correction (correction table, center region 2040 [0084] Fig 6/center region corresponds to division region 60a [0065] Fig 5) using a first offset which is a temperature correction value (Δ degree C/sec, center region, shown in Fig 9/60a Fig 5) for eliminating temperature variations [0007] over the entire wafer (semiconductor wafer W [0049] Fig 2) surface throughout the entire processes from heating [0007] to cooling [0076] in the treatment process; and
a step of further performing a second correction (correction table, edge region, 2040 [0084] Fig 6/edge region corresponds to division region 60b [0065] Fig 3) using a second offset in the cooling process [0076], which is a temperature correction value (claim 8 and Δ degree C/sec, edge region, shown in Fig 9/60b Fig 3) being set so that the temperature correction value (claim 8 and Δ degree C/sec, edge region, shown in Fig 9/60b Fig 3) for a wafer (W Fig 2) outer circumference (edge region shown in Fig 9/60b Fig 3),
which is the outer circumferential region (edge region Fig 6 and Fig 9/60b Fig 3) including the wafer (W Fig 2) periphery, is set to be relatively +0.1°C or more and +5.0°C or less (0.21 -0.43 Fig 6 and Fig 9), compared to the temperature correction values (correction table, center region, 2040 [0084] Fig 6/60a Fig 3) for the wafer regions other than the wafer outer circumference (edge region shown in Fig 9/60b Fig 3).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Kobayashi et al’117 to include a step of performing a first correction using a first offset which is a temperature correction value for eliminating temperature variations over the entire wafer surface throughout the entire processes from heating to cooling in the RTA treatment; and a step of further performing a second correction using a second offset in the cooling process, which is a temperature correction value being set so that the temperature correction value for a wafer outer circumference, which is the outer circumferential region including the wafer periphery, is set to be relatively +0.1°C or more and +5.0°C or less, compared to the temperature correction values for the wafer regions other than the wafer outer circumference as taught by Yamamoto et al in order to have the temperature feedback-controlled in order to affect characteristics of the semiconductor device [0003]. Further, a person of ordinary skill in the art would have recognized that having more control over the temperature of the device would be advantageous in suppressing the slip indexing occurrence as indicated by Kobayashi et al [page 1, lines 9-24] (see MPEP 2143.I(D)).
Regarding Claim 9, the combination of Kobayashi et al’117 and Yamamoto et al discloses the limitations of claim 8 as explained above. The combination of Kobayashi et al’117 and Yamamoto further discloses
wherein the second correction of +0.1˚C or more and +5.0˚C or less is performed to part or the entire wafer outer circumference (circumference of 60b is shown in Fig 3 Kobayashi et al’117).
Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi et al’117 (TW 515117) in view of Yamamoto et al (US 2021/0132575), and in further view of Kobayashi et al’895 (US 2014/0322895).
Regarding Claim 5, the combination of Kobayashi et al’117 and Yamamoto et al discloses the limitations of claim 1 as explained above. The combination of Kobayashi et al’117 and Yamamoto et al further discloses
wherein the RTA treatment (a method for manufacturing a semiconductor wafer 18 [page 3, lines 1-44] using a RT device 10 [page 3, lines 1-44] to perform a heat treatment process on a semiconductor wafer [page 1, lines 9-24] Fig 2 Kobayashi et al’117) is performed while the semiconductor wafer (semiconductor wafer 18 Fig 2 Kobayashi et al’117) is placed on a wafer support member having a support surface inclined downwardly toward the inside.
The combination of Kobayashi et al’117 and Yamamoto et al does not directly disclose
the surface roughness of the semiconductor wafer in the vicinity of the contact position of the semiconductor wafer with the wafer support member is 5.0 nm ≤ Ra ≤ 30.0 nm.
Kobayashi et al’895, in the related art of semiconductor devices that includes semiconductor manufacturing of semiconductor wafers, discloses
wherein the surface roughness of the semiconductor wafer (SOI wafer [0012]) in the vicinity of the contact position of the semiconductor wafer (SOI wafer) with the wafer support member is 5.0 nm ≤ Ra ≤ 30.0 nm (surface roughness has come within 3 nm being obtained by the ion implantation delamination method in mass production level [0012]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Kobayashi et al’117 and Yamamoto et al to include the surface roughness of the semiconductor wafer in the vicinity of the contact position of the semiconductor wafer with the wafer support member is 5.0 nm ≤ Ra ≤ 30.0 nm as taught by Kobayashi et al’895 since the surface roughness of SOI wafers can be within 3nm by ion implantation delamination method in mass production level [0012] and because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05).
Regarding Claim 6, the combination of Kobayashi et al’117 and Yamamoto et al discloses the limitations of claim 1 as explained above. The combination of Kobayashi et al’117 and Yamamoto et al does not directly disclose
wherein the diameter of the semiconductor wafer subjected to the RTA treatment is 300 mm or more.
Kobayashi et al’895, in the related art of semiconductor devices that includes semiconductor manufacturing of semiconductor wafers, discloses
wherein the diameter of the semiconductor wafer (SOI wafer [0012]) subjected to the RTA treatment is 300 mm or more (diameter is 300 mm [0012]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Kobayashi et al’117 and Yamamoto et al to include wherein the diameter of the semiconductor wafer subjected to the RTA treatment is 300 mm or more as taught by Kobayashi et al’895 in order to meet small size parameters of semiconductor devices that utilize SOI wafers and because it would have been an obvious matter of design choice to optimize the diameter of the semiconductor wafer such a modification would have involved a mere change in size of the component. A change in size is generally recognized as being within the level of ordinary skill in the art In Re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) MPEP 2144.04.IV(A). Further, a person of ordinary skill in the art would have recognized that meeting smaller size parameters would be advantageous in optimizing the efficiency of device function as well as improving integration density (see MPEP 2143.I(D)).
Regarding Claim 7, the combination of Kobayashi et al’117 and Yamamoto et al discloses the limitations of claim 1 as explained above. The combination of Kobayashi et al’117 and Yamamoto et al does not directly disclose
wherein the wafer outer circumference is defined as an area of 10 mm or less to the center from the periphery of the semiconductor wafer.
Kobayashi et al’895, in the related art of semiconductor devices that includes semiconductor manufacturing of semiconductor wafers, discloses
wherein the diameter of the semiconductor wafer (SOI wafer [0012]) subjected to the RTA treatment is 300 mm or more (diameter is 300 mm [0012]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Kobayashi et al’117 and Yamamoto et al to include wherein the diameter of the semiconductor wafer subjected to the RTA treatment is 300 mm or more as taught by Kobayashi et al’895 in order to meet small size parameters of semiconductor devices that utilize SOI wafers and because it would have been an obvious matter of design choice to optimize the diameter of the semiconductor wafer such a modification would have involved a mere change in size of the component. A change in size is generally recognized as being within the level of ordinary skill in the art In Re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955) MPEP 2144.04.IV(A). Further, a person of ordinary skill in the art would have recognized that meeting smaller size parameters would be advantageous in optimizing the efficiency of device function as well as improving integration density (see MPEP 2143.I(D)).
The combination of Kobayashi et al’117, Yamamoto et al, and Kobayashi et al’895 now discloses
wherein the outer circumference of the wafer would be a small portion of its diameter (which although not drawn to scale, appears to be 1/13 of the diameter shown in Fig 1b-d Kobayashi et al’895 which would be approximately 1/13 x 300 mm = 23.07 mm).
The combination of Kobayashi et al’117, Yamamoto et al, and Kobayashi et al’895 does not directly disclose
wherein the wafer outer circumference is defined as an area of 10 mm or less to the center from the periphery of the semiconductor wafer.
However, a person of ordinary skill in the art would know that the size of the outer circumference of the wafer would be a result effective variable in that the outer edge would protect elements in the center of the wafer during the manufacturing process.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Kobayashi et al’117, Yamamoto et al, and Kobayashi et al’895 to include wherein the wafer outer circumference is defined as an area of 10 mm or less to the center from the periphery of the semiconductor wafer in order to protect elements in the center of the wafer during the manufacturing process, and to help suppress the non-uniformity in temperatures of the semiconductor wafer [0022] as referred to by Yamamoto et al. Further, a person of ordinary skill in the art would have recognized that defining the outer circumference as a small area would be advantageous in the prevention of damage which would increase the reliability and durability of the resulting device (see MPEP 2143.I(D)).
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 3:
Regarding Claim 3, the combination of Kobayashi et al’117 and Yamamoto et al discloses the limitations of claim 1 as explained above.
Aoki et al (JP 2010027959 A) discloses
wherein the RTA treatment is carried out in an oxidizing atmosphere under conditions of holding at a maximum temperature reached of 1250˚C or higher (the heat treatment is between 1100 degrees Celsius and 1350 degrees Celsius [page 4, lines 20-41]) and of at a cooling rate of 33˚C/s or more.
Kobayashi et al’121 (WO-2015141121-A1) discloses
wherein the maximum temperature of the RTA treatment is preferably 1100 degrees C or more and the treatment time is about 1 to 30 seconds [page 5, lines 20-30].
The reason for the indication of allowability of Claim 3 is the inclusion of
cooling down to 1000˚C or less.
Specifically, the prior art reference Aoki et al discloses in [page 4, lines 20-41] that if the heat treatment is above 1350 degrees Celsius, the occurrence of slip dislocation is a concern, and if the temperature is lower than 1100 degrees Celsius, sufficient hole injection cannot be obtained. Therefore, if another reference were found that disclosed a cooling down process to 1000 degrees Celsius, it would not be obvious to a person of ordinary skill in the art to combine the references and alter Aoki et al in this manner since it would teach away from the disclosure of Aoki et al.
It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Aga et al (US 2004/0063298) which discloses an RTA process of a wafer [0010], and Ishizuka et al (US 2017/0345663) which discloses a silicon wafer with a diameter of 300 mm [0009].
Conclusion
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/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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