DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
CLAIM INTERPRETATION
Claims in this application are not interpreted under 35 U.S.C. §112(f).
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-7, 13-14 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claims 6, 13 and 20:
The term “normal” recited in these claims is a relative term which renders the claim indefinite. The term “normal” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Furthermore, Applicant’s arguments in the Remarks dated 05 January 2025 (Rem) assert that “normal order programming” has a special meaning that is common in the art, which is “programming from the drain side of a memory block to the source side”. However, the specification at [0210] asserts that in normal order programming, programming “begins on the source side of the sub-block and proceeds in a direction towards the drain side of the sub block”, which is exactly the opposite of the order asserted by Applicant as being “common in the art”. As the two asserted meanings are contradictory, the scope of the claim cannot be determined and the claim is indefinite.
Regarding claims 7 and 14:
Claims 7 and 14 are rejected for failing to cure the deficiencies of a rejected base claim from which they depend.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-9 and 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication No. US 2025/0028453 A1 (Zhang) in view of US Patent Application Publication No. US 2011/0199825 A1 (Han) in further view of US Patent Application Publication No. US 2023/0343395 A1 (Zhang_2).
Regarding claim 1 and analogous claim 8:
Zhang_1 teaches, a method of operating a memory device, comprising steps of: preparing a memory device that includes a memory block with an array of memory cells that are arranged in a plurality of word lines, wherein the plurality of word lines are divided into a first sub-block and a second sub-block (by teaching that the pages of a memory block (defined by wordlines) can be divided into sub-blocks (such as an upper half and lower half of the block as the sub-blocks (a first sub-block and a second sub-block). The upper and lower halves can be called decks or half-blocks, and are part of the stack [Fig. 2] [Fig. 8] [0054]. The sub-block/half-block architecture allows each to be separately erased [Fig. 8] [0081]. Furthermore, the memory may include multiple devices (2000) connected to a host (4000) CPU through a memory controller (2500) (i.e., packages in communication with a processor) [Fig. 25] [0132-0136]), the memory cells of the first sub-block contain data, the memory block has a source side and a drain side, (by disclosing that each memory block has a source select gate (SSG) at its source end and a drain select gate (DSG) at its drain end [0051] [0056-0057] [Fig. 2]) and the memory cells of the second sub-block are erased (see [Fig. 8], because of the nature of NAND cells, data in NAND flash cells cannot be overwritten. Therefore, data can only be programmed into an erased block [0044]); programming the data into the memory cells of the second sub-block (by teaching that data can only be programmed into an erased half-block, and cannot be programmed into a half block that is not erased because NAND flash cells cannot be overwritten [0044]).
Zhang_1 does not explicitly disclose, but Han teaches, determining that the memory cells of the first sub-block have experienced read disturb; and programming the data in the memory cells of the first sub-block into the memory cells of the second sub-block (by teaching that when data of a sub-block reaches a reference value for read disturb, the sub-block may be refreshed. In that case, the sub-block refresh operation includes backing up data stored in the sub-block and writing it to the other sub-block of the same physical memory block (i.e., from the upper to lower halves) in a copyback operation [0266-0267] [Fig. 18] [0281]. Han teaches that this is performed by a refresh unit (630), driven in the flash translation layer in the controller as part of a processor (520) of the controller (circuitry) [0268-0273)).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the operation of the memory with sub-blocks as taught by Zhang_1 to include checking the sub-blocks for read disturb based on a read count by comparison to a threshold and writing the data from the disturbed sub-block to the other sub-block of the same physical block as taught by Han.
One of ordinary skill in the art would have been motivated to make this modification because selective refresh can restore the reliability of the memory system as taught by Han in [0289].
Zhang_1 does not explicitly disclose, but Zhang_2 teaches, wherein prior to the step of programming the data in the memory cells of the first sub-block to the memory cells of the second sub-block (i.e., as previously taught by Han), the data has a first order within the first sub-block; and after step of programming the data in the memory cells of the first sub-block to the memory cells of the second sub-block (i.e., as previously taught by Han), the data has a second order within the second sub-block, the second order being opposite of the first order (by teaching that the programming order of the wordlines in each sub-block is from the middle outward. Accordingly, the programming order of the data stored (the data to be refreshed as taught by Han) in the first sub-block (i.e., top/bottom) is the opposite (i.e., middle-up or middle-down) from the programming order of the second sub-block (i.e., the opposite of top/bottom and the opposite programming order of middle-up/middle-down) (where the refreshed data is stored as taught by Han) [see Fig. 8] [0136]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the programming of the data for refresh in the copyback operation from one half-block to another half-block in the same physical block as taught by Han to include reversing the programming order from the other sub-block such that the half-blocks are programmed from the middle-out as taught by Zhang_2.
One of ordinary skill in the art would have been motivated to make this modification because it achieves better reliability in the programming of the sub-blocks as taught by Zhang_2 in [0136].
Regarding claim 2 and analogous claim 9:
The method as set forth in claim 1 is made obvious by Zhang_1 in view of Han in further view of Zhang_2 (Zhang_1-Han-Zhang2).
Zhang_1 does not explicitly disclose, but Han teaches, further including steps of counting a number of read cycles to establish a read cycle count; and comparing the read count cycle to a predetermined threshold; and wherein the step of determining that the memory cells of the first sub-block have experienced significant read disturb occurs in response to the read cycle count exceeding the predetermined threshold (by teaching the read cycle table that is used to count a number of read cycles, such that the sub-block can be selectively refreshed when it hits a threshold [0047] [0062] [0266].
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the operation of the memory with sub-blocks as taught by Zhang_1 to include checking the sub-blocks for read disturb based on a read count by comparison to a threshold and writing the data from the disturbed sub-block to the other sub-block of the same physical block as taught by Han.
One of ordinary skill in the art would have been motivated to make this modification because selective refresh can restore the reliability of the memory system as taught by Han in [0289].
Regarding claim 4 and analogous claim 11:
The method as set forth in claim 1 is made obvious by Zhang_1-Han-Zhang_2.
Zhang_1 does not explicitly disclose, but Han teaches further including the steps of: erasing the memory cells of the first sub-block; determining that the memory cells of the second sub-block have experienced significant read disturb; and programming the data in the memory cells of the second sub-block into the memory cells of the first sub-block (by teaching that after a sub-block is refreshed and the data from the sub-block being refreshed is programmed into the other sub-block of the same physical block of which the sub-block is being refreshed, the refreshed sub-block may be erased and the read count of the sub-block may be reset [0285-0289]. Accordingly, when the read count of the sub-block to which the data was transferred reaches the threshold, the data in the sub-block to which the data was transferred may be refreshed and the data being refreshed may be transferred back to the original sub-block of the same physical block [0266-0289]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the operation of the memory system as taught by Zhang_1 to include erasing a sub-block after its data has been refreshed, such that the data of the other sub-block may subsequently be refreshed if it hits the read count threshold by refreshing the data to the original sub-block as taught by Han.
One of ordinary skill in the art would have been motivated to make this modification because the reliability of the memory system may be improved as taught by Han in [0289].
Regarding claim 5 and analogous claim 12:
The method as set forth in claim 4 is made obvious by Zhang_1-Han-Zhang_2.
Zhang_1 does not explicitly disclose, but Zhang_2 teaches, wherein after the step of programming the data in the memory cells of the second sub-block into the memory cells of the first sub-block, the data has the first order (by teaching that the programming order of the wordlines in each sub-block is from the middle outward. Accordingly, the programming order of the data stored (the data to be refreshed as taught by Han) in the first sub-block (i.e., top/bottom) is the opposite (i.e., middle-up or middle-down) from the programming order of the second sub-block (i.e., the opposite of top/bottom and the opposite programming order of middle-up/middle-down) (where the refreshed data is stored as taught by Han) [see Fig. 8] [0136]. Therefore, if the second sub-block is subsequently refreshed and stored again in the other sub-block of the same block (as taught by Han), its order would be restored to the original programming order of the first-sub block (i.e., back to the original programming order of the top/bottom sub-block which would be middle-up/middle-down) [see Fig. 8] [0136]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the programming of the data for refresh in the copyback operation from one half-block to another half-block in the same physical block as taught by Han to include reversing the programming order from the other sub-block such that the half-blocks are programmed from the middle-out as taught by Zhang_2.
One of ordinary skill in the art would have been motivated to make this modification because it achieves better reliability in the programming of the sub-blocks as taught by Zhang_2 in [0136].
Regarding claim 6 and analogous claim 13:
The method as set forth in claim 5 is made obvious by Zhang_1-Han-Zhang_2.
Zhang_1 teaches, wherein the first sub-block is a lower sub-block and wherein the second sub-block is an upper sub-block (by teaching that the sub-blocks may include lower and upper decks or half-blocks [see Figs. 8 & 17]).
Zhang_1 does not explicitly disclose, but Zhang_2 teaches, wherein the step of programming the data in the memory cells of the lower sub-block into the memory cells of the upper sub-block includes programming according to a normal order programming direction (by teaching that the blocks are programmed from the middle-out (normal) [Fig. 8] [-136]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the programming of the data for refresh in the copyback operation from one half-block to another half-block in the same physical block as taught by Han to include reversing the programming order from the other sub-block such that the half-blocks are programmed from the middle-out as taught by Zhang_2.
One of ordinary skill in the art would have been motivated to make this modification because it achieves better reliability in the programming of the sub-blocks as taught by Zhang_2 in [0136].
Regarding claim 7 and analogous claim 14:
The method as set forth in claim 6 is made obvious by Zhang_1-Han-Zhang_2.
Zhang_1 does not explicitly disclose, but Zhang_2 teaches, wherein the step of programming the data in the memory cells of the upper sub-block into the memory cells of the lower sub-block includes programming according to a reverse order programming direction (by teaching that the programming of each half of the sub-blocks is from the middle out, such that one is from the middle up and the other is from the middle-down (opposite) [Fig. 8] [0136]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the programming of the data for refresh in the copyback operation from one half-block to another half-block in the same physical block as taught by Han to include reversing the programming order from the other sub-block such that the half-blocks are programmed from the middle-out as taught by Zhang_2.
One of ordinary skill in the art would have been motivated to make this modification because it achieves better reliability in the programming of the sub-blocks as taught by Zhang_2 in [0136].
Claims 15-16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang_1 in view of Han in further view of Zhang_2 in further view of the paper by Hyun-Jin Kim et. al., titled “1GB/s 2Tb NAND Flash Multi-Chip Package with Frequency-Boosting Interface Chip” (Kim).
Regarding claims 15-16 and 18-20:
Claims 15-16 and 18-20 are rejected according to a similar analysis performed for claims 1-2 and 4-6, respectively, except that Zhang_1 does not explicitly disclose that the plurality of memory devices (2000) are high bandwidth flash (HBF) packages.
However, Kim teaches to use high bandwidth flash (HBF) packages (by teaching flash packages that include an interface chip to allow multiple flash packages to be combined to create greater bandwidth by decreasing capacitance and jitter to allow high capacity and high bandwidth [see Fig. 7.6.1] [§7.6, ¶1-7])
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory devices (2000) making up the SSD as taught by Zhang_1 to include the high bandwidth multichip flash packages taught by Kim.
One of ordinary skill in the art would have been motivated to make this modification because the use of the multi-chip package including the F-chip allows for higher I/O bandwidth, which solves a key bottleneck in SSD technology as taught by Kim in [§7.6, ¶1].
Response to Arguments/Amendments
In response to the amendments to the claims, the claim objections have been withdrawn.
In response to the amendments to the claims, the 35 USC §112(b) rejections for the claims reciting “significant” have been withdrawn.
In response to the arguments against claims 6-7, 13-14 and 20 for reciting “normal”, the Examiner is not persuaded. Applicant’s arguments in the Remarks dated 05 January 2025 (Rem) assert that “normal order programming” has a special meaning that is common in the art, which is “programming from the drain side of a memory block to the source side”. However, the specification at [0210] asserts that in normal order programming, programming “begins on the source side of the sub-block and proceeds in a direction towards the drain side of the sub block”, which is exactly the opposite of the order asserted by Applicant as being “common in the art”. As the two asserted meanings are contradictory, the scope of the claim cannot be determined and the claim is indefinite. The Examiner suggests amending the claims to indicate whether the order is from a drain side to a source side, or from a source side to a drain side, to avoid any ambiguity, rather than trying to rely on contradictory and relative descriptions of “normal”.
Applicant’s arguments have been fully considered, but are not persuasive, because they rely on limitations that are not required by the claims.
As amended, claim 1 requires only that the data have a first order within a first sub-block prior to programming and a second, opposite order within a second sub-block after programming. The claim does not require that the data be copied in a mirrored physical sequence, nor does it require that specific logical word lines in one sub-block map to corresponding logical word lines in the other sub-block in a reversed order as argued by Applicant in [Rem, pg. 10, last ¶ continued onto pg. 11].
Applicant argues that Zhang_2 teaches only a logical word line numbering scheme and does not teach copying data in a particular order [Rem, pg. 10, last ¶ continued onto pg. 11]. However, the claim is not limited to a copying order of data transfer between sub-blocks. Rather, as supported by the specification, the claimed “order” encompasses a programming order, i.e., the direction or temporal sequence in which data is programmed into memory cells. The specification explicitly describes programming order as including opposite directions (e.g., drain to source or source to drain) also referred to as normal and reverse order programming [0210].
Zhang_2 teaches programming word lines from the middle outward in each sub-block [0136] [Fig. 8]. As applied in the rejection, when Zhang_2’s middle out programming scheme is used in the refresh copyback operation taught by Han, the temporal programming order of data in one sub-block is opposite to the temporal programming order of data in the other sub-block. Specifically, one sub-block is programmed middle-down (top-down) while the other is programmed middle-up (bottom-up). This results in opposite data programming orders (which are orders of data within sub-blocks) between the two sub-blocks, as required by the claim.
Applicant’s argument that there is “no reason” for data from a particular logical word line in one sub-block to be written to a specific logical word line in the other sub-block is misplaced. The claim does not require any particular logical word line correspondence or mirrored physical placement of data. It requires only that the order of data within one sub-block be opposite the order of data in the other sub-block, which is satisfied by the reversed temporal programming orders taught by Zhang_2 when applied to Han’s refresh operation.
Accordingly, the rejection does not rely on impermissible hindsight bias or Applicant’s specification, as it relied only on the teachings of Zhang_1, Han, and Zhang_2. The combination of Zhang_1, Han, and Zhang_2 teaches or renders obvious all limitations of the claim, including the requirement that data have opposite orders (i.e., programming orders) in the two sub-blocks following the programming operation. The rejection under 35 USC §103 is therefore updated to reflect the claims as amended.
As Applicant’s arguments applied to the independent claims are not persuasive, the same arguments applied to the dependent claims are similarly not persuasive, and the rejections of the dependent claims have been updated to reflect the claims as amended.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CURTIS JAMES KORTMAN/ Primary Examiner, Art Unit 2139