DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
CLAIM INTERPRETATION
Claims in this application are not interpreted under 35 U.S.C. §112(f).
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-2, 4-9, 11-16 and 18-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 1 and analogous claims 8 and 15:
Claim 1 (and analogous claims 8 and 15) discusses programming data from one part of a block to another part of the same block and then recites that this “avoids the need to manage the relocated data in a logical-to-physical mapping table”. Although paragraph [00208] recites substantially identical language, the Specification does not describe how this result (moving the data while avoiding the need to manage relocated data in a logical-to-physical mapping table) is achieved. The disclosed relocation moves the data from physical pages in a sub-block (for example, SB0) to different physical pages in another sub-block of the same block (for example, SB1) [see Fig. 9B, Fig. 9F] [00208]. Therefore, while the physical block may remain unchanged, the physical page at which the data is stored changes (as evidenced by the different WL numbers of the different sub-blocks of the same physical block shown in [Fig. 4D] and the illustrations in [Fig. 9B and Fig. 9F]). The specification does not identify any address translation, predetermined correspondence, sub-block indicator, or other mechanism by which the controller subsequently locates the relocated data without managing the changed physical location in the logical-to-physical mapping table. For example, [0065] indicates that the storage system is “free to store the data as it wishes among the locations of the one or more memory dies”. Accordingly, absent some other undisclosed mechanism, failing to update or otherwise manage the relocation in the logical-to-physical address mapping table after relocating the data according to the process as disclosed would cause the mapping to identify the former physical location of the data.
MPEP 2163.03(V) explains that:
The written description requirement is not necessarily met when the claim language appears in ipsis verbis in the specification. "Even if a claim is supported by the specification, the language of the specification, to the extent possible, must describe the claimed invention so that one skilled in the art can recognize what is claimed. The appearance of mere indistinct words in a specification or a claim, even an original claim, does not necessarily satisfy that requirement." Enzo Biochem, Inc. v. Gen-Probe, Inc., 323 F.3d 956, 968, 63 USPQ2d 1609, 1616 (Fed. Cir. 2002).
Accordingly, the fact that [00208] provides ipsis verbis support is not a sufficient condition for determining that written description exists within the specification. Furthermore, written description issues arise in this context when “the claim defines the invention in functional language specifying a desired result, but the disclosure fails to sufficiently identify how the function is performed or the result is achieved” [MPEP 2163.03(V)]. As the claim is directed to an intended result without identifying a sufficient mechanism for how this result is achieved, the specification does not demonstrate that Applicant was in possession of the claimed invention for achieving the desired result and the claim lacks written description support.
Regarding claims 2, 4-7, 9, 11-14, 16 and 18-20:
Claims 2, 4-7, 9, 11-14, 16 and 18-20 are rejected for failing to cure the deficiencies of a rejected base claim from which they depend.
Response to Arguments/Amendments
In response to the amendments to the claims, the previous 35 U.S.C. §112(b) rejection to the claims have been withdrawn. However, in response to the amendments to the claims, a new 35 U.S.C. §112(b) rejection to claims have been made as seen in the corresponding rejection section above.
In response to the amendments to the claims, a new 35 USC §112(a) rejection has been made as seen in the corresponding rejection section above.
In response to the amendments to the claims, the 35 USC §103 rejection has been withdrawn.
As claims 1-2, 4-9, 11-16 and 18-20 are rejected under 35 USC §112(a), the claims are not indicated as allowable.
Subject Matter Free From Prior Art
The subject matter of claim 1, particularly, “wherein data are relocated from part of the memory block to another part of the same memory block and avoids the need to manage the relocated data in a logical-to-physical mapping table” was searched for in the prior art, but not found. Accordingly, the claims are not rejected with prior art. However, claims 1-2, 4-9, 11-16 and 17-20 are subject to an outstanding 35 USC §112(a) rejection and accordingly, are not indicate as allowable.
The subject matter of claims 8 and 15 is not rejected with prior art for analogous reasons to those indicated for claim 1.
The subject matter of the dependent claims is not rejected with prior art at least by virtue of their dependence from the independent claims, which were not rejected.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Provided that the claimed subject matter which is lacking an adequate written description is removed, the claims would be rejected according to the following references and according to the following analysis:
US Patent Application Publication No. US 2025/0028453 A1 (Zhang_1)
US Patent Application Publication No. US 2017/0168891 A1 (Park)
US Patent Application Publication No. US 2011/0199825 A1 (Han)
US Patent Application Publication No. US 2023/0343395 A1 (Zhang_2)
US Patent Application Publication No. US 2014/0068365 A1 (Chen).
The paper by Hyun-Jin Kim et. al., titled “1GB/s 2Tb NAND Flash Multi-Chip Package with Frequency-Boosting Interface Chip” (Kim).
Regarding claim 1 and analogous claim 8 (omitting the limitation rejected under 35 USC §112(a) - written description):
Zhang_1 teaches, a method of operating a memory device, comprising steps of: preparing a memory device that includes a memory block with an array of memory cells that are arranged in a plurality of word lines, wherein the plurality of word lines are divided into a first sub-block and a second sub-block (by teaching that the pages of a memory block (defined by wordlines) can be divided into sub-blocks (such as an upper half and lower half of the block as the sub-blocks (a first sub-block and a second sub-block). The upper and lower halves can be called decks or half-blocks, and are part of the stack [Fig. 2] [Fig. 8] [0054]. The sub-block/half-block architecture allows each to be separately erased [Fig. 8] [0081]. Furthermore, the memory may include multiple devices (2000) connected to a host (4000) CPU through a memory controller (2500) (i.e., packages in communication with a processor) [Fig. 25] [0132-0136]), the memory cells of the first sub-block contain data, the memory block has a source side and a drain side, (by disclosing that each memory block has a source select gate (SSG) at its source end and a drain select gate (DSG) at its drain end [0051] [0056-0057] [Fig. 2]) and the memory cells of the second sub-block are erased (see [Fig. 8], because of the nature of NAND cells, data in NAND flash cells cannot be overwritten. Therefore, data can only be programmed into an erased block [0044]); programming the data into the memory cells of the second sub-block (by teaching that data can only be programmed into an erased half-block, and cannot be programmed into a half block that is not erased because NAND flash cells cannot be overwritten [0044]).
Zhang_1 does not explicitly disclose, but Han teaches, determining that the memory cells of the first sub-block have experienced read disturb; and programming the data in the memory cells of the first sub-block into the memory cells of the second sub-block; wherein data are relocated from part of the memory block to another part of the same memory block (by teaching that when data of a sub-block reaches a reference value for read disturb, the sub-block may be refreshed. In that case, the sub-block refresh operation includes backing up data stored in the sub-block and writing it to the other sub-block of the same physical memory block (i.e., from the upper to lower halves or vice versa, from part of the memory block to another part of the same memory block) in a copyback operation [0266-0267] [Fig. 18] [0281]. Han teaches that this is performed by a refresh unit (630), driven in the flash translation layer in the controller as part of a processor (520) of the controller (circuitry) [0268-0273)).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the operation of the memory with sub-blocks as taught by Zhang_1 to include checking the sub-blocks for read disturb based on a read count by comparison to a threshold and writing the data from the disturbed sub-block to the other sub-block of the same physical block as taught by Han.
One of ordinary skill in the art would have been motivated to make this modification because selective refresh can restore the reliability of the memory system as taught by Han in [0289].
Han does not explicitly disclose, but Park teaches that the refresh operation involves reading the data sequentially from the source block and then sequentially programming the data into corresponding pages of the destination block (by teaching that during a reclaim operation, the data is sequentially read from the first memory block being the source memory block, and is then programmed into the destination block in a plurality of sub-operations, including reading the data of one page of the source block, correcting the errors of that page, and then programming that page of error corrected data into a page of the destination block, which together or separately may be considered a sub-operation [0060] [Fig. 5]. In this way, an interval of time between the sub-operations may be adjusted based on a determined error type of the block being reclaimed, and when a longer interval is used, the performance degradation of the reclaim operation on the memory system may be reduced, while still securing the integrity of the data stored in the source block [0039] [0041] [0062-0063] [0075-0076] [0081-083]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the performance of the refresh operation on the sub-blocks moving data from a source sub-block to a destination block of the same physical block as taught by Han to include sequentially reading the data of the source block (sub-block as taught by Han), correcting the errors of the read data, and then programming the error corrected data into the destination block (sub-block as taught by Han) in units of sub-operations, such that the rate of performing the sub-operations may be controlled as taught by Park.
One of ordinary skill in the art would have been motivated to make this modification because controlling the rate of the sub-operations can reduce the performance degradation while still ensuring the integrity of the data in the source block as taught by Park in [0083] [0039].
Zhang_1 does not explicitly disclose, but Zhang_2 teaches, programming data into the first sub-block beginning with an innermost word line of the first sub-block and programming the data into the second sub-block beginning with an innermost word line of the second sub-block, such that the data of the innermost wordline of the first sub-block is programmed first in programming of the first sub-block and the data of the innermost word line of the second sub-block is programmed first in the programming of the second sub-block, and each next word line of the first sub block is programmed sequentially in programming of the first sub-block and each next word line of the second block is programmed sequentially in programming of the second sub-block, wherein prior to the step of programming the data in the memory cells of the first sub-block to the memory cells of the second sub-block (i.e., as previously taught by Han), the data has a first order within the first sub-block that beings on the drain side of the first sub-block and proceeds towards the source side of the first sub-block; and after step of programming the data in the memory cells of the first sub-block to the memory cells of the second sub-block (i.e., as previously taught by Han), the data has a second order within the second sub-block according to a second programming direction that begins on the source side of the second sub-block and proceeds toward the drain side of the second sub-block, wherein the second programming direction is opposite of the first programming direction (by teaching that the programming order of the wordlines in each sub-block is from the middle outward [see Fig. 8]. Accordingly, the programming order of the data stored (the data to be refreshed as taught by Han) in the first sub-block (i.e., for example, SB0 [see Fig. 4C]) is from the drain side of SB0 (i.e., WL119 is closer to the drain side of the block (SGD0-SGD2), “drain side select layers” [0085]) to the select side of SB0 (i.e., WL 0 is closer to the select side of the block (SGS0-SGS2) “source side select layers” [0085]). Furthermore, the programming order of the data to be stored (the data that is refreshed as taught by Han) in the second sub-block (i.e., for example, SB1) [see Fig. 4C] is from the source side of SB1 (WL120) to the drain side of SB1 (WL239). Accordingly, the programming order of SB0 (first sub-block) is opposite the programming order of SB1 (second sub-block) as they are both middle-out, but SB0 is drain to source and SB1 is source to drain [Fig. 4C] [Fig. 8] [0136-0137]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the programming of the data for refresh in the copyback operation, read sequentially from one half-block and then written to the other half-block in the same physical block as taught by Han to include reversing the programming order from the other sub-block (832 vs 830) such that each of the half-blocks are programmed from the middle-out, including from a drain to source for a first sub-block and from a source to a drain for a second sub-block as taught by Zhang_2.
One of ordinary skill in the art would have been motivated to make this modification because it achieves better reliability in the programming of the sub-blocks as taught by Zhang_2 in [0136].
Zhang_1 in view of Park in view of Han in further view of Zhang_2 teaches to program the data into the first/source sub-block sequentially from the innermost wordline to the outermost wordline of the first/source sub-block, and teaches to read the data sequentially from the source/first sub-block in a refresh operation and then program it sequentially in the second/destination sub-block from the from the innermost wordline to the outermost wordline of the second/destination sub-block. However, Zhang_1 in view of Park in view of Han in further view of Zhang_2 do not teach a particular side of or place within the first/source block to start reading data from. However, Chen teaches a particular side of or place within the first/source block to start reading data from as part of the refresh operation, such that programming the data in the memory cells of the first sub-block into the memory cells of the second sub-block would be performed by reading the data sequentially beginning with an innermost data-containing word line of the first sub-block and programming the data into the memory cells of the second sub-block beginning with an innermost word line of the second sub-block such that the data of the innermost data-containing word line of the first sub-block is programmed into the innermost word line of the second sub-block and the data of each next word line of the first sub-block is programmed into a next word line of the second sub-block (by teaching that a read scrub may be performed simply from a first page (page 0) to a last page (page 127) in the block [0058]. The page order of the read operations for the read scrub may be all the pages in the block read sequentially, and “may be the same as the page order used in programming” [0062]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the sequential reading of pages of a sub-block during a refresh operation to then program those pages to the destination sub-block as taught by Zhang_1 in view of Park in view of Han by programming them to the innermost word line of the destination sub-block to a next, next, and next word line toward the outermost word line of the destination sub-block as taught by Zhang_1 in view of Park in view of Han in further view of Zhang_2 to include sequentially reading the pages simply from a first page (LWL0 as taught by Zhang_2) to a last page (LWL119 as taught by Zhang_2) and the same order as the order of programming (LWL0 to LWL119 as taught by Zhang_2) as taught by Chen because it would have only required the combination of known elements according to known methods to yield predictable results. For example, Zhang_2 teaches a first word line (LWL0) and a last word line (LWL119) of a sub-block, and teaches a programming direction of the word lines, from LWL0 to LWL119, which is from an innermost word line to an outermost wordline. Furthermore, Park teaches the refresh operation occurs by reading the pages of the source block sequentially. However, Park does not disclose a particular word line of the source block to begin reading from sequentially during the refresh operation. Accordingly, Chen teaches that the sequential direction may progress simply from a first word line (0) to a last word line (127), and may progress in the same order as the page order used during programming. Therefore, one of ordinary skill in he art could have combined the order taught by Chen for reading the pages (from the lowest word line to the highest word line, or the programming order of the word lines as taught by Chen) with the sequential reading of pages as taught by Park according to the lowest to the highest wordline as taught by Chen of the sub-block (LWL0 -> LWL119) as taught by Zhang_2, and according to the programming order as taught by Chen of the sub-block (LWL0 -> LWL119) as taught by Zhang_2 according to known methods and the results would have been predictable. Therefore, the combination would have been obvious to one of ordinary skill in the art.
Regarding claim 2 and analogous claim 9 (omitting the limitation rejected under 35 USC §112(a) - written description):
The method as set forth in claim 1 (omitting the limitation rejected under 35 USC §112(a) - written description) is made obvious by Zhang_1 in view of Park in view of Han in further view of Zhang_2 in further view of Chen (Zhang_1-Park-Han-Zhang_2-Chen).
Zhang_1 does not explicitly disclose, but Han teaches, further including steps of counting a number of read cycles to establish a read cycle count; and comparing the read count cycle to a predetermined threshold; and wherein the step of determining that the memory cells of the first sub-block have experienced significant read disturb occurs in response to the read cycle count exceeding the predetermined threshold (by teaching the read cycle table that is used to count a number of read cycles, such that the sub-block can be selectively refreshed when it hits a threshold [0047] [0062] [0266].
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the operation of the memory with sub-blocks as taught by Zhang_1 to include checking the sub-blocks for read disturb based on a read count by comparison to a threshold and writing the data from the disturbed sub-block to the other sub-block of the same physical block as taught by Han.
One of ordinary skill in the art would have been motivated to make this modification because selective refresh can restore the reliability of the memory system as taught by Han in [0289].
Regarding claim 4 and analogous claim 11 (omitting the limitation rejected under 35 USC §112(a) - written description):
The method as set forth in claim 1 (omitting the limitation rejected under 35 USC §112(a) - written description) is made obvious by Zhang_1-Park-Han-Zhang_2-Chen.
Zhang_1 does not explicitly disclose, but Han teaches further including the steps of: erasing the memory cells of the first sub-block; determining that the memory cells of the second sub-block have experienced significant read disturb; and programming the data in the memory cells of the second sub-block into the memory cells of the first sub-block (by teaching that after a sub-block is refreshed and the data from the sub-block being refreshed is programmed into the other sub-block of the same physical block of which the sub-block is being refreshed, the refreshed sub-block may be erased and the read count of the sub-block may be reset [0285-0289]. Accordingly, when the read count of the sub-block to which the data was transferred reaches the threshold, the data in the sub-block to which the data was transferred may be refreshed and the data being refreshed may be transferred back to the original sub-block of the same physical block [0266-0289]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the operation of the memory system as taught by Zhang_1 to include erasing a sub-block after its data has been refreshed, such that the data of the other sub-block may subsequently be refreshed if it hits the read count threshold by refreshing the data to the original sub-block as taught by Han.
One of ordinary skill in the art would have been motivated to make this modification because the reliability of the memory system may be improved as taught by Han in [0289].
Regarding claim 5 and analogous claim 12 (omitting the limitation rejected under 35 USC §112(a) - written description):
The method as set forth in claim 4 (omitting the limitation rejected under 35 USC §112(a) - written description) is made obvious by Zhang_1-Park-Han-Zhang_2-Chen.
Zhang_1 does not explicitly disclose, but Zhang_2 teaches, wherein after the step of programming the data in the memory cells of the second sub-block into the memory cells of the first sub-block, the data has the first order (by teaching that the programming order of the wordlines in each sub-block is from the middle outward. Accordingly, the programming order of the data stored (the data to be refreshed as taught by Han) in the first sub-block (i.e., top/bottom) is the opposite (i.e., middle-up or middle-down) from the programming order of the second sub-block (i.e., the opposite of top/bottom and the opposite programming order of middle-up/middle-down) (where the refreshed data is stored as taught by Han) [see Fig. 8] [0136]. Therefore, if the second sub-block is subsequently refreshed and stored again in the other sub-block of the same block (as taught by Han), its order would be restored to the original programming order of the first-sub block (i.e., back to the original programming order of the top/bottom sub-block which would be middle-up/middle-down) [see Fig. 8] [0136]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the programming of the data for refresh in the copyback operation from one half-block to another half-block in the same physical block as taught by Han to include reversing the programming order from the other sub-block such that the half-blocks are programmed from the middle-out as taught by Zhang_2.
One of ordinary skill in the art would have been motivated to make this modification because it achieves better reliability in the programming of the sub-blocks as taught by Zhang_2 in [0136].
Regarding claim 6 and analogous claim 13 (omitting the limitation rejected under 35 USC §112(a) - written description):
The method as set forth in claim 5 (omitting the limitation rejected under 35 USC §112(a) - written description) is made obvious by Zhang_1-Park-Han-Zhang_2-Chen.
Zhang_1 teaches, wherein the first sub-block is a lower sub-block and wherein the second sub-block is an upper sub-block (by teaching that the sub-blocks may include lower and upper decks or half-blocks [see Figs. 8 & 17]).
Zhang_1 does not explicitly disclose, but Zhang_2 teaches, wherein the step of programming the data in the memory cells of the lower sub-block into the memory cells of the upper sub-block includes programming according to the second programming direction that begins on the source side of the upper sub-block and proceeds towards the drain side of the upper sub-block (by teaching that the blocks are programmed from the middle-out, which for one of the sub-blocks would include the drain side to source side [Fig. 8] [0136]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the programming of the data for refresh in the copyback operation from one half-block to another half-block in the same physical block as taught by Han to include reversing the programming order from the other sub-block such that the half-blocks are programmed from the middle-out as taught by Zhang_2.
One of ordinary skill in the art would have been motivated to make this modification because it achieves better reliability in the programming of the sub-blocks as taught by Zhang_2 in [0136].
Regarding claim 7 and analogous claim 14 (omitting the limitation rejected under 35 USC §112(a) - written description):
The method as set forth in claim 6 (omitting the limitation rejected under 35 USC §112(a) - written description) is made obvious by Zhang_1-Park-Han-Zhang_2-Chen.
Zhang_1 does not explicitly disclose, but Zhang_2 teaches, wherein the step of programming the data in the memory cells of the upper sub-block into the memory cells of the lower sub-block includes programming according to the first programming direction that begins on a drain side of the lower sub-block and proceeds toward the source side of the lower sub-block (by teaching that the programming of each half of the sub-blocks is from the middle out, such that one is from the middle up and the other is from the middle-down, and such that one sub-block programming direction would include from the source side to the drain side and one would include from the drain side to the source side (830/832) [Fig. 8] [0136] (also see [Figs. 4B-4J], which depict source sides (those including SGS lines) and drain sides (those including SGD lines) [0085] [0133]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the programming of the data for refresh in the copyback operation from one half-block to another half-block in the same physical block as taught by Han to include reversing the programming order from the other sub-block such that the half-blocks are programmed from the middle-out as taught by Zhang_2.
One of ordinary skill in the art would have been motivated to make this modification because it achieves better reliability in the programming of the sub-blocks as taught by Zhang_2 in [0136].
Regarding claims 15-16 and 18-20 (omitting the limitation rejected under 35 USC §112(a) - written description):
Claims 15-16 and 18-20 would be rejected according to a similar analysis performed for claims 1-2 and 4-6 (omitting the limitation rejected under 35 USC §112(a) - written description), respectively, except that Zhang_1 does not explicitly disclose that the plurality of memory devices (2000) are high bandwidth flash (HBF) packages.
However, Kim teaches to use high bandwidth flash (HBF) packages (by teaching flash packages that include an interface chip to allow multiple flash packages to be combined to create greater bandwidth by decreasing capacitance and jitter to allow high capacity and high bandwidth [see Fig. 7.6.1] [§7.6, ¶1-7])
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the memory devices (2000) making up the SSD as taught by Zhang_1 to include the high bandwidth multichip flash packages taught by Kim.
One of ordinary skill in the art would have been motivated to make this modification because the use of the multi-chip package including the F-chip allows for higher I/O bandwidth, which solves a key bottleneck in SSD technology as taught by Kim in [§7.6, ¶1].
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CURTIS JAMES KORTMAN/ Primary Examiner, Art Unit 2139
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