DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 are rejected under pre-AIA 35 U.S.C. 102(a)(1) as being anticipated by Takabayashi (JP 2017142464A).
With regard to claim 1, Takabayashi teaches:
An optical waveguide device (Fig. 1A and 1B, 100) comprising
an optical waveguide substrate (Fig. 1B, 30); and
an optical semiconductor element (Fig. 1A and 1B, 20) including
a silicon waveguide (Fig. 1B, 201, 301) and mounted (Fig. 1B, 40, 101 and Fig. 2B, 313) on the optical waveguide substrate (Fig. 1B, 30), wherein
the optical waveguide substrate (Fig. 1B, 30) includes:
a substrate (Fig. 1B and 2B, 10);
a first cladding layer (Fig. 2B, 311) formed on the substrate (Fig 2B, 10);
a first core layer (Fig. 2B, 312) formed on the first cladding layer (Fig. 2B, 311); and
a second cladding layer (Fig. 2B 313 and Fig. 1B, 40) formed on the first cladding layer (Fig. 2B, 311) and the first core layer (Fig. 2B, 312),
the silicon waveguide (Fig. 1B, 201, 301) includes a second core layer (Fig. 1B, 312) optically coupled to the first core layer (Fig. 2B, 312), and
the optical semiconductor element (Fig.1B, 20) is fixed (Fig.1B, 40, 101, and Fig.2B, 313) to the substrate (Fig. 1B, 10) by the second cladding layer (Fig. 1B, 313 and Fig. 2B, 40).
With regard to claim 2, Takabayashi teaches:
The optical waveguide device (Fig. 1A and 1B, 100) as claimed in claim 1, wherein the second cladding layer (Fig. 1B, 313 and Fig. 2B, 40) includes an epoxy resin (Fig. 1B, 40) or a polyimide resin (Fig. 1B, 40).
With regard to claim 3, Takabayashi teaches:
The optical waveguide device (Fig. 1A and 1B, 100) as claimed in claim 1, wherein the first core layer (Fig. 2B, 311) and the second core layer (Fig. 2B, 311) are separated from each other.
With regard to claim 4, Takabayashi teaches:
The optical waveguide device (Fig. 1A and 1B, 100) as claimed in claim 1, wherein the optical semiconductor element (Fig. 1A and 1B, 20) includes:
a first side surface (embedded boundary teaches a boundary layer not labeled in figure);
a second side surface (embedded boundary teaches a boundary layer not labeled in figure) continuous with the first side surface (embedded boundary teaches a boundary layer not labeled in figure); and
a third side surface (embedded boundary teaches a boundary layer not labeled in figure) continuous with the first side surface (embedded boundary teaches a boundary layer not labeled in figure) on
a side opposite to the second side surface (embedded boundary teaches a boundary layer not labeled in figure), the second cladding layer (Fig. 1B, 313 and Fig. 2B, 40) includes:
a first surface (embedded boundary teaches a boundary layer not labeled in figure) in contact with the first side surface (embedded boundary teaches a boundary layer not labeled in figure);
a second surface (embedded boundary teaches a boundary layer not labeled in figure) in contact with the second side surface (embedded boundary teaches a boundary layer not labeled in figure); and
a third surface (embedded boundary teaches a boundary layer not labeled in figure) in contact with the third side surface (embedded boundary teaches a boundary layer not labeled in figure).
Claim 1-4 are rejected under pre-AIA 35 U.S.C. 102(a)(1) as being Tanaka (JP 5728964 B2) by.
With regard to claim 1, Tanaka teaches:
An optical waveguide device (Fig. 1, 1) comprising:
an optical waveguide substrate (Fig. 1, 10); and
an optical semiconductor element (Fig. 1, 20) including a silicon waveguide (Fig. 1, 15) and mounted (Fig. 1, 17) on the optical waveguide substrate (Fig. 1, 10), wherein
the optical waveguide substrate (Fig. 1, 10) includes:
a substrate (Fig. 1, 11);
a first cladding layer (Fig. 1, 12) formed on the substrate (Fig. 1, 11);
a first core layer (Fig. 1, 22) formed on the first cladding layer (Fig. 1, 23); and
a second cladding layer (Fig. 1, 27) formed on the first cladding layer (Fig. 1, 23) and the first core layer (Fig. 1, 21),
the silicon waveguide (Fig. 1, 15) includes a second core layer (Fig. 1, 12) optically coupled to the first core layer (Fig. 1, 22), and
the optical semiconductor element (Fig. 1, 20) is fixed (Fig. 1, 17) to the substrate (Fig. 1, 11) by the second cladding layer (Fig. 1, 27).
With regard to claim 2, Tanaka teaches:
The optical waveguide device (Fig. 1, 1) as claimed in claim 1, wherein the second cladding layer (Fig. 1, 27) includes an epoxy resin (embedded boundary teaches materials not labeled in figure) or a polyimide resin (embedded boundary teaches materials not labeled in figure).
With regard to claim 3, Tanaka teaches:
The optical waveguide device (Fig. 1, 1) as claimed in claim 1, wherein the first core layer (Fig 1, 22) and the second core layer (Fig 1, 22) are separated from each other.
With regard to claim 4, Tanaka teaches:
The optical waveguide device (Fig. 1, 1) as claimed in claim 1, wherein the optical semiconductor element (Fig. 1, 20) includes:
a first side surface (embedded boundary teaches a boundary layer not label in figure);
a second side surface (embedded boundary teaches a boundary layer not label in figure) continuous with the first side surface (embedded boundary teaches a boundary layer not label in figure); and
a third side surface (embedded boundary teaches a boundary layer not label in figure) continuous with the first side surface (embedded boundary teaches a boundary layer not label in figure) on
a side opposite to the second side surface (embedded boundary teaches a boundary layer not label in figure), the second cladding layer (Fig. 1, 27) includes:
a first surface (embedded boundary teaches a boundary layer not label in figure) in contact with the first side surface (embedded boundary teaches a boundary layer not label in figure);
a second surface (embedded boundary teaches a boundary layer not label in figure) in contact with the second side surface (embedded boundary teaches a boundary layer not label in figure); and
a third surface (embedded boundary teaches a boundary layer not label in figure) in contact with the third side surface (embedded boundary teaches a boundary layer not label in figure).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. The following references teach splitter and/or fan-out devices similar to applicant’s JP 2017142464A, JP 5728964 B2.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSIMAR D COLINDREZ whose telephone number is 571-270-0533. The examiner can normally be reached Monday-Friday 8:00am-4pm EST.
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/JOSIMAR D COLINDREZ/ Examiner, Art Unit 2874
/THOMAS A HOLLWEG/Supervisory Patent Examiner, Art Unit 2874
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