DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. However, should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e). Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Information Disclosure Statement
The information disclosure statements (IDS) filed on May 10th, 2024, November 7th, 2024, December 18th, 2024, July 10th, 2025, and February 4th, 2026, are being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The specification is objected to as the section headings are in bold type. Pursuant to MPEP
608.01(a) and 37 C.F.R. 1.77(c), “The text of the specification sections defined in paragraphs (b)(1)
through (b)(12) of this section, if applicable, should be preceded by a section heading in uppercase and
without underlining or bold type” (emphasis added). The instant application has section headings with
underlining. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claims 1, 8, and 12, the term “area” in Claims 1, 8, and 12 is a relative term which renders the claim indefinite. The term “area” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. More specifically, the “area” of the metal layer and the “area” of the chip layer could be referring to the three-dimensional surface area of those layers, a top-surface area, or, in the instance where more sophisticated shapes are used (i.e., a trapezoid where the top-surface and the bottom-surface area are different), a separate bottom-surface area. For the benefit of compact prosecution, the Examiner will interpret “area” as stated in Claims 1, 8, and 12 to be referencing the top-surface area of the respective layers.
Regarding Claims 2-7, 9-11, and 13-18, due to their dependence upon previously rejected claims (i.e., Claims 1, 8, and 12, respectively), they are additionally rejected.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7, 12-13, and 16-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin, et al (US 20230352361 A1; hereinafter referred to as Lin).
Regarding Claim 1, Lin discloses a power module structure, comprising:
a substrate (insulating substrate 100, [0023], Fig 1C);
a copper layer disposed on the substrate (first conductive layer 102, [0015], Fig. 1C; “the first conductive layer 102 . . . may be metal layers, such as copper layers”);
a metal layer disposed on the copper layer (third conductive layer 110, [0017], Fig. 1C), wherein the metal layer has a smaller area than that of the copper layer (Fig. 1C; the third conductive layer 110 has a smaller top-surface area than the first conductive layer 102); and
a chip disposed on the metal layer (first chip 112, [0019], Fig. 1C), wherein the chip has a smaller area than that of the metal layer (Fig 1C; the chip has a smaller top-surface area than the third conductive layer 110).
Regarding Claim 2, Lin discloses the power module structure as claimed in claim 1, wherein the substrate comprises aluminum oxide ([0023], “the material of the insulating substrate 100 may be silicon, silicon oxide, aluminum oxide, aluminum nitride, boron nitride or a combination thereof”).
Regarding Claim 3, Lin discloses the power module structure as claimed in claim 1, wherein the metal layer comprises copper, silver or aluminum ([0017], “the third conductive layer 110 may be a metal layer, such as a copper layer, but the embodiment of the present disclosure is not limited thereto”).
Regarding Claim 4, Lin discloses the power module structure as claimed in claim 1, wherein the metal layer comprises a rectangle, a circle, a polygon, or a trapezoid in shape (Fig. 1C; the second conductive layer forms a closed shape/polygon).
Regarding Claim 5, Lin discloses the power module structure as claimed in claim 1, wherein the metal layer is in contact with the copper layer (Fig. 1C; the third conductive layer [metal layer] is in contact with the first conductive layer [copper layer] through the first thermal interface material layer 108).
Regarding Claim 6, Lin discloses the power module structure as claimed in claim 1, wherein the chip comprises a power component ([0002], “power device”).
Regarding Claim 7, Lin discloses the power module structure as claimed in claim 1, wherein the chip is in contact with the metal layer (Fig. 1C; the first chip [chip] is in contact with the third conductive layer [metal layer] through the conductive adhesion layer 113).
Regarding Claim 12, Lin discloses a power module structure, comprising:
a substrate (insulating substrate 100, [0015], Fig. 5);
a copper layer disposed on the substrate (first conductive layer 102 and second conductive layer 104, [0015], Fig. 5; “the first conductive layer 102 and the second conductive layer 104 may be metal layers, such as copper layers”);
a first metal layer disposed on the copper layer (third conductive layer 110, [0017], Fig. 5), wherein the first metal layer has a smaller area than that of the copper layer (Fig. 5; the top-surface area of the third conductive layer is smaller than the top-surface area of the first conductive layer);
a second metal layer disposed on the copper layer (fourth conductive layer 502, [0033], Fig. 5), wherein the second metal layer has a smaller area than that of the copper layer (Fig. 5; the top-surface area of the fourth conductive metal layer is smaller than the top-surface area of the second conductive layer), and the second metal layer is separated from the first metal layer (Fig. 5; the two stacks are separated from one another);
a first chip disposed on the first metal layer (first chip 112, [0033], Fig. 5), wherein the first chip has a smaller area than that of the first metal layer (Fig. 5; the first chip has a smaller top-surface area than the third conductive layer); and
a second chip disposed on the second metal layer (second chip 114, [0033], Fig. 5), wherein the second chip has a smaller area than that of the second metal layer (Fig. 5; the second chip has a smaller top-surface area than the fourth conductive layer).
Regarding Claim 13, Lin discloses the power module structure as claimed in claim 12, wherein the first metal layer and the second metal layer comprise a rectangle, a circle, a polygon or a trapezoid in shape (Fig. 5; the third and fourth conductive layers form a closed shape/polygon).
Regarding Claim 16, Lin discloses the power module structure as claimed in claim 12, wherein the first metal layer and the second metal layer are in contact with the copper layer (Fig. 5; the third and fourth conductive layers [first and second metal layer] are in contact with the first and second conductive layers [copper layer] through respective first and second thermal interface material layers 108/500).
Regarding Claim 17, Lin discloses the power module structure as claimed in claim 12, wherein the first chip is in contact with the first metal layer (Fig. 5; the first chip is in contact with the third conductive layer through conductive adhesion layer 113).
Regarding Claim 18, Lin discloses the power module structure as claimed in claim 12, wherein the second chip is in contact with the second metal layer (Fig. 5; the second chip is in contact with the fourth conductive layer through conductive adhesion layer 113).
Claim(s) 8-11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gottwald, et al (US 20190363043 A1; hereinafter referred to as Gottwald).
Regarding Claim 8, Gottwald discloses a power module structure (power-electronic metal-ceramic module 10, Fig. 6), comprising:
a substrate (ceramic carrier 14, [0036], Fig. 6);
a copper layer disposed on the substrate (metal top ply 16, [0036], Fig. 6; “the metal plies 16, 18 are, for example and in particular, copper plies”);
a chip disposed on the copper layer (electronic component 30, [0039], Fig. 6); and
a metal layer disposed on the copper layer and surrounding the chip (metal layer 22, [0039], Fig. 6), wherein the metal layer has a smaller area than that of the copper layer (Fig. 6; the metal layer has a smaller area than the copper layer as a portion of the top-surface layer is removed in order to place the chip).
Regarding Claim 9, Gottwald discloses the power module structure as claimed in claim 8, wherein the chip and the metal layer have different thicknesses ([0058], Fig. 12).
Regarding Claim 10, Gottwald discloses the power module structure as claimed in claim 8, wherein the chip and the metal layer are in contact with the copper layer ([0039] Fig. 10).
Regarding Claim 11, Gottwald discloses the power module structure as claimed in claim 8, wherein the chip is in contact with the metal layer (Figs. 10, 11, 12; the chip is in contact with the metal layer through the resin layer 58).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a) Determining the scope and contents of the prior art.
b) Ascertaining the differences between the prior art and the claims at issue.
c) Resolving the level of ordinary skill in the pertinent art.
d) Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin as applied to claims 1-7, 12-13, and 16-18 above, and further in view of Lee (US 20230023610A1; hereinafter referred to as Lee).
Regarding Claim 14, Lin discloses the power module structure as claimed in claim 12.
Lin is silent on the first metal layer and the second metal layer having different shapes.
However, in analogous art, Lee discloses that metal layers (spacers 30) that are on a copper layer (electrode pattern 20) can have different shapes (Figs. 1-2; one shape is expressly disclosed as a square and another shape as a rectangle).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to allow for the first and second metal layers as taught in Lin to have different shapes as disclosed in Lee. One would be motivated to do so as the shape of the metal layers does not provide criticality in the instant application, and, therefore, the difference in shape between the metal layers can be considered an obvious variant of one that does not have differing shapes. See MPEP 2144.04(IV)(B).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin as applied to claims 1-7, 12-13, and 16-18 above, and further in view of Kojima, et al (EP3093882 A1; hereinafter referred to as Kojima).
Regarding Claim 15, Lin discloses the power module structure as claimed in claim 12.
Lin is silent on the first metal layer and the second metal layer having different thicknesses, as it only discloses the metal layers being of equal thickness.
However, as taught in Kojima, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to optimize the thicknesses of the first and second metal layer in order to effectively meet the heat dissipation requirements of the layers associated chip (Kojima: [0063-0065]). If the first chip associated with the first metal layer was outputting increased heat compared to the second chip associated with the second metal layer, then a difference in thickness of the first and second metal layers would result in the expected outcome of increased heat dissipation, thus making the thickness of the first metal layer and the second metal layer a result effective variable. See MPEP 2144.05(II).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
(a) Fuji (US 20220037260 A1); discloses a power module structure with a copper layer, metal layer, and semiconductor chip.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Noah C. Robertson whose telephone number is (571) 317-0595. The examiner can normally be reached Monday-Friday 9:30 AM - 6:30 PM (Eastern Time Zone).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge, can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/Noah C. Robertson/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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