POWER MODULE STRUCTURE

Application No. 18/660,926

• Filed: May 10, 2024
• Priority: Jul 12, 2023 — provisional 63/513,176
  • Dec 06, 2023 — CN 202311661683.0
• Examiner: ROBERTSON, NOAH CHRISTOPHER
• Assignee: Delta Electronics Inc.
• OA Round: 2 (Final)

Office Action

DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .

Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. However, should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e). Failure to provide a certified translation may result in no benefit being accorded for the non-English application.

Information Disclosure Statement
The information disclosure statements (IDS) filed on May 10th, 2024, November 7th, 2024, December 18th, 2024, July 10th, 2025, and February 4th, 2026, are being considered by the examiner.

Specification
The specification objections (e.g., the title and specification header objections) as previously issued have been withdrawn pursuant to Applicant’s amendments dated September 2nd, 2026.

Claim Rejections - 35 USC § 112
The 35 U.S.C. § 112(b) rejections as previously issued have been withdrawn pursuant to Applicant’s amendments dated September 2nd, 2026.

Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –

(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.

Claim(s) 8-11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gottwald, et al (US 20190363043 A1; hereinafter referred to as Gottwald).

Regarding Claim 8, Gottwald discloses a power module structure (power-electronic metal-ceramic module 10, Fig. 6), comprising:
a substrate (ceramic carrier 14, [0036], Fig. 10);
a copper layer disposed on the substrate, wherein the copper layer has the same top-surface area as that of the substrate (metal top ply 16, [0036], Fig. 10; “the metal plies 16, 18 are, for example and in particular, copper plies” and, as disclosed in Fig. 10, the metal top ply 16 has a same top-surface area as that of the ceramic substrate);
a chip disposed on the copper layer (electronic component 30, [0039], Fig. 10); and
a metal layer disposed on the copper layer and surrounding the chip (metal layer 22, [0039], Fig. 6), wherein the metal layer has a smaller area than that of ​​the copper layer (Fig. 6; the metal layer has a smaller area than the copper layer as a portion of the top-surface layer is removed in order to place the chip).

Regarding Claim 9, Gottwald discloses the power module structure as claimed in claim 8, wherein the chip and the metal layer have different thicknesses ([0058], Fig. 12).

Regarding Claim 10, Gottwald discloses the power module structure as claimed in claim 8, wherein the chip and the metal layer are in contact with the copper layer ([0039], Fig. 10).

Regarding Claim 11, Gottwald discloses the power module structure as claimed in claim 8, wherein the chip is in contact with the metal layer (Figs. 10, 11, 12; the chip is in contact with the metal layer through the resin layer 58).

Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.

This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.

Claim(s) 1-7, 12-13, and 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable by Lin, et al (US 20230352361 A1; hereinafter referred to as Lin) and further in view of Gottwald.

Regarding Claim 1, Lin discloses a power module structure, comprising:
a substrate (insulating substrate 100, [0023], Fig 1C);
a copper layer disposed on the substrate (first conductive layer 102, [0015], Fig. 1C; “the first conductive layer 102 . . . may be metal layers, such as copper layers”);
a metal layer disposed on the copper layer (third conductive layer 110, [0017], Fig. 1C), wherein the metal layer has a smaller area than that of ​​the copper layer (Fig. 1C; the third conductive layer 110 has a smaller top-surface area than the first conductive layer 102); and
a chip disposed on the metal layer (first chip 112, [0019], Fig. 1C), wherein the chip has a smaller top-surface area than that of ​​the metal layer (Fig 1C; the chip has a smaller top-surface area than the third conductive layer 110).
Lin fails to explicitly disclose the copper layer has the same top-surface area as that of the substrate.
However, in analogous art, Gottwald discloses a power module structure (Gottwald: circuit board module 60, Fig. 10) with a copper layer disposed on the substrate (Gottwald: top metal ply 16, Fig. 10; “The metal plies 16, 18 are, for example and in particular, copper plies” and as such would be a copper layer) having the same top-surface area as that of the substrate (Gottwald: Fig. 10).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the structure of Lin such that the copper layer has the same top-surface area as that of the substrate, as disclosed by Gottwald. One would be motivated to do so because the equal top surface-area allows for better heat spreading results as there is greater contact between the copper layer and the ceramic substrate (Gottwald: [0013]).

Regarding Claim 2, Lin/Gottwald discloses the power module structure as claimed in claim 1, wherein the substrate comprises aluminum oxide (Lin: [0023], “the material of the insulating substrate 100 may be silicon, silicon oxide, aluminum oxide, aluminum nitride, boron nitride or a combination thereof”).

Regarding Claim 3, Lin/Gottwald discloses the power module structure as claimed in claim 1, wherein the metal layer comprises copper, silver or aluminum (Lin: [0017], “the third conductive layer 110 may be a metal layer, such as a copper layer, but the embodiment of the present disclosure is not limited thereto”).

Regarding Claim 4, Lin/Gottwald discloses the power module structure as claimed in claim 1, wherein the metal layer comprises a rectangle, a circle, a polygon, or a trapezoid in shape (Lin: Fig. 1C; the second conductive layer forms a closed shape/polygon).

Regarding Claim 5, Lin/Gottwald discloses the power module structure as claimed in claim 1, wherein the metal layer is in contact with the copper layer (Lin: Fig. 1C; the third conductive layer [metal layer] is in contact with the first conductive layer [copper layer] through the first thermal interface material layer 108).

Regarding Claim 6, Lin/Gottwald discloses the power module structure as claimed in claim 1, wherein the chip comprises a power component (Lin: [0002], “power device”).

Regarding Claim 7, Lin/Gottwald discloses the power module structure as claimed in claim 1, wherein the chip is in contact with the metal layer (Lin: Fig. 1C; the first chip [chip] is in contact with the third conductive layer [metal layer] through the conductive adhesion layer 113).

Regarding Claim 12, Lin discloses a power module structure, comprising:
a substrate (insulating substrate 100, [0015], Fig. 5);
a copper layer disposed on the substrate (first conductive layer 102 and second conductive layer 104, [0015], Fig. 5; “the first conductive layer 102 and the second conductive layer 104 may be metal layers, such as copper layers”);
a first metal layer disposed on the copper layer (third conductive layer 110, [0017], Fig. 5), wherein the first metal layer has a smaller top-surface area than that of ​​the copper layer (Fig. 5; the top-surface area of the third conductive layer is smaller than the top-surface area of the first conductive layer);
a second metal layer disposed on the copper layer (fourth conductive layer 502, [0033], Fig. 5), wherein the second metal layer has a smaller top-surface area than that of ​​the copper layer (Fig. 5; the top-surface area of the fourth conductive metal layer is smaller than the top-surface area of the second conductive layer), and the second metal layer is separated from the first metal layer (Fig. 5; the two stacks are separated from one another);
a first chip disposed on the first metal layer (first chip 112, [0033], Fig. 5), wherein the first chip has a smaller top-surface area than that of ​​the first metal layer (Fig. 5; the first chip has a smaller top-surface area than the third conductive layer); and
a second chip disposed on the second metal layer (second chip 114, [0033], Fig. 5), wherein the second chip has a smaller area than that of ​​the second metal layer (Fig. 5; the second chip has a smaller top-surface area than the fourth conductive layer), and the first chip and the second chip are bonded with the first metal layer and the second metal layer by silver paste ([0019], “in other embodiments, the conductive adhesion layer 113 may also be a bonding layer formed by sintering silver or copper”).
Lin fails to disclose the first metal layer and the second metal layer are bonded with the copper layer by solder paste.
However, in analogous art, Gottwald discloses the first metal layer and the second metal layer (Gottwald: metal layers 22, [0038], Fig. 4) are bonded with the copper layer (Gottwald: top metal ply 16, [0038], Fig. 4) by solder paste (Gottwald: layer 20, [0038]).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date to bind the first and second metal layer with the copper layer of Lin with a solder paste, as disclosed by Gottwald. One would be motivated to do so in order to assist in increasing adhesion/bonding strength between the copper layer and the metal layers (Gottwald: [0038]).

Regarding Claim 13, Lin/Gottwald discloses the power module structure as claimed in claim 12, wherein the first metal layer and the second metal layer comprise a rectangle, a circle, a polygon or a trapezoid in shape (Lin: Fig. 5; the third and fourth conductive layers form a closed shape/polygon).

Regarding Claim 16, Lin/Gottwald discloses the power module structure as claimed in claim 12, wherein the first metal layer and the second metal layer are in contact with the copper layer (Lin: Fig. 5; the third and fourth conductive layers [first and second metal layer] are in contact with the first and second conductive layers [copper layer] through respective first and second thermal interface material layers 108/500).

Regarding Claim 17, Lin/Gottwald discloses the power module structure as claimed in claim 12, wherein the first chip is in contact with the first metal layer (Lin: Fig. 5; the first chip is in contact with the third conductive layer through conductive adhesion layer 113). ​

Regarding Claim 18, Lin/Gottwald discloses the power module structure as claimed in claim 12, wherein the second chip is in contact with the second metal layer (Lin: Fig. 5; the second chip is in contact with the fourth conductive layer through conductive adhesion layer 113).

Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin/Gottwald as applied to claims 1-7, 12-13, and 16-18 above, and further in view of Lee (US 20230023610A1; hereinafter referred to as Lee).

Regarding Claim 14, Lin/Gottwald discloses the power module structure as claimed in claim 12.
The combination of Lin/Gottwald is silent on the first metal layer and the second metal layer having different shapes.
However, in analogous art, Lee discloses that metal layers (Lee: spacers 30) that are on a copper layer (electrode pattern 20) can have different shapes (Lee: Figs. 1-2; one shape is expressly disclosed as a square and another shape as a rectangle).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to allow for the first and second metal layers as taught in Lin to have different shapes as disclosed in Lee. One would be motivated to do so as the shape of the metal layers does not provide criticality in the instant application, and, therefore, the difference in shape between the metal layers can be considered an obvious variant of one that does not have differing shapes. See MPEP 2144.04(IV)(B).

Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin/Gottwald as applied to claims 1-7, 12-13, and 16-18 above, and further in view of Kojima, et al (EP3093882 A1; hereinafter referred to as Kojima).

Regarding Claim 15, Lin/Gottwald discloses the power module structure as claimed in claim 12.
The combination of Lin/Gottwald is silent on the first metal layer and the second metal layer having different thicknesses, as it only discloses the metal layers being of equal thickness.
However, as taught in Kojima, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to optimize the thicknesses of the first and second metal layer in order to effectively meet the heat dissipation requirements of the layers associated chip (Kojima: [0063-0065]). If the first chip associated with the first metal layer was outputting increased heat compared to the second chip associated with the second metal layer, then a difference in thickness of the first and second metal layers would result in the expected outcome of increased heat dissipation, thus making the thickness of the first metal layer and the second metal layer a result effective variable. See MPEP 2144.05(II).

Response to Arguments
Applicant’s arguments, see pages 7-8, filed September 2nd, 2026, with respect to the rejection(s) of Claim(s) 1 under 35 USC 102(a)(1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Lin, et al. and Gottwald, as Gottwald discloses the added limitation of the copper layer having the same top-surface area as that of the substrate.

Applicant’s arguments, see pages 8-9, filed September 2nd, 2026, with respect to the rejection(s) of Claim(s) 8 under 35 USC 102(a)(1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Gottwald. The new rejection using Gottwald uses the further disclosed embodiment as shown in Fig. 10, which discloses the copper layer having the same top-surface area as that of the substrate.

Applicant’s arguments, see pages 9-10 filed September 2nd, 2026, with respect to the rejection(s) of Claim(s) 12 under 35 USC 102(a)(1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Lin, et al. and Gottwald, as Gottwald discloses the added limitations of the first metal layer and the second metal layer being bonded to the copper layer by a solder paste, and Lin discloses in a further embodiment that the first chip and the second chip are bonded with the first metal layer and the second metal layer by silver paste (e.g., sintering silver).

Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).

A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.

Any inquiry concerning this communication or earlier communications from the examiner should be directed to Noah C. Robertson whose telephone number is [phone]. The examiner can normally be reached Monday-Friday 9:30 AM - 6:30 PM (Eastern Time Zone).

Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.

If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge, can be reached at [phone]. The fax phone number for the organization where this application or proceeding is assigned is [phone].

Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at [phone] (toll-free). If you would like assistance from a USPTO Customer Service Representative, call [phone] (IN USA OR CANADA) or [phone].

/Noah C. Robertson/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812

Prosecution Timeline

• May 10, 2024: Application Filed
• Jun 03, 2026: Non-Final Rejection mailed — §102, §103, §112
• Sep 02, 2026: Response Filed
• Sep 15, 2026: Response after Non-Final Action
• Sep 23, 2026: Final Rejection mailed — §102, §103, §112 (current)