3Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species I (Fig. 3) and Subspecies III (Figs. 5 and 7A) in the reply filed on June 17, 2026, is acknowledged. The traversal is on the grounds that the base claims all recite a separation structure including a plurality of support patterns and that a single search of the prior art will necessarily encompass the core elements of the species. This is not found persuasive because the differences among the species still render them patentably distinct, and thus prior art that reads on one species may not read on the others, thus creating a search burden.
The requirement is still deemed proper and is therefore made FINAL.
Claim Objections
Claims 1, 11, and 16 objected to because of the following informalities:
In claim 1, line 3, “each the plurality” should be “each of the plurality”.
In claim 1, line 4, “plurality of peripheral circuit structure” should be “plurality of peripheral circuit structures”.
In claim 1, line 5, “plurality of stacked structure” should be “plurality of stacked structures”.
In claim 11, line 3, “plurality of stacked structure” should be “plurality of stacked structures”.
In claim 16, line 2, “three-dimensional semiconductor memory device” should be “a three-dimensional semiconductor memory device”.
In claim 16, line 8, “plurality of stacked structured” should be “plurality of stacked structures”.
In claim 16, line 9, “plurality of peripheral circuit structure” should be “plurality of peripheral circuit structures”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8-9 and 14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites the limitation, “wherein each of the plurality of support patterns has a first side surface covering a side surface of each of the plurality of support patterns corresponding to each of the plurality of support patterns”. This contradicts the specification, which instead shows a first side surface of each of the plurality of support patterns covering a side surface of each of the separation patterns corresponding to each of the plurality of support patterns. It is also unclear how a surface of a support pattern can be in contact with a surface of another support patten when the support patterns alternate with separation patterns, as required by claim 7, which claim 8 is dependent on.
Claim 9 is also rejected because it is dependent on claim 8 and thus inherits the deficiencies of the parent claim. In addition, claim 9 is rejected due to the additional issue, separate from that inherited from claim 8, detailed below.
Claim 9 recites the limitation, “the side surface of each of the plurality of separation patterns”, in lines 1-2. There is insufficient antecedent basis for this limitation in the claim.
Claim 14 recites the limitation, “the plurality of internal insulating layers”, in lines 1-2. There is insufficient antecedent basis for this limitation in the claim.
For examination purposes, the following will be assumed:
The new limitation in claim 8 was meant to read “wherein each of the plurality of support patterns has a first side surface covering a side surface of each of the plurality of separation patterns corresponding to each of the plurality of support patterns”.
The plurality of internal insulating layers recited in claim 14 were instead meant to be a single insulating layer, as recited in claim 13.
These rejections may be overcome by:
Amending claim 8 to read as assumed for examination purposes. This would also correct the lack of antecedent basis found separately in claim 9.
Either recite a plurality of internal insulating layers in claim 11 or 13 or amend claim 14 to only recite a single internal insulating layer.
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Fig. 21A of Kraman, reproduced with annotations and notation of the first and second directions added by the examiner.
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Fig. 21B of Kraman, reproduced with annotations and notation of the second and third directions added by the examiner.
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Fig. 1 of Lee, reproduced with annotation added by the examiner.
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Fig. 2 of Lee, reproduced with annotations added by the examiner.
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Fig. 5 of Lee, reproduced with annotation added by the examiner.
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Fig. 6 of Lee, reproduced with annotation added by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kraman et. al., Pub. No. US 2024/0414917, hereafter referred to as Kraman, in view of Lee et. al., Pub. No. US 2022/0115390, hereafter referred to as Lee.
Regarding claim 1, Kraman teaches “A three-dimensional semiconductor memory device” (Kraman [0001]) “comprising: …a plurality of stacked structures” (Kraman Fig. 21A, reproduced above with annotations added by the examiner), “each the plurality of stacked structures including a plurality of gate electrodes” (Kraman [0152]: “The electrically conductive layers 46 may comprise source side select gate electrodes, word lines overlying the source side select gate electrodes, and drain side select gate electrodes overlying the word lines.”; Fig. 21A, electrically conductive layers 46) “stacked… in a first direction perpendicular to a lower surface of the substrate” (Kraman Fig. 21A; note that the electrically conductive layers 46 and the insulating layers 32 are stacked in the first direction), “and the plurality of stacked structure being spaced apart from each other in a second direction parallel to the lower surface of the substrate” (Kraman Fig. 21A; note that the stacks are separated from each other by isolation pillars 73); “a separation structure extending between the plurality of stacked structures in a third direction intersecting the first direction and the second direction” (Kraman Figs. 21A and B; support pillars 20; note that the support pillars 20 and the isolation pillars 73 serve the same purpose, and thus the support pillars 20 will be treated as the separation structure; see [0164]: “The isolation pillar structures 73 and the support pillar structures 20 are lateral isolation structures that provide electrical isolation between neighboring pairs of electrically conductive strips 84”), “the separation structure including a plurality of support patterns that are spaced apart from each other in the third direction in the separation structure” (Kraman Figs. 21A and B, isolation pillars 73; note that the isolation pillars 73 are spaced apart in the third direction’ note that the support pillars 20 and the isolation pillars 73 serve the same purpose, and thus the isolation pillars 73 will be treated as the support patterns; see [0164]); but does not teach “a plurality of peripheral circuit structures on a substrate”, “(a plurality of stacked structures) on the plurality of peripheral circuit structure”, and “an internal insulating layer surrounding a side surface of each of the plurality of support patterns.”
Lee, on the other hand, does teach “a plurality of peripheral circuit structures on a substrate” (Lee [0047]; Fig. 6, peripheral circuit structure PS), “(a plurality of stacked structures) on the plurality of peripheral circuit structure” (Lee [0053]; Fig. 6, cell array structure CS), and “an internal insulating layer” (Lee [0105]; Fig. 6, second spacer part SP2, which is part of the second support structure WC2) “surrounding a side surface of each of the plurality of support patterns” (Lee [0105]: “The second filler part FL2 may fill a space surrounded by the second spacer part SP2.”; Fig. 6, second filler part FL2). Lee further teaches that the spacer parts are formed using atomic layer deposition (ALD) and the filler parts by chemical vapor deposition (CVD) (Lee [0095]).
The peripheral circuit structure of Lee can be incorporated into the device of Kraman as a similar peripheral circuit structure disposed beneath the stacked structures. Furthermore, the internal insulating layer of Lee can be incorporated into the device of Kraman as an internal insulating layer surrounding the support patterns.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have incorporated a peripheral circuit structure as taught by Lee into the device of Kraman because doing so would provide the necessary hardware to read from and write to the memory device, and it would be a simple combination of elements of the two disclosures. Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have included a spacer layer surrounding the support patterns because the spacer would protect the gate electrodes from reacting with the vapor used in forming the filler during the CVD process and it would be a simple combination of elements of the two disclosures.
Regarding claim 2, the combined device of Kraman and Lee described in the discussion of claim 1 teaches “The three-dimensional memory device of claim 1”, but does not teach “wherein the internal insulating layer includes metal oxide.”
Kraman, on the other hand, teaches the existence of metal oxides with high dielectric constants (high-k dielectrics) (Kraman [0070]: “…dielectric metal oxides that are commonly known as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.)…”).
The teaching of high-k dielectric metal oxides of Kraman can be incorporated into the combined device of Kraman and Lee described in the discussion of claim 1 through the use of such a material for the second spacer part of Lee. The combined device teaches “wherein the internal insulating layer includes metal oxide” (Lee [0105]; Fig. 6, second spacer part SP2, which is made of a metal oxide in the combined device; see Kraman [0070]).
It would have been obvious to one of ordinary skill in the art to have used a high-k metal oxide as the second spacer layer in the combined device of Kraman and Lee described in the discussion of claim 1 because it would provide better shielding against stray electric fields from a neighboring device region and it would be a simple substitution of one element for another.
Regarding claim 3, the combined device of Kraman and Lee described in the discussion of claim 1 further teaches “The three-dimensional memory device of claim 1, wherein the internal insulating layer is interposed between the plurality of support patterns and the plurality of gate electrodes” (Lee Fig. 6; note that the second spacer part SP2 is interposed between the second filler part FL2 and the gate electrodes ELa and ELb).
Regarding claim 4, the combined device of Kraman and Lee described in the discussion of claim 1 further teaches “The three-dimensional memory device of claim 1, wherein the plurality of support patterns are spaced apart from the plurality of gate electrodes” (Lee Fig. 6; the fact that the second spacer part SP2 is interposed between the second filler part FL2 and the gate electrodes ELa and ELb means that the second filler part FL2 is spaced apart from the gate electrodes).
Regarding claim 5, the combined device of Kraman and Lee described in the discussion of claim 1 anticipates “The three-dimensional memory device of claim 1, wherein an upper surface of each of the plurality of support patterns has at least one shape of a circle, an oval, and a rectangle with four rounded corners” by teaching support patterns in the shape of an oval (Kraman Fig. 21B; note that the isolation pillars 73 have the shape of an oval).
Regarding claim 6, the combined device of Kraman and Lee described in the discussion of claim 1 anticipates “The three-dimensional memory device of claim 1, wherein the separation structure includes a plurality of separation structures disposed in the second direction” (Kraman Fig. 21B; note that the rows of isolation pillars 73 and support pillars 20 are disposed along the second direction), “wherein each of the plurality of separation structures includes the plurality of support patterns” (Kraman Fig. 21B; note that the support pillars 20 alternate with the isolation pillars 73), “and wherein the plurality of support patterns are arranged in a zigzag shape or a row in the second direction” by teaching support pillars arranged in rows along the second direction (Kraman Fig. 21B; note that the isolation pillars 73 are arranged in rows along the second direction).
Regarding claim 7, the combined device of Kraman and Lee described in the discussion of claim 1 further teaches “The three-dimensional memory device of claim 1, wherein the separation structure further includes a plurality of separation patterns” (Kraman Fig. 21B; note that there is a plurality of support pillars 20 in each row extending along the third direction) “alternately arranged with the plurality of support patterns in the third direction” (Kraman Fig. 21B; note that the support pillars 20 within a row extending along the third direction alternate with isolation pillars 73).
Regarding claim 8, the combined device of Kraman and Lee as applied to claim 1 above further teaches “The three-dimensional memory device of claim 7, wherein each of the plurality of support patterns has a first side surface” (Kraman Fig. 21B; first side surface of isolation pillar 73) “covering a side surface of each of the plurality of support patterns corresponding to each of the plurality of support patterns” (Kraman Fig. 21B; side surface of the support pillar 20; note that, per the discussion of the rejection of this claim under 35 U.S.C. 112(b), it is assumed that “support patterns” in this limitation is meant to be “separation patterns”), “and wherein the internal insulating layer covers the first side surface of each of the plurality of support patterns” (Lee Fig. 6; note that the second spacer part SP2 covers the first side surface of the second filler part FL2).
Regarding claim 9, the combined device of Kraman and Lee as applied to claim 1 above further teaches “The three-dimensional memory device of claim 8, wherein the side surface of each of the plurality of separation patterns is curved toward an inside of each of the plurality of separation patterns” (Kraman Fig. 21B; note that the side surfaces of the support pillars 20 are curved toward the interiors of the pillars).
Regarding claim 10, the combined device of Kraman and Lee as applied to claim 1 above further teaches “The three-dimensional memory device of claim 7, wherein the plurality of support patterns are spaced apart from the plurality of separation patterns” (Kraman Fig. 21B, isolation pillars 73 and support pillars 20; Lee Fig. 6, note that the second filler part FL2 would be spaced apart from the support pillars 20 of Kraman by the second spacer part SP2 in the combined device).
Regarding claim 11, Kraman teaches “A three-dimensional semiconductor memory device” (Kraman [0001]) “comprising: …a plurality of stacked structures” (Kraman Fig. 21A, reproduced above with annotations added by the examiner), “each the plurality of stacked structures including a plurality of gate electrodes” (Kraman [0152]; Fig. 21A, electrically conductive layers 46) “stacked… in a first direction perpendicular to a lower surface of the substrate” (Kraman Fig. 21A; note that the electrically conductive layers 46 and the insulating layers 32 are stacked in the first direction), “and the plurality of stacked structure being spaced apart from each other in a second direction parallel to the lower surface of the substrate” (Kraman Fig. 21A; note that the stacks are separated from each other by isolation pillars 73); “a separation structure extending between the plurality of stacked structures in a third direction intersecting the first direction and the second direction” (Kraman Figs. 21A and B; support pillars 20; note that the support pillars 20 and the isolation pillars 73 serve the same purpose, and thus the support pillars 20 will be treated as the separation structure; see [0164]), “the separation structure including a plurality of support patterns that are spaced apart from each other in the third direction in the separation structure” (Kraman Figs. 21A and B, isolation pillars 73; note that the isolation pillars 73 are spaced apart in the third direction’ note that the support pillars 20 and the isolation pillars 73 serve the same purpose, and thus the isolation pillars 73 will be treated as the support patterns; see [0164]); but does not teach “a plurality of peripheral circuit structures on a substrate”, “(a plurality of stacked structures) on the plurality of peripheral circuit structure”, and “wherein the plurality of support patterns are spaced apart from the plurality of gate electrodes.”
Lee, on the other hand, teaches “a plurality of peripheral circuit structures on a substrate” (Lee [0047]; Fig. 6, peripheral circuit structure PS), and “(a plurality of stacked structures) on the plurality of peripheral circuit structure” (Lee [0053]; Fig. 6, cell array structure CS). Furthermore, Lee teaches support structures (Lee [0105]; Fig. 6, second support structure WC2) consisting of spacers (Lee [0105]; Fig. 6, second spacer part SP2) surrounding a filler layer (Lee [0105]; Fig. 6, second filler part FL2) and that the spacer parts are formed using atomic layer deposition (ALD) and the filler parts by chemical vapor deposition (CVD) (Lee [0095]).
The peripheral circuit structure of Lee can be incorporated into the device of Kraman as a similar peripheral circuit structure disposed beneath the stacked structures. Furthermore, the internal insulating layer of Lee can be incorporated into the device of Kraman as an internal insulating layer surrounding the support patterns. The combined device teaches “wherein the plurality of support patterns are spaced apart from the plurality of gate electrodes” (Lee Fig. 6; note that the second spacer part SP2 serves to separate the second filler part FL2 from the gate electrodes ELa and ELb).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have incorporated a peripheral circuit structure as taught by Lee into the device of Kraman because doing so would provide the necessary hardware to read from and write to the memory device, and it would be a simple combination of elements of the two disclosures. Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have included a spacer layer surrounding the support patterns because the spacer would protect the gate electrodes from reacting with the vapor used in forming the filler during the CVD process and it would be a simple combination of elements of the two disclosures.
Regarding claim 12, the combined device of Kraman and Lee described in the discussion of claim 11 further teaches “The three-dimensional memory device of claim 11, wherein each of the plurality of stacked structures further includes a plurality of interlayer insulating layers alternately stacked with the plurality of gate electrodes in the first direction” (Kraman [0074]; Fig. 21A, insulating layers 32), “and wherein the plurality of support patterns are in contact with the plurality of interlayer insulating layers” (Kraman Fig. 21A, note that the isolation pillars 73 contact the insulating layers 32).
Regarding claim 13, the combined device of Kraman and Lee described in the discussion of claim 11 further teaches “The three-dimensional memory device of claim 11, further comprising an internal insulating layer between the plurality of support patterns and the plurality of gate electrodes” (Lee Fig. 6; note that the second spacer part SP2 surrounds the second filler part FL2, and thus serves to separate the second filler part FL2 from the gate electrodes ELa and ELb).
Regarding claim 14, the combined device of Kraman and Lee as applied to claim 11 teaches “The three-dimensional memory device of claim 13”, but does not teach “wherein the plurality of internal insulating layers includes metal oxide.”
Kraman, on the other hand, teaches the existence of metal oxides with high dielectric constants (high-k dielectrics) (Kraman [0070]).
The teaching of high-k dielectric metal oxides of Kraman can be incorporated into the combined device of Kraman and Lee described in the discussion of claim 11 through the use of such a material for the second spacer part of Lee. The combined device teaches “wherein the plurality of internal insulating layers includes metal oxide” (Lee [0105]; Fig. 6, second spacer part SP2, which is made of a metal oxide in the combined device; see Kraman [0070]).
It would have been obvious to one of ordinary skill in the art to have used a high-k metal oxide as the second spacer layer in the combined device of Kraman and Lee described in the discussion of claim 11 because it would provide better shielding against stray electric fields from a neighboring device region and it would be a simple substitution of one element for another.
Regarding claim 15, the combined device of Shin, Kraman, and Lee described in the discussion of claim 11 further teaches “The three-dimensional memory device of claim 11, wherein the separation structure further includes a plurality of separation patterns” (Kraman Fig. 21B; note that there is a plurality of support pillars 20 in each row extending along the third direction) “alternately arranged with the plurality of support patterns in the third direction” (Kraman Fig. 21B; note that the support pillars 20 within a row extending along the third direction alternate with isolation pillars 73).
Regarding claim 16, Kraman teaches “An electronic system comprising: three-dimensional semiconductor memory device” (Kraman [0001]) “wherein the three-dimensional semiconductor memory device includes: …a plurality of stacked structures” (Kraman Fig. 21A, reproduced above with annotations added by the examiner), “each the plurality of stacked structures including a plurality of gate electrodes” (Kraman [0152]; Fig. 21A, electrically conductive layers 46) “stacked… in a first direction perpendicular to a lower surface of the substrate” (Kraman Fig. 21A; note that the electrically conductive layers 46 and the insulating layers 32 are stacked in the first direction), “and the plurality of stacked structure being spaced apart from each other in a second direction parallel to the lower surface of the substrate” (Kraman Fig. 21A; note that the stacks are separated from each other by isolation pillars 73); “a separation structure extending between the plurality of stacked structures in a third direction intersecting the first direction and the second direction” (Kraman Figs. 21A and B; support pillars 20; note that the support pillars 20 and the isolation pillars 73 serve the same purpose, and thus the support pillars 20 will be treated as the separation structure; see [0164]), “the separation structure including a plurality of support patterns that are spaced apart from each other in the third direction in the separation structure” (Kraman Figs. 21A and B, isolation pillars 73; note that the isolation pillars 73 are spaced apart in the third direction’ note that the support pillars 20 and the isolation pillars 73 serve the same purpose, and thus the isolation pillars 73 will be treated as the support patterns; see [0164]); but does not teach “a controller electrically connected to the three-dimensional semiconductor memory device through an input/output pad and configured to control the three-dimensional semiconductor memory device”, “a plurality of peripheral circuit structures on a substrate”, “(a plurality of stacked structures) on the plurality of peripheral circuit structure”, and “an internal insulating layer surrounding a side surface of each of the plurality of support patterns.”
Lee, on the other hand, does teach “a controller electrically connected to the three-dimensional semiconductor memory device” (Lee [0028] and [0031]; Figs. 1 and 2, controller 1220 and 2002) “through an input/output pad” (Lee [0027]; Fig. 1, input/output pad 1101) “and configured to control the three-dimensional semiconductor memory device” (Lee [0028]: “For example, the electronic system 1000 may include a plurality of three-dimensional semiconductor memory devices 1100, and in this case, the controller 1200 may control the plurality of three-dimensional semiconductor memory devices 1100.”), “a plurality of peripheral circuit structures on a substrate” (Lee [0047]; Fig. 6, peripheral circuit structure PS), “(a plurality of stacked structures) on the plurality of peripheral circuit structure” (Lee [0053]; Fig. 6, cell array structure CS), and “an internal insulating layer” (Lee [0105]; Fig. 6, second spacer part SP2, which is part of the second support structure WC2) “surrounding a side surface of each of the plurality of support patterns” (Lee [0105]: “The second filler part FL2 may fill a space surrounded by the second spacer part SP2.”; Fig. 6, second filler part FL2). Lee further teaches that the spacer parts are formed using atomic layer deposition (ALD) and the filler parts by chemical vapor deposition (CVD) (Lee [0095]).
The controller of Lee can be incorporated into the device of Kraman by electrically connecting the memory structure of Kraman to a controller. Furthermore, the peripheral circuit structure of Lee can be incorporated into the device of Kraman as a similar peripheral circuit structure disposed beneath the stacked structures. Furthermore, the internal insulating layer of Lee can be incorporated into the device of Kraman as an internal insulating layer surrounding the support patterns.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to connect the memory device of Kraman to a controller as taught by Lee because the controller would enable one to read data from and write data to the memory, and it would be a simple combination of elements of the two disclosures. Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have incorporated a peripheral circuit structure as taught by Lee into the device of Kraman because doing so would provide necessary hardware to read from and write to the memory device, and it would be a simple combination of elements of the two disclosures. Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have included a spacer layer surrounding the support patterns because the spacer would protect the gate electrodes from reacting with the vapor used in forming the filler during the CVD process and it would be a simple combination of elements of the two disclosures.
Regarding claim 17, the combined device of Kraman and Lee described in the discussion of claim 16 teaches “The electronic system of claim 16”, but does not teach “wherein the internal insulating layer includes metal oxide.”
Kraman, on the other hand, teaches the existence of metal oxides with high dielectric constants (high-k dielectrics) (Kraman [0070]).
The teaching of high-k dielectric metal oxides of Kraman can be incorporated into the combined device of Kraman and Lee described in the discussion of claim 16 through the use of such a material for the second spacer part of Lee. The combined device teaches “wherein the internal insulating layer includes metal oxide” (Lee [0105]; Fig. 6, second spacer part SP2, which is made of a metal oxide in the combined device; see Kraman [0070]).
It would have been obvious to one of ordinary skill in the art to have used a high-k metal oxide as the second spacer layer in the combined device of Kraman and Lee described in the discussion of claim 16 because it would provide better shielding against stray electric fields from a neighboring device region and it would be a simple substitution of one element for another.
Regarding claim 18, the combined device of Kraman and Lee described in the discussion of claim 16 further teaches “The electronic system of claim 16, wherein the plurality of support patterns are spaced apart from the plurality of gate electrodes” (Lee Fig. 6; the fact that the second spacer part SP2 is interposed between the second filler part FL2 and the gate electrodes ELa and ELb means that the second filler part FL2 is spaced apart from the gate electrodes).
Regarding claim 19, the combined device of Kraman and Lee described in the discussion of claim 16 further teaches “The electronic system of claim 16, wherein the separation structure further includes a plurality of separation patterns” (Kraman Fig. 21B; note that there is a plurality of support pillars 20 in each row extending along the third direction) “alternately arranged with the plurality of support patterns in the third direction” (Kraman Fig. 21B; note that the support pillars 20 within a row extending along the third direction alternate with isolation pillars 73).
Regarding claim 20, the combined device of Kraman and Lee described in the discussion of claim 16 anticipates “The electronic system of claim 16, wherein the separation structure includes a plurality of separation structures disposed in the second direction” (Kraman Fig. 21B; note that the rows of isolation pillars 73 and support pillars 20 are disposed along the second direction), “wherein each of the plurality of separation structures includes the plurality of support patterns” (Kraman Fig. 21B; note that the support pillars 20 alternate with the isolation pillars 73), “and wherein the plurality of support patterns are arranged in a zigzag shape or a row in the second direction” by teaching support pillars arranged in rows along the second direction (Kraman Fig. 21B; note that the isolation pillars 73 are arranged in rows along the second direction).
Conclusion
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/R.E.T./Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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