Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ge et al. (US 20140374812 A1).
Regarding claim 1, FIG. 1 and FIG. 3 of Ge et al. teach a memory device (20; FIG. 1; paragraph 0030), comprising:
a semiconductor substrate (22; FIG. 1; paragraph 0031) including an active region (24, 26; FIG. 1; paragraph 0031) and a field region (28; FIG. 1; paragraph 0031);
a floating gate (30; FIG. 1; paragraph 0031);
a control gate (32; FIG. 1; paragraph 0031) above the floating gate; and
a dielectric layer (34; FIG. 1; paragraph 0031) interposed between the control gate and the floating gate, wherein the control gate is made at least in part of a metallic material (108; FIG. 3; paragraph 0040).
Regarding claim 2, FIG. 4 of Ge et al. teaches the memory device of claim 1, comprising a non-volatile memory cell (122; FIG. 4; paragraph 0045) including a floating gate transistor (146; FIG. 4; paragraph 0046) and a selection transistor (136; FIG. 4; paragraph 0046) each positioned over the active region.
Regarding claim 12, FIG. 3 of Ge et al. teaches the memory device of claim 1, wherein the field region includes a P- well (98; FIG. 3; paragraph 0038), wherein the active region includes an N-Well (92, 94, 96; FIG. 3; paragraph 0038).
Regarding claim 18, FIG. 1 of Ge et al. teaches a memory device, comprising:
a semiconductor substrate (22; FIG. 1; paragraph 0031) including an active region (24, 26; FIG. 1; paragraph 0031) and a field region (28; FIG. 1; paragraph 0031);
a floating gate (30; FIG. 1; paragraph 0031) overlying the active region and the field region;
a control gate (32; FIG. 1; paragraph 0031) arranged above the floating gate; and
a dielectric layer (34; FIG. 1; paragraph 0031) interposed between the control gate and the floating gate wherein the control gate overlays the field region without overlapping the active region (FIG. 1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Ge et al. in view of Zuliani et al. (US 20040152267 A1).
Regarding claim 3, FIG. 3 and FIG. 4 of Ge et al. teach the memory device of claim 2, wherein:
the floating gate transistor includes the floating gate (146; FIG. 4; paragraph 0046);
the selection transistor includes a gate terminal (136; FIG. 4; paragraph 0046); and
wherein the dielectric layer (78; FIG. 3; paragraph 0041) includes an opening above the gate terminal.
Ge et al. does not teach the gate terminal being of a same material as the floating gate.
FIG. 3 of Zuliani et al. teaches the gate regions of floating gate transistors and selection transistors are formed of a first oxide layer (9; FIG. 3; paragraph 0054), a first polysilicon layer (11; FIG. 3; paragraph 0054), a second oxide layer (12; FIG. 3; paragraph 0054) and a second polysilicon layer (13; FIG. 3; paragraph 0054).
Ge et al. and Zuliani et al. are both analogous to the claimed invention in that they involve semiconductor memory devices with floating gates and control gates. Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to modify Ge et al. so that the gate terminal is of a same material as the floating gate. This is the result of them being formed in the same process (paragraph 0054).
Regarding claim 19, FIG. 1 of Ge et al. teaches the memory device of claim 18, comprising a non-volatile memory cell ((122; FIG. 4; paragraph 0045) including:
a floating gate transistor (146; FIG. 4; paragraph 0046) including the floating gate (146; FIG. 4; paragraph 0046); and
a selection transistor (136; FIG. 4; paragraph 0046) including a gate terminal (136; FIG. 4; paragraph 0046) positioned over the active region and the field region and including:
a gate contact (144a; FIG. 4; paragraph 0047) in direct contact with the gate terminal and overlays the field region (FIG. 4) without overlapping the active region (126, 128; FIG. 4; paragraph 0046).
Ge et al. does not teach the device wherein the gate terminal is of a same material as the floating gate.
FIG. 3 of Zuliani et al. teaches the gate regions of floating gate transistors and selection transistors are formed of a first oxide layer (9; FIG. 3; paragraph 0054), a first polysilicon layer (11; FIG. 3; paragraph 0054), a second oxide layer (12; FIG. 3; paragraph 0054) and a second polysilicon layer (13; FIG. 3; paragraph 0054).
Ge et al. and Zuliani et al. are both analogous to the claimed invention in that they involve semiconductor memory devices with floating gates and control gates. Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to modify Ge et al. so that the gate terminal is of a same material as the floating gate. This is the result of them being formed in the same process (paragraph 0054).
Claims 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Ge et al. in view of Zuliani et al. and further in view of Liang et al. (US 20210066326 A1) and Matsuno (US 20080246075 A1).
Regarding claim 4, the combination of Ge et al. in view of Zuliani et al. teaches the memory device of claim 3. Neither Ge et al. nor Zuliani et al. teach the device wherein the dielectric layer is a silicide protection dielectric layer including a plurality of sub-layers.
FIG. 10 of Liang et al. teaches a metal silicide layer (214; FIG. 10; paragraph 0053) attached to an isolation spacer layer made of dielectric materials (208; FIG. 10; paragraph 0059). Liang et al. does not teach the dielectric layer being composed of numerous sub-layers.
Matusno et al. teaches multiple dielectric layers (1, 12, 13, 14, 15; FIG. 3; paragraph 0038).
Ge et al., Zuliani et al., Liang et al., and Matsuno are all analogous to the claimed invention in that they involve semiconductor memory devices with floating gates and control gates. Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to modify Ge et al. so that the dielectric layer is a silicide protection dielectric layer including a plurality of sub-layers. It is known that these dielectric layers can be made covered with metal layers (Liang et al.: paragraph 0049), with the sub-layers known to cover these configurations (Matsuno: paragraph 0037).
Regarding claim 5, the combination of Ge et al. in view of Zuliani et al. and further in view of Liang et al. and Matsuno teaches the memory device of claim 4. Neither Ge et al. nor Zuliani et al. teach the device wherein the sub-layers include a first sub-layer of silicon oxide, a second sub-layer of tetraethyl orthosilicate on the first sub-layer, and a third sub-layer of silicon nitride on the second sub-layer.
FIG. 10 of Liang et al. teaches a dielectric isolation spacer layer (208; FIG. 10; paragraph 0058) that can be formed with layers including silicon oxide, tetraethyl orthosilicate, and silicon nitride (paragraph 0038). Liang et al. does not teach them being stacked on top of each other.
FIG. 3 of Matsuno teaches the silicon oxide (12; FIG. 3; paragraph 0038), tetraethyl orthosilicate (13; FIG. 3; paragraph 0038), and silicon nitride (14; FIG. 3; paragraph 0038) layers are stacked on top of each other.
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to modify Ge et al. to have a first sub-layer of silicon oxide, a second sub-layer of tetraethyl orthosilicate on the first sub-layer, and a third sub-layer of silicon nitride on the second sub-layer. These are known materials to make up dielectric material (Matsuno: paragraph 0038)
Claims 6, 7, and 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Ge et al. in view of Roohparvar (US 20060022254 A1).
Regarding claim 6, Ge et al. teaches the memory device of claim 2. Ge et al does not teach the device wherein the control gate includes:
a first control gate contact in contact with the dielectric layer over the floating gate and overlapping the field region on a first side of the active region; and
a second control gate contact in contact with the dielectric layer over the floating gate and overlapping the field region on a second side of the active region.
FIG. 4 of Roohparvar teaches two contacts (340; FIG. 4; paragraph 0034) touching both the control gate (314; FIG. 4; paragraph 0034) and dielectric layer (332; FIG. 4; paragraph 0034) over the floating gate (310; FIG. 4; paragraph 0034), with each contact on opposing sides of a pair of source/drain regions (330; FIG. 4; paragraph 0032).
Ge et al. and Roohparvar et al. are both analogous to the claimed invention in that they involve semiconductor memory devices with floating gates and control gates. Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to modify Ge et al. so the control gate includes two contacts in contact with the dielectric layer on opposing sides of an active region. This connection allows power to flow into the control gate (paragraph 0014).
Regarding claim 7, the combination of Ge et al. in view of Roohparvar et al. teaches the memory device of claim 6. Ge et al. does not teach the device wherein the first control gate contact and the second control gate contact do not overlap the active region.
FIG. 4 of Rohhparvar teaches the two contacts (340; FIG. 4; paragraph 0034) not overlapping the source/drain regions (330; FIG. 4; paragraph 0032).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to modify Ge et al. so that the first control gate contact and the second control gate contact do not overlap the active region. This is the result of the structure and placement of the active regions (paragraph 0032).
Regarding claim 13, Ge et al. teaches a memory device (20; FIG. 1; paragraph 0030), comprising:
a semiconductor substrate (22; FIG. 1; paragraph 0031) including an active region (24, 26; FIG. 1; paragraph 0031) and a field region (28; FIG. 1; paragraph 0031);
a floating gate (30; FIG. 1; paragraph 0031);
a control gate (32; FIG. 1; paragraph 0031) above the floating gate; and
a dielectric layer (34; FIG. 1; paragraph 0031) interposed between the control gate and the floating gate.
Ge et al. does not teach the device wherein the control gate includes a plurality of discrete elements.
FIG. 4 of Roohparvar teaches a control gate of polysilicon word lines (314; FIG. 4; paragraph 0030) touching two metal contacts (340; FIG. 4; paragraph 0037).
Ge et al. and Roohparvar et al. are both analogous to the claimed invention in that they involve semiconductor memory devices with floating gates and control gates. Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to modify Ge et al. so the control gate includes a plurality of discrete elements. This allows the structure to be properly conductive (paragraph 0030).
Regarding claim 14, the combination of Ge et al. in view of Roohparvar et al. teaches the memory device of claim 13. Ge et al. does not teach the device wherein the plurality of discrete elements includes a first control gate contact and a second control gate contact both in direct contact with the dielectric layer.
FIG. 4 of Roohparvar teaches two contacts (340; FIG. 4; paragraph 0034) touching both the control gate (314; FIG. 4; paragraph 0034) and dielectric layer (332; FIG. 4; paragraph 0034) over the floating gate (310; FIG. 4; paragraph 0034), with each contact on opposing sides of a pair of source/drain regions (330; FIG. 4; paragraph 0032).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to modify Ge et al. so the control gate includes two contacts in contact with the dielectric layer on opposing sides of an active region. This connection allows power to flow into the control gate (paragraph 0014).
Regarding claim 15, the combination of Ge et al. in view of Roohparvar et al. teaches the memory device of claim 14. Ge et al. does not teach the device wherein:
a first area of contact of the first control gate contact and the dielectric layer at least partially overlies the field region on a first side of the active region; and
a second area of contact of the second control gate contact and the dielectric layer at least partially overlies the field region on a second side of the active region opposite the first side.
FIG. 4 of Rohhparvar teaches the two contacts (340; FIG. 4; paragraph 0034) contacting the dielectric layer (332; FIG. 4; paragraph 0034) in an aera overlapping the non-source/drain parts of the substrate (303; FIG. 4; paragraph 0029) of opposing sides of a pair of source/drain regions (330; FIG. 4; paragraph 0032).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to modify Ge et al. so that where the first control gate contact and the second control gate contact make contact with the dielectric layer over the field region. This is the result of the structure and placement of the active regions (paragraph 0032).
Regarding claim 16, the combination of Ge et al. in view of Roohparvar et al. teaches the memory device of claim 14. Ge et al. does not teach the device wherein the first area of contact is laterally entirely outside the active region on the first side, wherein the second area of contact is laterally entirely outside the active region on second first side.
FIG. 4 of Rohhparvar teaches the two contacts (340; FIG. 4; paragraph 0034) not overlapping the source/drain regions (330; FIG. 4; paragraph 0032).
It would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to modify Ge et al. so that the first control gate contact and the second control gate contact do not overlap the active region. This is the result of the structure and placement of the active regions (paragraph 0032).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Ge et al. in view of Rhie (US 20140151774 A1).
Regarding claim 9, Ge et al. teaches the memory device of claim 2. Ge et al. does not teach the device comprising a field dielectric positioned on a first side of the active region and on a second side of the active region opposite the first side, wherein the metal field plate overlies the active region, the field dielectric on the first side of the active region, and the field dielectric on the second side of the active region.
FIG. 25 and FIG. 26 of Rhie teach field dielectrics (102; FIG. 25; paragraph 0136) around n-type conductive regions in the active regions (103; FIG. 25; paragraph 0134) overlayed by conducting layers (105a-105c; FIG. 26; paragraph 0136) made of metal (paragraph 0164).
Ge et al. and Rhieare both analogous to the claimed invention in that they are semiconductor devices with field and active regions. Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have modified Ge et al. to have a field dielectric positioned on a first side of the active region and on a second side of the active region opposite the first side and a metal plate overlying the three areas. This is the result of the patterning of the active and field regions (paragraph 0133).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Ge et al. in view of Rhie and further in view of Roohparvar.
Regarding claim 10, the combination of Ge et al. in view of Rhie teach the memory device of claim 9. Neither Ge et al. nor Rhie teach the device comprising dielectric sidewall spacers on sidewalls of the floating gate, wherein the dielectric layer is in direct contact with the dielectric sidewall spacers.
FIG. 4 of Roohparvar teaches dielectric spacers (324; FIG. 4; paragraph 0031) along the sides of a floating gate layer (310; FIG. 4; paragraph 0030) and directly contacting both an interlayer dielectric layer (312; FIG. 4; paragraph 0030) and a dielectric layer (332; FIG. 4; paragraph 0033).
Ge et al., Rhie, and Roohparvar are all analogous to the claimed invention in that they involve semiconductor devices with active regions and gates. Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to have modified Ge et al. to have dielectric sidewall spacers on sidewalls of the floating gate, wherein the dielectric layer is in direct contact with the dielectric sidewall spacers. These sidewalls are a known aspect of the structure (paragraph 0031).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Ge et al. in view of Georgescu et al. (US 20090003074 A1).
Regarding claim 11, Ge et al. teaches the memory device of claim 2. Ge et al. does not teach the device wherein the floating gate transistor and the selection transistor each have a respective gate dielectric of a same thickness and a same material.
FIG. 4 of Georgescu et al. teaches gate dielectrics (442, 443; FIG. 4; paragraph 0062) for access transistors (311, 313; FIG. 4; paragraph 0062) and gate dielectrics (441, 444; FIG. 4; paragraph 0062) for NVM transistors (321, 323; FIG. 4; paragraph 0062), which includes floating gates (421, 422; FIG. 4; paragraph 0044; paragraph 0047) made of the same material and thickness (FIG. 4; paragraph 0062).
Ge et al. and Georgescu et al. are both analogous to the claimed invention in that they involve semiconductor memory devices with floating gates and control gates. Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to modify Ge et al. so the floating gate transistor and the selection transistor each have a respective gate dielectric of a same thickness and a same material. This allows the transistors to respond to certain amount of voltage needed (paragraph 0062).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Ge et al. in view of Roohpavar et al. and further in view of Liang et al..
Regarding claim 17, the combination of Ge et al. in view of Roohparvar et al. teaches the memory device of claim 13. Neither Ge et al. nor Roohparvar et al. teach the device wherein the dielectric layer is a silicide protection layer including a plurality of sub-layers.
FIG. 10 of Liang et al. teaches a metal silicide layer (214; FIG. 10; paragraph 0053) attached to an isolation spacer layer made of dielectric materials (208; FIG. 10; paragraph 0059), which can be thought of as two layers.
Ge et al., Roohpavar et al., and Liang et al. are all analogous to the claimed invention in that they involve semiconductor memory devices with floating gates and control gates. Therefore, it would have been obvious for a person with ordinary skill in the art before the effective filing date of the claimed invention to modify Ge et al. so that the dielectric layer is a silicide protection dielectric layer including a plurality of sub-layers. It is known that these dielectric layers can be made covered with metal layers (paragraph 0049).
Allowable Subject Matter
Claims 8 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 8, the combination of Ge et al. in view of Roohparvar et al. teaches the memory device of claim 6. Ge et al. further teaches the device wherein the first control gate contact (108; FIG. 3; paragraph 0040) forms a first capacitor area with the floating gate (106; FIG. 3; paragraph 0040). Ge et al. does not teach the device wherein the second control gate contact forms a second capacitor area with the floating gate, wherein the first capacitor area is at least 10 times larger than the second capacitor area. None of the located prior art teaches this limitation. Therefore, it would be improper in hindsight to modify Ge et al. to have a second control gate contact form a second capacitor area with the floating gate, wherein the first capacitor area is at least 10 times larger than the second capacitor area. None of the located prior art teaches this limitation.
Regarding claim 20, the combination of Ge et al. in view of Zuliani et al. teaches the memory device of claim 19. Neither Ge et al. nor Zuliani et al. teach the device wherein the gate contact contacts the gate terminal through an opening in the dielectric layer. None of the located prior art teaches this limitation. Therefore, it would be improper in hindsight to modify Ge et al. to have the gate contact contacting the gate terminal through an opening in the dielectric layer.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chen et al. (US 20140361358 A1) concerns a nonvolatile memory structure with a floating gate transistor and select transistors. Yamazaki (US 20110101351 A1) concerns a semiconductor device that can function as a memory device, containing a control gate and a floating gate transistor.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A VLCEK whose telephone number is (571)272-9665. The examiner can normally be reached Mon-Fri, 9:00 AM -5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.A.V./Examiner, Art Unit 2817
/RATISHA MEHTA/Primary Examiner, Art Unit 2817
Prosecution Insights