DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
2. Claims 1-7, 13 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takiguchi et al. U.S. Patent Application Publication 2022/0199695 A1 (the ‘695 reference, of record).
The reference discloses in Figs. 3A, 11B, para [151] (paragraph(s) [0151] and other text a method of manufacturing a light-emitting diode device and a light-emitting diode device as claimed.
Referring to claim 1, the ‘695 reference discloses a method of manufacturing a light-emitting diode device, which method comprises:
fabricating a light-emitting diode structure (LED 11) comprising an inorganic semiconductor (GaN-based compound semiconductor, para [77]); and
fabricating an optic (micro-lens 72) over the light-emitting diode structure (11) by nano-imprint lithography (nanoimprinting, para [167]).
Referring to claim 2, the reference further discloses in para [151] and Fig. 3A that fabricating the light-emitting diode structure (11) comprises:
epitaxially growing (MOCVD deposition; see, for example, Mezouari et al. U.S. Patent Application Publication 20220199871, para [118] that MOCVD deposition is the same as epitaxially growing) a layer of a first semiconductor (n-type contact) over a substrate (manufacturing base);
epitaxially growing a layer of a second semiconductor (p-type contact) over the layer of the first semiconductor;
selectively etching the layers to form a mesa (para [151]: “etched into a desired shape”, see also Fig. 3A);
selectively etching the mesa to remove a portion of the second semiconductor (the p-type contact) along one edge of the mesa to form a stepped mesa having an exposed portion of the first semiconductor (the n-type contact); and
forming a first electrical contact (55) on the exposed portion of the first semiconductor, and forming a second electrical contact (56) on the second semiconductor;
wherein one of the first and second semiconductors is a p-type semiconductor, and one of the first and second semiconductors is an n-type semiconductor.
Referring to claim 3, the reference further discloses that the first semiconductor (the n-type contact) is an n-type semiconductor, and the second semiconductor (the p-type contact) is a p-type semiconductor (note that the contacts are formed from GaN-based compound semiconductor, para [77, 151] (paragraph(s) [0077], [0151])).
Referring to claim 4, the reference further discloses that fabricating the light-emitting diode structure (11) comprises fabricating the light-emitting diode structure on a substrate (manufacturing base) and subsequently removing the substrate (para [151], last sentence).
Referring to claim 5, the reference further discloses that the substrate (the manufacturing base) is removed by laser lift-off (para [151]).
Referring to claim 6, the reference further discloses patterning a surface (that of planarizing layer 72’, Fig. 11B, para [167]) of the light-emitting diode structure; wherein
the optic (72) is formed over the patterned surface.
Referring to claim 7, the reference further discloses that the surface is patterned by growing the light-emitting diode structure (11) on a substrate (including 72’, Figs. 3B through 11B) having a patterned surface.
Referring to claim 13 and using the same reference characters, interpretations, and citations as detailed above for claim 1 where applicable, the reference discloses a light-emitting diode device, comprising:
a light-emitting structure (11) comprising an inorganic semiconductor (GaN-based compound semiconductor); and
a(n) [nano-imprinted] optic (72) arranged over the light-emitting structure (11).
Note that the limitation “nano-imprinted” is taken to be a product-by-process limitation and considered non-limitation in a product claim (MPEP 2112.01 and MPEP 2113). In a product by process claim, it is the patentability of the claimed product, in this case an optic, and not of the recited process steps which must be established. Therefore, when the prior art discloses a product which reasonably appears to be identical with or only slightly different than the product claimed in a product by process claim, a rejection based on sections 102 or 103 is fair. The Patent Office is not equipped to manufacture products by a myriad of processes put before it and then obtain prior art product and make physical comparisons therewith.
Referring to claim 15, Fig. 3A depicts that the light-emitting structure (11) has a patterned surface.
3. Claims 1-3 and 13-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Koike et al. U.S. Patent Application Publication 2016/0056352 A1 (the ‘352 reference).
The reference discloses in Fig. 6, other figures and related text a method of manufacturing a light-emitting diode device and a light-emitting diode device as claimed.
Referring to claim 1, the ‘352 reference discloses a method of manufacturing a light-emitting diode device, which method comprises:
fabricating a light-emitting diode structure (comprising 32/40/50, Figs. 5, 6, para [122, 133, 136, 137]; 702/703/704, Fig. 25, para [316]) comprising an inorganic semiconductor (silicon or germanium, para [136]); and
fabricating an optic (concave/convex 503/504, Fig. 6, para [157]; concave/convex 705, Fig. 25, para [316], and note that 705, which is equivalent to 503/504, is part of optical substrate D, para [316], which is fabricated by nanoimprint lithography, para [395, 396]) over the light-emitting diode structure (32/40/50; 702/703/704) by nano-imprint lithography (nanoimprint lithography, para [395, 396]).
Referring to claim 13 and using the same reference characters, interpretations, and citations as detailed above for claim 1 where applicable, the reference discloses a light-emitting diode device, comprising:
a light-emitting structure (32/40/50, Figs. 5, 6; 702/703/704, Fig. 25) comprising an inorganic semiconductor (silicon or germanium); and
a(n) [nano-imprinted] optic (503/504; 705) arranged over the light-emitting structure.
In a manner similar to that detailed above for claim 13 in paragraph numbered 2. above, “nano-imprinted” is taken to be a product-by-process limitation and considered non-limitation in a product claim.
Referring to claim 2, the reference further discloses in Figs. 4, 5 that fabricating the light-emitting diode structure (32/40/50) comprises:
epitaxially growing (para [137]) a layer of a first semiconductor (n-type 32) over a substrate (10);
epitaxially growing (para [137]) a layer of a second semiconductor (p-type 50) over the layer of the first semiconductor (32);
(inherently) selectively etching the layers to form a mesa (that depicted in Fig. 4);
selectively etching the mesa to remove a portion of the second semiconductor (50) along one edge of the mesa to form a stepped mesa having an exposed portion of the first semiconductor (32); and
forming a first electrical contact (80, para [124]) on the exposed portion of the first semiconductor (32), and forming a second electrical contact (70, para [124]) on the second semiconductor;
wherein one of the first and second semiconductors is a p-type semiconductor, and one of the first and second semiconductors is an n-type semiconductor.
Referring to claim 3, the reference further discloses that the first semiconductor (the n-type semiconductor 32) is an n-type semiconductor, and the second semiconductor (the p-type semiconductor 50) is a p-type semiconductor.
Referring to claim 14, Fig. 6 depicts that exactly one side of the light-emitting structure (32/40/50) has a stepped profile.
Referring to claim 15, Fig. 6 depicts that the light-emitting structure (32/40/50) has a patterned surface.
Referring to claim 16, the reference further discloses a lens (convex 20a, Fig. 6, para [120]) [obtainable by thermal reflow lithography] arranged between the light emitting structure (32/40/50) and the [nanoimprinted] optic (503/504, Fig. 6).
In a manner similar to that detailed above for claim 13 in paragraph numbered 2. above, “obtainable by thermal reflow lithography” is taken to be a product-by-process limitation and considered non-limitation in a product claim.
4. Claims 1, 4-6, 13, 15-16 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. U.S. Patent Application Publication 2022/0271193 A1 (the ‘193 reference).
The reference discloses in Fig. 11 and related text a method of manufacturing a light-emitting diode device and a light-emitting diode device as claimed.
Referring to claim 1, the ‘193 reference discloses a method of manufacturing a light-emitting diode device, which method comprises:
fabricating a light-emitting diode structure (LED 21) comprising an inorganic semiconductor (a group III-nitride material, para [83]); and
fabricating an optic (lens interface layer 81, para [136]) over the light-emitting diode structure (21) by nano-imprint lithography (imprint lithography, para [103]).
Referring to claim 13 and using the same reference characters, interpretations, and citations as detailed above for claim 1 where applicable, the reference discloses a light-emitting diode device, comprising:
a light-emitting structure (21, Fig. 11) comprising an inorganic semiconductor (a group III-nitride); and
a(n) [nano-imprinted] optic (81) arranged over the light-emitting structure.
In a manner similar to that detailed above for claim 13 in paragraph numbered 2. above, “nano-imprinted” is taken to be a product-by-process limitation and considered non-limitation in a product claim.
Referring to claim 4, the reference further discloses that fabricating the light-emitting diode structure (21) comprises fabricating the light-emitting diode structure on a substrate (“a substrate”, para [83]) and subsequently removing the substrate (para [83]: “…followed by removal of the substrate to expose a light emitting surface”).
Referring to claim 6, the reference further discloses patterning a surface (that of 21) of the light-emitting diode structure (21); wherein
the optic (81) is formed over the patterned surface.
Referring to claim 15, Fig. 11 depicts that the light-emitting structure (21) has a patterned surface.
Referring to claim 16, the reference further discloses a lens (51, para [102]) [obtainable by thermal reflow lithography] arranged between the light emitting structure (20) and the [nanoimprinted] optic (81).
In a manner similar to that detailed above for claim 13 in paragraph numbered 2. above, “obtainable by thermal reflow lithography” is taken to be a product-by-process limitation and considered non-limitation in a product claim.
Referring to claim 18, the reference discloses an array comprising a plurality of light-emitting diode devices (21, 22, 23) as detailed above for claim 13, arranged on a backplane (a substrate, not shown, para [84]: “LEDs may be provided with transparent contacts, such that a light emitting surface 24 of a light generating layer 20 may be provided on an opposite side of the light emitting surface 24 to a substrate”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. §103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claim 19 is rejected under 35 U.S.C. §103 as being unpatentable over Kim et al. U.S. Patent Application Publication 2022/0271193 A1 (the ‘193 reference).
Referring to claim 19, although the reference does not specifically disclose a dimension as claimed, the claimed dimension (a pitch (of the array) of less than or equal to 50 μm) will not support the patentability of subject matter encompassed by the prior art (the ‘193 reference discloses a scheme to control a pitch of the array, para [95]: “each container volume may have a surface area such that a pixel pitch of the LED array does not become excessive”) unless there is evidence indicating such dimensions are critical. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation"; MPEP 2144.05.
6. Claims 8 and 17 are rejected under 35 U.S.C. §103 as being unpatentable over Kim et al. U.S. Patent Application Publication 2022/0271193 A1 (the ‘193 reference) in view of Ohtsu et al. U.S. Patent Application Publication 2003/0142409 or Song U.S. Patent Application Publication 2018/0190942.
Referring to claims 8 and 17, the ‘193 reference discloses an optic (lens 81) and a lens (51) as detailed above for claims 1 and 17, but does not disclose that the lenses comprise a composite material comprising a polymer material and inorganic nanoparticles and that the lenses comprise a material having a refractive index in the range 1.5 to 1.8.
Ohtsu, in disclosing a micro-lens array comprising lenses, discloses that the lenses comprise a composite material comprising a polymer material (para [62]) and inorganic nanoparticles (para [63]) and that the lenses comprise a material having a refractive index in the range 1.4 to 1.6 (para [62]), which overlaps the claim range 1.5 to 1.8; or, Song, in disclosing a display device having an optical lens structure 21, discloses that the lens comprise a composite material comprising a polymer material (para [87]) and inorganic nanoparticles (para [86, 87]) and that the lenses comprise a material having a refractive index in the range of 1.6 or more (para [62]), which overlaps the claim range 1.5 to 1.8
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the reference’s lenses (81, 51) utilizing a polymer material and inorganic nanoparticles dispersed therein. One would have been motivated to make such a modification in view of the teachings in Ohtsu or Song that a polymer material and inorganic nanoparticles dispersed therein is material suitable for forming a lens, and such a material possesses a reflective index in the range 1.4 to 1.6 or more, overlapping and meeting the claim range of 1.5 to 1.8.
7. Claim 20 is rejected under 35 U.S.C. §103 as being unpatentable over Kim et al. U.S. Patent Application Publication 2022/0271193 A1 (the ‘193 reference) in view of Kessler et al. U.S. Patent 11,640,064 B2.
Referring to claim 20, the ‘193 reference discloses an optical array as detailed above for claim 18, and further discloses that the optical array is used in a display device (para [02]), but does not disclose an optical relay arranged over the array, the optical relay comprising a first lens, a turning prism arranged downstream of the first lens on an optical path, and a second lens arranged downstream of the turning prism on the optical path.
Kessler, in disclosing an optical array (image generator 10, Fig. 6B), teaches in Fig. 6B, claim 18 and col. 6, lines 18-40 using the optical array (10) in a display apparatus wherein the display apparatus comprises the array (10), and an optical relay (40) arranged over the array, the optical relay comprising a first lens (L3), a turning prism (20) arranged downstream of the first lens on an optical path, and a second lens (L5) arranged downstream of the turning prism on the optical path.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the reference’s optical array with an optical relay arranged over the array. One would have been motivated to make such a modification in view of the teachings in Kessler to form a working display apparatus.
Allowable Subject Matter
8. Claims 9-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to teach or render obvious a method of manufacturing a light-emitting diode device with all limitations as recited in claim 9, which may be characterized in, after fabricating the light-emitting diode structure and before fabricating the optic, forming a first lens on the light-emitting diode structure using thermal reflow lithography.
Conclusion
9. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TU TU V HO whose telephone number is (571)272-1778. The examiner can normally be reached on Monday to Thursday 6:30 - 15:00, Monday through Thursday.
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06-18-2026
/TU-TU V HO/Primary Examiner, Art Unit 2818
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