Prosecution Insights
Last updated: October 26, 2026
Application No. 18/661,342

SYSTEM AND METHOD FOR SOURCE SYNCHRONOUS IMPLEMENTATION

Non-Final OA §101
Filed
May 10, 2024
Examiner
MEMULA, SURESH
Art Unit
2851
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Microsoft Technology Licensing, LLC
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
825 granted / 942 resolved
+19.6% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
16 currently pending
Career history
963
Total Applications
across all art units

Statute-Specific Performance

§101
16.5%
-23.5% vs TC avg
§103
18.9%
-21.1% vs TC avg
§102
44.5%
+4.5% vs TC avg
§112
16.0%
-24.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 942 resolved cases

Office Action

§101
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections In claim 6, at line 1: after “generating” insert “a” to correct a typographical error. In claim 12, at line 2: change “data propagation signal paths” to “data signal propagation paths” to recite consistent terminology. Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 15-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to nonstatutory subject matter. Functional descriptive material, such as computer programs or data structures, are nonstatutory, per se, because they are not physical “things” and they are not capable of causing functional change in the computer. To qualify as statutory (MPEP §2106.01), the claimed functional descriptive material: (1) Must be directed to functional descriptive material. In other words, the functional descriptive material must impart functionality when employed as a computer component by a computer system, and cannot be directed to nonfunctional descriptive material, such as but not limited to music, computer listings, and a compilation or mere arrangement of data; and (2) Must be embodied on a non-transitory computer-readable storage medium (also called machine readable medium and other such variations), so as to define a structural and functional interrelationship between the functional descriptive material and a computer system which permits the functional descriptive material’s function to be realized. Moreover, the claims may only be directed to non-transitory storage medium, and the storage medium may not be directed to nonstatutory transitory embodiments such as signal waves, transmission media and the like. See: In re Nuijten, 500 F.3d 1346, 1356-57 (Fed. Cir. 2007). Claims 15-20 fail to comply with (2) above because neither the Specification nor the claims themselves necessarily limit “computer readable medium” to only non-transitory embodiments. Furthermore, the ¶ 0047 of the Specification expressly permits propagating mediums, propagating signals, and carrier waves. Allowable Subject Matter Claims 1-7 and 8-14 are allowable. Claims 15-20 would be allowed if amended to overcome the § 101 rejections set forth above. Claims 1-7, 8-14, and 15-20 would be allowable if amended to overcome any applicable objection or § 101 rejection because the prior art of record does not teach or suggest a method, system, or computer product having all the combinations of steps or elements as recited in independent claims 1, 8, or 15, particularly including, among other things, the following: In claim 1, generating a plurality of candidate signal propagation paths through the integrated circuit by determining a ratio of metal layer portions from a combination of discrete metal layer portions from the plurality of metal layers of the plurality of signal propagation tracks; dividing the plurality of candidate signal propagation paths into a plurality of candidate signal propagation path groups; generating a first set of signal propagation paths from the plurality of candidate signal propagation paths from a first candidate signal propagation path group; and generating a second set of signal propagation paths from the plurality of candidate signal propagation paths from a second candidate signal propagation path group, wherein the second set of signal propagation paths are variably offset from the first set of signal propagation paths. In claim 8, generating a plurality of candidate signal propagation paths through the integrated circuit by skipping every other signal propagation track for each metal layer and by determining a ratio of metal layer portions from a combination of discrete metal layer portions from the plurality of metal layers of the plurality of signal propagation tracks; dividing the plurality of candidate signal propagation paths into a plurality of candidate signal propagation path groups; generating a first set of signal propagation paths from the plurality of candidate signal propagation paths from a first candidate signal propagation path group; and generating a second set of signal propagation paths from the plurality of candidate signal propagation paths from a second candidate signal propagation path group, wherein the second set of signal propagation paths are 50% offset from the first set of signal propagation paths. In claim 15, generating a plurality of candidate signal propagation paths through the integrated circuit by skipping every other signal propagation track for each metal layer and by determining a ratio of metal layer portions from a combination of discrete metal layer portions from the plurality of metal layers; dividing the plurality of candidate signal propagation paths into a plurality of candidate signal propagation path groups; generating a first set of signal propagation paths from the plurality of candidate signal propagation paths from a first candidate signal propagation path group; and generating a second set of signal propagation paths from the plurality of candidate signal propagation paths from a second candidate signal propagation path group, wherein the second set of signal propagation paths are 50% offset from the first set of signal propagation paths, wherein the first set of signal propagation paths and the second set of signal propagation paths transmit data signals and clock signals source synchronously. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Examiner SURESH MEMULA whose telephone number is (571)272-8046, and any inquiry for a formal Applicant initiated interview must be requested via a PTOL-413A form and faxed to the Examiner's personal fax phone number: (571) 273-8046. Furthermore, Applicant is invited to contact the Examiner via email (suresh.memula@uspto.gov) on the condition the communication is pursuant to and in accordance with MPEP §502.03 and §713.01. The Examiner can normally be reached Monday-Thursday: 9am-6pm. If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Jack Chiang, can be reached on 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned (i.e., central fax phone number) is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SURESH MEMULA/Primary Examiner, Art Unit 2851
Read full office action

Prosecution Timeline

May 10, 2024
Application Filed
Oct 16, 2026
Non-Final Rejection mailed — §101 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
88%
With Interview (+0.0%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 942 resolved cases by this examiner. Grant probability derived from career allowance rate.

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