DETAILED ACTION
Claims 1-20 are pending for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim under US PRO 63/516949 filed on 8/1/2023.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 and 14-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sharifi et al, US 2022/0414646 A1 (Sharifi).
Regarding Claim 1, Sharifi discloses a physical unclonable function (PUF) circuit, comprising:
one or more micro-electromechanical systems (MEMS) structures configured to provide an output, wherein the output includes active oscillations, charge, resistance, inductance, and/or capacitance values (Sharifi [0040] – multiple PUF values may be generated from multiple physical structures, and may be combined to make a key or otherwise used to generate key and other cryptographic values; PUFs may be based on a variety of physical parameters such as … physical responses of electromechanical systems (e.g., microelectromechanical circuits), and other electrical or mechanical systems resident on the devices); and
active transistor PUF circuitry communicatively coupled to the one or more MEMS structures (Sharifi [0111] – An exemplary embodiment of an arbiter-based PUF is depicted in FIG. 5c);
wherein the active transistor PUF circuitry is configured to receive a challenge input and generate a PUF response in response to the challenge input, wherein the PUF response is generated based on the output provided by the one or more MEMS structures and manufacturing variation in components of the active transistor PUF circuitry (Sharifi [0040] – multiple PUF values may be generated from multiple physical structures, and may be combined to make a key or otherwise used to generate key and other cryptographic values; PUFs may be based on a variety of physical parameters such as … physical responses of electromechanical systems (e.g., microelectromechanical circuits), and other electrical or mechanical systems resident on the devices; [0111] – An exemplary embodiment of an arbiter-based PUF is depicted in FIG. 5c) ;
wherein the PUF response generated by the active transistor PUF circuitry is an output of the PUF circuit (Sharifi [0158] – the processing circuitry 1510 may form a combined value where a portion (e.g., half) of the combined value is from the programmable PUF source 1515 and another portion (e.g., half) of the combined value is from the non-programmable PUF source 1520).
Regarding Claim 2, Sharifi discloses the PUF circuit of claim 1, wherein one or more MEMS structures and/or the active transistor PUF circuitry is used exclusively for the PUF circuit (Sharifi see [0040] for MEMS).
Regarding Claim 3, Sharifi discloses the PUF circuit of claim 1, wherein the one or more MEMS structures include only a single MEMS structure (Sharifi see [0040] for MEMS).
Regarding Claim 4, Sharifi discloses the PUF circuit of claim 1, wherein the one or more MEMS structures include a plurality of MEMS structures (Sharifi see [0040] for MEMS).
Regarding Claim 14, Sharifi discloses a device, comprising: a physical unclonable function (PUF) circuit including:
one or more micro-electromechanical systems (MEMS) structures configured to provide active oscillations, charge, resistance, inductance, and/or capacitance values (Sharifi [0040] – multiple PUF values may be generated from multiple physical structures, and may be combined to make a key or otherwise used to generate key and other cryptographic values; PUFs may be based on a variety of physical parameters such as … physical responses of electromechanical systems (e.g., microelectromechanical circuits), and other electrical or mechanical systems resident on the devices); and
active transistor PUF circuitry communicatively coupled to the one or more MEMS structures, wherein the active transistor PUF circuitry is configured to receive a challenge input and output a PUF response in response to the challenge input (Sharifi [0040] – multiple PUF values may be generated from multiple physical structures, and may be combined to make a key or otherwise used to generate key and other cryptographic values; PUFs may be based on a variety of physical parameters such as … physical responses of electromechanical systems (e.g., microelectromechanical circuits), and other electrical or mechanical systems resident on the devices; [0111] – An exemplary embodiment of an arbiter-based PUF is depicted in FIG. 5c),
wherein the PUF response output by the active transistor PUF circuitry is generated based on the active oscillations, charge, resistance, inductance, and/or capacitance values output by the one or more MEMS structures and manufacturing variation in components of the active transistor PUF circuitry (Sharifi [0111] – An exemplary embodiment of an arbiter-based PUF is depicted in FIG. 5c); and
one or more additional circuits configured to generate the challenge input and/or utilize the PUF response for one or more cryptographic processes (Sharifi [0040] – multiple PUF values may be generated from multiple physical structures, and may be combined to make a key or otherwise used to generate key and other cryptographic values).
Regarding Claim 15, Sharifi discloses the device of claim 14, wherein the one or more MEMS structures include a plurality of MEMS structures (Sharifi see [0040] for MEMS).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is rejected under 35 U.S.C. 103 as being unpatentable over Sharifi, in view of Shin et al, US 2022/0045873 A1 (Shin).
Regarding Claim 5, Sharifi discloses the PUF circuit of claim 4, as outlined above.
However, Sharifi does not explicitly disclose the PUF circuit further comprises a respective signal conditioning circuit coupled between each respective MEMS structure of the plurality of MEMS structures and the active transistor PUF circuitry.
Shin teaches the PUF circuit further comprises a respective signal conditioning circuit coupled between each respective MEMS structure of the plurality of MEMS structures and the active transistor PUF circuitry (Shin [0053] – The first PUF cell PC11 may include a first transistor MN11 and a first switch SW11. The first transistor MN11 may function as a diode-connected between the first switch SW11 and a specific voltage; [0054] – The second PUF cell PC12 may include a second transistor MN12 and a second switch SW12. The second transistor MN12 may function as a diode-connected between the second switch SW12 and the specific voltage).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Sharifi to have a respective signal conditioning circuit, as taught by Shin. One would be motivated as circuit would be able to modify characteristics of an input between the MEMS structures.
Claim(s) 6, 7, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Sharifi, in view of Mathew et al, US 2015/0178143 A1 (Mathew).
Regarding Claim 6, Sharifi discloses the PUF circuit of claim 1, as outlined above.
However, Sharifi does not explicitly disclose the PUF circuit is configured to implement an arbiter PUF topology.
Mathew teaches the PUF circuit is configured to implement an arbiter PUF topology (Mathew [0037] – a processor includes a processor core and a secure key manager component that is coupled to the processor core. The secure key manager includes the PUF component and a dark-bit masking circuit coupled to the PUF component… an arbiter PUF can be used. An arbiter PUF may include a number of four-terminal switching elements connected in series. These pass a signal through or switch it to the other output terminal based on a configuration bit. The challenge consists of a vector of configuration bits which are applied to the switch elements, resulting in a challenge space which is exponential in the number of challenge bits. A race condition is set up in the circuit by injecting a rising edge, and the faster propagation path determined by a terminating arbiter).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Sharifi to implement an arbiter PUF topology, as taught by Mathew. One would be motivated as the structure would provide a cascade effect.
Regarding Claim 7, Sharifi discloses the PUF circuit of claim 1, as outlined above.
However, Sharifi does not explicitly disclose the active transistor PUF circuitry includes an array of ring oscillator loops that each include a same number of inverter components.
Mathew teaches the active transistor PUF circuitry includes an array of ring oscillator loops that each include a same number of inverter components (Mathew [0037] – a ring oscillator PUF can be used. The ring oscillator is a self-oscillating delay loop commonly constructed from inverters. In the ring oscillator PUF, the frequencies of logically identical ring oscillators are compared to produce a single response bit. The operating frequency of the ring oscillators will be influenced by manufacturing variation and the frequency difference between two oscillators can be measured using a counter. A single response bit can thus be generated for a pair of oscillators. The ring oscillator PUF can be viewed as having a single challenge).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Sharifi to include an active transistor PUF circuitry, as taught by Mathew. One would be motivated as the active transistor regulates the usage of the circuitry.
Regarding Claim 16, Sharifi discloses the device of claim 14, as outlined above.
However, Sharifi does not explicitly disclose the PUF circuit is configured to implement a ring oscillator PUF topology, wherein the active transistor PUF circuitry includes a plurality of ring oscillators communicatively coupled to one or more MEMS structures.
Mathew teaches the PUF circuit is configured to implement a ring oscillator PUF topology, wherein the active transistor PUF circuitry includes a plurality of ring oscillators communicatively coupled to one or more MEMS structures (Mathew [0037] – a ring oscillator PUF can be used. The ring oscillator is a self-oscillating delay loop commonly constructed from inverters. In the ring oscillator PUF, the frequencies of logically identical ring oscillators are compared to produce a single response bit. The operating frequency of the ring oscillators will be influenced by manufacturing variation and the frequency difference between two oscillators can be measured using a counter. A single response bit can thus be generated for a pair of oscillators. The ring oscillator PUF can be viewed as having a single challenge).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Sharifi to implement a ring oscillator PUF topology, as taught by Mathew. One would be motivated as the circuit can use input data to create provide different outputs.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharifi and Mathew, in view of Shin.
Regarding Claim 17, Sharifi and Mathew teach the device of claim 16, as outlined above.
However, Sharifi does not explicitly disclose the PUF circuit further includes a respective signal conditioning circuit coupled between each respective MEMS structure of the one or more MEMS structures and the active transistor PUF circuitry.
Shin teaches the PUF circuit further includes a respective signal conditioning circuit coupled between each respective MEMS structure of the one or more MEMS structures and the active transistor PUF circuitry (Shin [0053] – The first PUF cell PC11 may include a first transistor MN11 and a first switch SW11. The first transistor MN11 may function as a diode-connected between the first switch SW11 and a specific voltage; [0054] – The second PUF cell PC12 may include a second transistor MN12 and a second switch SW12. The second transistor MN12 may function as a diode-connected between the second switch SW12 and the specific voltage).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Sharifi to include a PUF circuit which further includes a respective signal conditioning circuit, as taught by Shin. One would be motivated as the transistor switches between the cells.
Claim(s) 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Sharifi, in view of Li et al, US 2019/0305971 A1 (Li).
Regarding Claim 19, Sharifi discloses a method, comprising: receiving, with active transistor physical unclonable function (PUF) circuitry of a PUF circuit, a PUF challenge, wherein the PUF circuit further includes one or more MEMS structures communicatively coupled to the active transistor PUF circuitry; in response to the PUF challenge, generating a PUF response to the PUF challenge, based on active oscillations, charge, resistance, inductance, and/or capacitance values output by the one or more MEMS structures and manufacturing variation in components of the active transistor PUF circuitry; and outputting the PUF response to an additional circuit.
However, Sharifi does not explicitly disclose a PUF challenge.
Li teaches a PUF challenge (Li [0050] – Data output 640(0-N) in the form of a product identifier (or an identification or authorization process using PUF challenges and responses))
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Sharifi to include a PUF challenge, as taught by Li. One would be motivated as the PUF challenge adds the element of responses for an identifier.
Regarding Claim 20, Sharifi, in combination, further discloses the method of claim 19, further comprising using the PUF response for one or more cryptographic processes (Sharifi [0040] – multiple PUF values may be generated from multiple physical structures, and may be combined to make a key or otherwise used to generate key and other cryptographic values.
Allowable Subject Matter
Claims 8-13 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMIR SHAHNAMI whose telephone number is (571)270-0707. The examiner can normally be reached Monday - Friday 8:00 am to 4:00 pm.
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/AMIR SHAHNAMI/ Primary Examiner, Art Unit 2483
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