Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species V (Fig. 18, claims 1-5, 9-16, and 18-20) in the reply filed on June 15, 2026, is acknowledged.
Claims 6-8 and 17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on June 15, 2026.
Claim Objections
Claim 13 is objected to because of the following informalities: there should be “and” before “the one side of the second wireless communication element”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 12 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 recites the limitation, “the one side of the second wireless communication element and one side of the logic chip have a step difference from each other”. Claim 9, which claim 12 is dependent on, recites the limitation, “wherein the semiconductor package further includes an adhesive layer disposed between a portion of the logic chip and a portion of the second wireless communication element”. It is unclear how there can be a step difference between the second wireless communication element and the logic chip when there is an adhesive layer interposed between the two.
It will be assumed for examination purposes that the step difference instead exists between the adhesive layer and the second wireless communication element.
This rejection may be overcome by amending claim 12 to instead recite a step difference between the adhesive layer and the second wireless communication element.
PNG
media_image1.png
662
910
media_image1.png
Greyscale
Fig. 7A of Farooq, reproduced with annotations added by the examiner.
PNG
media_image2.png
585
952
media_image2.png
Greyscale
Fig. 8 of Farooq, reproduced with annotations added by the examiner.
PNG
media_image3.png
883
947
media_image3.png
Greyscale
Fig. 1 of Chuang, reproduced with annotations added by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Farooq et. al., Pub. No. US 2022/0359482, hereafter referred to as Farooq, in view of Chuang et. al., Pub. No. US 2024/0057349, hereafter referred to as Chuang.
Regarding claim 1, Farooq teaches “A semiconductor package” (Farooq [0062]; Fig. 7A, reproduced above with annotations added by the examiner, semiconductor structure 700A) “comprising: a package substrate” (Farooq [0062]; Fig. 7A, packaging substrate 71); “a logic chip on the package substrate” (Farooq [0062]; Fig. 7A, logic chip 75); “a chip structure on the logic chip” (Farooq [0062]; Fig. 7A, note that the translator chip 80 and memory chip 85 are placed on top of the logic chip 75), “and including a buffer chip” (Farooq [0062]; Fig. 7A, translator chip 80) “containing a first through-electrode” (Farooq [0062]; Fig. 7A, the through-silicon vias 83 disposed directly above the logic chip 75), “a second through-electrode” (Farooq [0062]; Fig. 7A, the through-silicon vias 83 not disposed directly above the logic chip 75), “a first connection circuit electrically connected to the first through-electrode” (Farooq [0062]; Fig. 7A, portion of backside 80B directly above the logic chip 75; also see [0042]: “Translator chip 10 includes… fanout wiring (not depicted) in backside 10B…” and [0029]: “Additionally, for brevity and maintaining a focus on distinctive features of elements of the present invention, description of previously discussed materials, processes, and structures may not be repeated with regard to subsequent Figures.”), “and a second connection circuit electrically connected to the second through-electrode” (Farooq [0062]; Fig. 7A, portion of backside 80B not directly above the logic chip 75; also see [0042] and [0029]), “a plurality of memory chips stacked on the buffer chip” (Farooq [0062]; Fig. 7A, memory chip 85; also see [0064]: “In other examples… more than two vertically aligned (not depicted) stacked memory chips can be joined to translator chip 80.”) “and electrically connected to the first and second through-electrodes” (Farooq [0062]; Fig. 7A, note that the memory chip 85 is connected to the through-silicon vias 83 through connections 86A); “and a plurality of conductive vertical structures between the chip structure and the package substrate” (Farooq [0062]; Fig. 7A, pillars 74; also see [0033]: “Power can be provided directly to logic chip 5, such as an accelerator chip from packaging substrate 1 through solder connections 2 and to memory chip 15 using pillars 4…” and [0029]).
Farooq, however, does not teach “(a package substrate) including a first wiring and a second wiring”, “(a logic chip) electrically connected to the first wiring of the package substrate”, “(a logic chip) including a first wireless communication element”, “a second wireless communication element within the buffer chip or between the buffer chip and the logic chip, electrically connected to the first connection circuit, and coupled to the first wireless communication element”, and “(a plurality of conductive vertical structures) electrically connecting the second connection circuit and the second wiring”. However, Farooq does teach that the conductive pillars are connected to the packaging substrate and serve to provide electrical power to the memory chip (Farooq [0062]; Fig. 7A, note that the pillars 74 are connected to the packaging substrate 71 through the solder connections 73; also see [0033]: “Power can be provided to memory chip 15 through translator chip 10 using pillars 4 surrounding the periphery of translator chip 10.” and [0029]) and that the logic chip and the buffer chip are connected through electrical wiring (Farooq [0062]; Fig. 7A, through-silicon vias 76, vias 77, and connections 81; also see [0063]: “Connections 81 joining backside 75B of logic chip 75 to backside 80B of translator chip 80… can be formed using known die to wafer chip joining processes… (e.g., copper to copper pad bonding, C4 joining, and hybrid copper bonding).”).
Chuang, on the other hand, teaches “(a package substrate) including a first wiring” (Chuang [0043] and [0055]; Fig. 1, reproduced above with annotations added by the examiner, package substrate 10 and lead lines 11, hereafter referred to as first wirings) “and a second wiring” (Chuang [0087]: “The third conductive bump 42 is further connected with the substrate connecting bump 12 through the lead line 11 in the first substrate 10, so that the second semiconductor die stack structure can exchange information with the external device through the substrate connecting bump 12.”; Fig. 1, lines connecting third conductive bumps 42 to the substrate connecting bump 12, hereafter referred to as second wirings), “(a logic chip) electrically connected to the first wiring of the package substrate” (Chuang [0061]: “In some embodiments, the first semiconductor die 20 includes a logic die and the second semiconductor die stack structure includes a DRAM die.”; Fig. 1, note that the first semiconductor die 20 is connected to the first wirings), “(a logic chip) including a first wireless communication element” (Chuang [0038]; Fig. 1, first wireless communication portion 22), and “a second wireless communication element… coupled to the first wireless communication element” (Chuang [0039]; Fig. 1, first semiconductor die 20, first wireless communication portion 22, first die stack structure 301, second wireless communication portion 33; also see [0035]: “…wireless communication is performed between the first semiconductor die and the first die stack structure through a first wireless communication portion and a second wireless communication portion…”). In addition, Chuang teaches that the second wiring is electrically connected to the memory dies (Chuang [0045]; Fig. 1, note that the second wirings are connected to the second semiconductor dies 31 through the signal line 41 in the second substrate 40) and that the second wireless communication element is placed within a semiconductor die directly above the logic chip (Chuang Fig. 1; note that the second wireless communication portion 33 is disposed within one of the second semiconductor dies 31; also see [0072]: “In some embodiments, the second wireless communication portion 33 includes a plurality of second sub-portions 331, …At least one second sub-portion 331… (is) included in each of second semiconductor dies 31 in the first die stack structure 301”).
The lead lines of Chuang can be incorporated into the device of Farooq as wiring in the packaging substrate, such that some of the wiring is connected to the logic chip (Chuang [0055]; Fig. 1, first wirings) and some is connected to the pillars (Chuang [0087]; Fig. 1, second wirings). In addition, the wireless communication elements of Chuang can be incorporated into the device of Farooq by introducing a wireless communication element inside the translator chip 80 as a substitute for the connections 81 between the translator chip 80 and logic chip 75 and electrically connected to the fanout wiring within the backside 80B and another wireless communication element within the logic chip 75 that is coupled to the element inside the translator chip. The combined device teaches “(a second wireless communication element) electrically connected to the first connection circuit” (Farooq [0062]; Fig. 7A, portion of backside 80B above the logic chip 75; Chuang [0038]; Fig. 1, second wireless communication portion 33) and “(a plurality of conductive vertical structures) electrically connecting the second connection circuit and the second wiring” (Farooq [0062]; Fig. 7A, note that the pillars 74 connect the packaging substrate 71 and the memory chip 85; Chuang [0087]; Fig. 1, second wirings).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to introduce two sets of wirings in the packaging substrate of Farooq as taught by Chuang, one connected to the logic chip and one connected to the pillars, because doing so allows for power delivery to the logic chip and memory chips, respectively, and it would be a simple combination of elements of the two disclosures. Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the application to introduce a wireless communication chip inside the translator chip of Farooq connected to the fanout wiring within the backside and a second wireless communication element within the logic chip, both as taught by Chuang, because the use of wireless communication would speed up data transfer between the two chips compared to traditional electrical coupling through wires, the fanout wiring providing the required power for the first wireless communication chip, and it would be a simple combination of elements of the two disclosures.
Regarding claim 2, the combination of Farooq and Chuang described in the discussion of claim 1 teaches “The semiconductor package of claim 1”, but does not teach “wherein in a top view, at least a portion of the first wireless communication element and at least a portion of the second wireless communication element are located within an area in which a portion of the chip structure and a portion of the logic chip overlap.”
Chuang, on the other hand, teaches two wireless communication portions that are positioned within regions where the first semiconductor die and a second semiconductor die overlap one another from a top view (Chuang Fig. 1; note that the first wireless communication portion 22 and the second wireless communication portion 33 are each positioned within the region where the first semiconductor die 20 and a second semiconductor die 31 overlap each other from a top view; also see [0073]: “Specifically, the first sub-portions in the first semiconductor die correspond to the second sub-portions in the first die stack structure one by one…”).
The placement of the wireless communication portions of Chuang can be incorporated into the combined device of Farooq and Chuang as described in the discussion of claim 1 by having the two wireless communication elements both be disposed within the areas of the logic chip and the translator chip where the two overlap from a top view. The combined device teaches “wherein in a top view, at least a portion of the first wireless communication element and at least a portion of the second wireless communication element are located within an area in which a portion of the chip structure and a portion of the logic chip overlap” (Chuang Fig. 1; note that the first wireless communication portion 22 and the second wireless communication portion 33 are each positioned within the region where the first semiconductor die 20 and a second semiconductor die 31 overlap each other from a top view; also see [0073]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have placed the wireless communication elements of the combined device of Farooq and Chuang described in the discussion of claim 1 in a region where the logic chip and translator chip overlap from a top view because doing so would reduce the distance between the two elements, allowing for better communication between them, and it would have been a simple combination of elements of the two disclosures.
Regarding claim 3, the combination of Farooq and Chuang described in the discussion of claim 1 further teaches “The semiconductor package of claim 1, wherein the buffer chip includes a first layer including the first and second through-electrodes” (Farooq [0062]; Fig. 7A, layer of the translation chip 80 containing the through-silicon vias 83), “and a second layer disposed below the first layer and including the first and second connection circuits” (Farooq [0062]; Fig. 7A, backside 80B; also see [0042] and [0029]).
Regarding claim 14, the combination of Farooq and Chuang described in the discussion of claim 1 teaches “The semiconductor package of claim 1”, but does not teach “further comprising an encapsulant covering at least portions of the logic chip, the chip structure, the conductive vertical structures, and the package substrate, respectively.”
Chuang, on the other hand, does teach “further comprising an encapsulant covering at least portions of the logic chip, the chip structure, the conductive vertical structures, and the package substrate, respectively” (Chuang [0092]; Fig. 1, package compound structure 80).
The encapsulant of Chuang can be incorporated into the combined device of Farooq and Chuang described in the discussion of claim 1 by enclosing the device in an encapsulant.
It would have been obvious to one of ordinary skill in the art to enclose the combined device of Farooq and Chuang described in the discussion of claim 1, as taught by Chuang, because the encapsulant would help protect the device from the outside environment and it would be a simple combination of elements of the two disclosures.
Regarding claim 15, Farooq teaches “A semiconductor package” (Farooq [0062]; Fig. 7A, semiconductor structure 700A) “comprising: a chip structure including a buffer chip” (Farooq [0062]; Fig. 7A, translator chip 80) “containing a first through-electrode” (Farooq [0062]; Fig. 7A, the through-silicon vias 83 not disposed above the logic chip 75), “a second through-electrode” (Farooq [0062]; Fig. 7A, the through-silicon vias 83 disposed above the logic chip 75), “first lower surface pads” (Farooq [0062]; Fig. 7A, connections 81), “and a first connection circuit electrically connecting the second through-electrode and the first lower surface pads” (Farooq [0062]; Fig. 7A, backside 80B; also see [0042] and [0029]), “and a plurality of memory chips stacked on the buffer chip” (Farooq [0062]; Fig. 7A, memory chip 85; also see [0064]) “and electrically connected to the first through-electrode and the second through-electrode” (Farooq [0062]; Fig. 7A, note that the memory chip 85 is connected to the through-silicon vias 83 through connections 86A); “a logic chip below the buffer chip to expose the first lower surface pads” (Farooq [0062]; Fig. 7A, note that the connections 81 are exposed by a gap between the logic chip 75 and the translator chip 80); and “a package substrate below the buffer chip and the logic chip” (Farooq [0062]; Fig. 7A, packaging substrate 71); “and a plurality of conductive vertical structures” (Farooq [0062]; Fig. 7A, pillars 74).
Farooq, however, does not teach “(a package substrate) including a first wiring electrically connected to the logic chip” “and a second wiring electrically connected to the buffer chip” “a first wireless communication element disposed within the chip structure or between the chip structure and the logic chip”, “and electrically connected to the first through-electrode”; “a second wireless communication element within the logic chip and coupled to the first wireless communication element”; “an encapsulant covering at least portions of the chip structure, the logic chip, and the package substrate respectively”; and “(a plurality of conductive vertical structures) extending within the encapsulant and electrically connecting the first lower surface pads and the second wiring.” Farooq does, however, teach that the conductive vertical structures (Farooq [0062]; Fig. 7A, pillars 74) are connected to the memory chips and to the packaging substrate (Farooq Fig. 7A; note that the pillars 74 are connected to the memory chips 85 and 90 and to the packaging substrate 71).
Chuang, on the other hand, teaches “(a package substrate) including a first wiring electrically connected to the logic chip” (Chuang [0055] and [0061]: “In some embodiments, the first semiconductor die 20 includes a logic die and the second semiconductor die stack structure includes a DRAM die.”; Fig. 1, note that the first semiconductor die 20 is connected to the first wirings), “a first wireless communication element disposed within the chip structure or between the chip structure and the logic chip” (Chuang [0039]; Fig. 1, note that the second wireless communication portion 33 is disposed within the first die stack structure 301) “a second wireless communication element within the logic chip” (Chuang [0038]; Fig. 1, note that the first wireless communication portion 22 is disposed within the first semiconductor die 20; also see [0061]) “and coupled to the first wireless communication element” (Chuang [0035]; Fig. 1, first semiconductor die 20, first wireless communication portion 22, first die stack structure 301, second wireless communication portion 33), and “an encapsulant covering at least portions of the chip structure, the logic chip, and the package substrate respectively” (Chuang [0092]; Fig. 1, note that the package compound structure 80 covers the first die stack structure 301, the first semiconductor die 20, and the first substrate 10). In addition, Chuang teaches a second wiring in the substrate that is electrically connected to the memory dies (Chuang [0045] and [0087]; Fig. 1, note that the second wirings are connected to the second semiconductor dies 31 through the signal line 41 in the second substrate 40).
The lead lines of Chuang can be incorporated into the device of Farooq as wiring in the packaging substrate, such that some of the wiring is connected to the logic chip (Chuang [0055]; Fig. 1, first wirings) and some is connected to the pillars (Chuang [0087]; Fig. 1, second wirings). In addition, the wireless communication elements of Chuang can be incorporated into the device of Farooq by introducing a wireless communication element inside the translator chip 80 as a substitute for the connections 81 between the translator chip 80 and logic chip 75 and electrically connected to the fanout wiring within the backside 80B and another wireless communication element within the logic chip 75 that is coupled to the element inside the translator chip. Furthermore, the package compound structure of Chuang can be incorporated into the device of Farooq as a similar compound enclosing the device. The combined device teaches “(a first wireless communication element) electrically connected to the first through-electrode” (Farooq [0062]; Fig. 7A, portion of backside 80B above the logic chip 75; Chuang [0039]; Fig. 1, second wireless communication portion 33) and “and a plurality of conductive vertical structures extending within the encapsulant and electrically connecting the first lower surface pads and the second wiring” (Farooq [0062]; Fig. 7A, note that the pillars 74 connect the packaging substrate 71 and the memory chip 85; Chuang [0087] and [0092]; Fig. 1, second wirings, package compound structure 80; note that the pillars 74 of Farooq would extend through the package compound structure 80 in the combined device).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to introduce two sets of wirings in the packaging substrate of Farooq as taught by Chuang, one connected to the logic chip and one connected to the pillars, because doing so allows for power delivery to the logic chip and memory chips, respectively, and it would be a simple combination of elements of the two disclosures. Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the application to introduce a wireless communication chip inside the translator chip of Farooq connected to the fanout wiring within the backside and a second wireless communication element within the logic chip, both as taught by Chuang, because the use of wireless communication would speed up data transfer between the two chips compared to traditional electrical coupling through wires, the fanout wiring providing the required power for the second wireless communication chip, and it would be a simple combination of elements of the two disclosures. Finally, it would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have enclosed the device of Farooq in an encapsulant as taught by Chuang because doing so would protect the device from the outside environment and it would be a simple combination of elements of the two disclosures.
PNG
media_image4.png
605
838
media_image4.png
Greyscale
Figs. 1A and 1B of Karhade, reproduced with annotations added by the examiner.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Farooq and Chuang in further view of Karhade et. al., Pub. No. US 2024/0063066, hereafter referred to as Karhade.
Regarding claim 4, the combination of Farooq and Chuang described in the discussion of claim 3 teaches “The semiconductor package of claim 3, wherein the first layer includes a semiconductor substrate surrounding the first and second through-electrodes and containing silicon” (Farooq [0062]; the fact that the elements 83 are referred to as “through-silicon vias”, or TSVs, implies that the first layer containing said through-silicon vias is made from silicon), but does not teach “and wherein the second layer includes an insulating layer surrounding the first and second connection circuits and including at least one of silicon oxide and silicon nitride.”
Karhade, on the other hand, teaches integrated circuit dies (Karhade [0075]; Fig. 1A, IC dies 104) with an interconnect layer (Karhade [0075]; Fig. 1A, interconnects 106) composed of both metallic bond pads (Karhade [0081]; Fig. 1B, bond pads 132 and 134; note that Fig. 1B is a cross section of the interconnects, per [0081]: “FIG. 1B is a schematic cross-sectional view of a detail of a particular one of interconnects 106 in microelectronic assembly 100.”) and an insulating layer (Karhade [0081]; Fig. 1B, dielectric material 107). Furthermore, Karhade teaches that the insulating layer can be made of silicon oxide or silicon nitride (Karhade [0081]: “Dielectric material 107 (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.) in base die 103 and layer 102 may bond with each other.”) and that the integrated circuit dies may be interposer dies (Karhade [0080]: “For example, one or more of IC dies 104 may be interposer dies (e.g., bridge dies)…”).
The use of silicon oxide or silicon nitride as the insulator in the interconnect layer of the dies of Karhade can be incorporated into the combined device of Farooq and Chuang described in the discussion of claim 3 by using silicon oxide or silicon nitride as an insulator in the backside 80B of Farooq. The combined device teaches “and wherein the second layer includes an insulating layer surrounding the first and second connection circuits and including at least one of silicon oxide and silicon nitride” (Farooq [0062]; Fig. 7A, backside 80B; Karhade [0081]; dielectric material 107; note that the backside 80B of Farooq includes silicon oxide or silicon nitride in the combined device).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to include an insulator in the backside of the combined device of Farooq and Chuang described in the discussion of claim 3 and to make the insulator out of silicon oxide or silicon nitride, both as taught by Karhade, because it would help to insulate the wires, preventing unwanted crosstalk between them, because silicon oxide or silicon nitride would be capable of serving the purpose of such an insulator, and it would be a simple combination of elements of the two disclosures.
PNG
media_image5.png
476
815
media_image5.png
Greyscale
Fig. 1A of Nakano, reproduced with annotations added by the examiner.
Claims 5 and 16 is rejected under 35 U.S.C. 103 as being unpatentable over Farooq and Chuang, in further view of Nakano, US Pat. No. 10,217,726, hereafter referred to as Nakano.
Regarding claim 5, the combination of Farooq and Chuang described in the discussion of claim 1 teaches “The semiconductor package of claim 1”, but does not teach “wherein the first wireless communication element includes a first conductive pattern, and wherein the second wireless communication element includes a second conductive pattern connected to the first conductive pattern through inductive coupling or capacitive coupling.”
Nakano, on the other hand, teaches a pair of semiconductor dies (Nakano col. 3, lines 1-3; Fig. 1A, first die 120a and second die 120b), each containing an inductive coil (Nakano col. 4, line 7-10; Fig. 1A, first inductors 125a and second inductors 125b) made from a conductive material (Nakano col. 6, lines 23-24: “The first and second inductors 125a-b are formed from a conductor (e.g., a conductive trace).”), with the inductive coils coupled to one another and exchanging signals wirelessly (Nakano col. 4, lines 26-30: “The first and second inductors 125a-b that are aligned are inductively coupled (shown schematically as 130) and able to wirelessly communicate data between one another, and thus between the first die 120a and the second die 120b.”).
The inductive coils of Nakano can be incorporated into the combined device of Farooq and Chuang described in the discussion of claim 1 through the use of inductive coils as the wireless communication elements. The combined device teaches “wherein the first wireless communication element includes a first conductive pattern” (Nakano col. 4, lines 7-8; Fig. 1A, first inductors 125a; also see col. 6, lines 23-24), “and wherein the second wireless communication element includes a second conductive pattern” (Nakano col. 4, lines 9-10; also see col. 6, lines 23-24) “connected to the first conductive pattern through inductive coupling or capacitive coupling” (Nakano col. 4, lines 26-30).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have used coupled inductive coils as the wireless communication elements in the combined device of Farooq and Chuang described in the discussion of claim 1 because the inductive coupling of the inductive coils render them capable of serving the purpose of wireless communication elements and it would be a simple substitution of one element for another.
Regarding claim 16, the combined device of Farooq and Chuang described in the discussion of claim 15 teaches “The semiconductor package of claim 15”, but does not teach “wherein the first wireless communication element includes a first conductive pattern, and wherein the second wireless communication element includes a second conductive pattern transmitting and receiving a signal with the first conductive pattern.”
Nakano, on the other hand, teaches a pair of semiconductor dies (Nakano col. 3, lines 1-3; Fig. 1A, first die 120a and second die 120b), each containing an inductive coil (Nakano col. 4, line 7-10; Fig. 1A, first inductors 125a and second inductors 125b) made from a conductive material (Nakano col. 6, lines 23-24: “The first and second inductors 125a-b are formed from a conductor (e.g., a conductive trace).”), with the inductive coils coupled to one another and exchanging signals wirelessly (Nakano col. 4, lines 26-30: “The first and second inductors 125a-b that are aligned are inductively coupled (shown schematically as 130) and able to wirelessly communicate data between one another, and thus between the first die 120a and the second die 120b.”).
The inductive coils of Nakano can be incorporated into the combined device of Farooq and Chuang described in the discussion of claim 1 through the use of inductive coils as the wireless communication elements. The combined device teaches “wherein the first wireless communication element includes a first conductive pattern” (Nakano col. 4, lines 7-8; Fig. 1A, first inductors 125a; also see col. 6, lines 23-24), “and wherein the second wireless communication element includes a second conductive pattern” (Nakano col. 4, lines 9-10; also see col. 6, lines 23-24) “transmitting and receiving a signal with the first conductive pattern” (Nakano col. 4, lines 26-30).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have used coupled inductive coils as the wireless communication elements in the combined device of Farooq and Chuang described in the discussion of claim 1 because the inductive coupling of the inductive coils render them capable of serving the purpose of wireless communication elements and it would be a simple substitution of one element for another.
PNG
media_image6.png
460
857
media_image6.png
Greyscale
Fig. 2 of Meyer, reproduced with annotations added by the examiner.
Claims 9, 11, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Farooq and Chuang, in further view of Nakano and Meyer et. al., Pub. No. US 2017/0180014, hereafter referred to as Meyer.
Regarding claim 9, the combination of Farooq and Chuang described in the discussion of claim 1 teaches “The semiconductor package of claim 1”, but does not teach “wherein the second wireless communication element is disposed between the buffer chip and the logic chip, and wherein the semiconductor package further includes an adhesive layer disposed between a portion of the logic chip and a portion of the second wireless communication element.”
Nakano, on the other hand, teaches an adhesive disposed between two semiconductor dies (Nakano col. 3, lines 55-57; Fig. 1A, second die-attach material 142; also see col. 3, lines 58-60: “The first and second die-attach materials 140, 142 can be, for example, adhesive films (e.g. die-attach films), epoxies, tapes, pastes, or other suitable materials.”).
The adhesive layer between the semiconductor dies of Nakano can be incorporated into the combined device of Farooq and Chuang as a similar adhesive layer between the logic chip and the translator chip. The combined device teaches “wherein the semiconductor package further includes an adhesive layer disposed between a portion of the logic chip and a portion of the second wireless communication element” (Farooq [0062]; Fig. 7A, logic chip 75 and translator chip 80; Chuang [0038]; Fig. 1, second wireless communication portion 33; Nakano col. 3, lines 55-57; Fig. 1A, second die-attach material 142; also see col. 3, lines 58-60; note that the second die-attach material 142 of Nakano is located between the logic chip 75 of Farooq and the second wireless communication portion 33 of Chuang in the combined device).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have introduced an adhesive between the logic chip and translator chip of the combined of Farooq and Chuang, as taught by Nakano, because doing so would help to secure the two elements in place and it would be a simple combination of elements of the two disclosures.
The combination of Farooq, Chuang, and Nakano just described, however, does not teach “wherein the second wireless communication element is disposed between the buffer chip and the logic chip”. The second wireless communication element of the combined device is instead located inside the buffer chip (Chuang [0039]; Fig. 1, second wireless communication portion 33).
Meyer, on the other hand, teaches pairs of inductive coils that are used to provide wireless coupling of semiconductor dies (Meyer [0013]: “The signal can be conducted through the trace 209 of the PCB 205 to another point. At the other point, the signal can be wirelessly transferred to the second integrated circuit package 202 using a pair of couplers 210. In certain examples, this wireless transfer of the signal can be achieved by the use of couplers 210, 211, 212, 213 that include coils or inductive lines.”; Fig. 2, couplers 210-213) and lie outside of said dies (Meyer Fig. 2; note that the couplers 210-213 lie outside the PCB 205 and the first and second integrated circuit packages 201 and 202).
The placement of the inductive coils of Meyer outside of their respective semiconductor dies can be incorporated into the combined device of Farooq, Chuang, and Nakano by placing the first wireless communication portion directly on the top of the logic chip and the second wireless communication portion directly on the bottom of the translator chip. The combined device teaches “wherein the second wireless communication element is disposed between the buffer chip and the logic chip” (Farooq [0062]; Fig. 7A, logic chip 75 and translator chip 80; Chuang [0039]; Fig. 1, second wireless communication portion 33; Meyer [0013] Fig. 2, coupler 210; note that the second wireless communication portion 33 of Chuang would be located between the logic chip 75 and translator chip 80 of Farooq in the combined device).
It would have been obvious to one of ordinary skill in the art to place the two wireless communication portions of the combined device of Farooq, Chuang, and Nakano directly on top of the logic chip and directly on the bottom of the translator chip as taught by Meyer because doing so would bring the two portions into closer proximity, enhancing their ability to communicate with one another, and it would be a simple combination of elements of the two disclosures.
Regarding claim 11, the combination of Farooq, Chuang, Nakano, and Meyer described in the discussion of claim 9 further teaches “The semiconductor package of claim 9, wherein an upper surface of the second wireless communication element and upper surfaces of the conductive vertical structures are on the same level” (Farooq [0062]; Fig. 7A, pillars 74; Chuang [0039]; Fig. 1, second wireless communication portion 33; Meyer [0013]; Fig. 2, coupler 210; note that, since the upper surfaces of the pillars 74 of Farooq and of the second wireless communication portion 33 of Chuang contact the backside 80B in the combined device, they are on the same level).
Regarding claim 13, the combination of Farooq, Chuang, Nakano, and Meyer described in the discussion of claim 9 further teaches “The semiconductor package of claim 9, wherein one side of the second wireless communication element extends toward a center of the logic chip” (Farooq [0062]; Fig. 7A, logic chip 75; Chuang [0038]; Fig. 1, second wireless communication portion 33; note that, as the second wireless communication portion 33 of Chuang has a finite extent, some part of it can be considered to extend toward the logic chip 75 of Farooq), “the one side of the second wireless communication element and one side of the chip structure have a step difference” (Farooq [0062]; Fig. 7A, translator chip 80; Chuang [0038]; Fig. 1, second wireless communication portion 33; Meyer [0013]; Fig. 2, coupler 210; note that, as the second wireless communication portion 33 of Chuang is disposed outside of the translator chip 80 of Farooq in the combined device, there will be a step difference between the second wireless communication portion 33 and the translator chip 80).
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Farooq and Chuang, in further view of Meyer.
Regarding claim 19, Farooq teaches “A semiconductor package” (Farooq [0062]; Fig. 7A, semiconductor structure 700A) “comprising: a package substrate” (Farooq [0062]; Fig. 7A, packaging substrate 71); “a logic chip on the package substrate” (Farooq [0062]; Fig. 7A, note that the logic chip 75 is disposed on the packaging substrate 71); “a chip structure on the logic chip” (Farooq [0062]; Fig. 7A, translator chip 80 and memory chip 85), “and including a memory circuit” (Farooq [0062]; Fig. 7A, memory chip 85), “and a first through-electrode” (Farooq [0062]; Fig. 7A, the through-silicon vias 83 disposed directly above the logic chip 75) “and a second through-electrode” (Farooq [0062]; Fig. 7A, the through-silicon vias 83 not disposed directly above the logic chip 75) “electrically connected to the memory circuit” (Farooq [0062]; Fig. 7A; note that the memory chip 85 is electrically connected to the through-silicon vias 83 through the connections 86A); “and a conductive vertical structure” (Farooq [0062]; Fig. 7A, pillars 74).
Farooq, however, does not teach “(a package substrate) including a first wiring and a second wiring”, “(a logic chip) electrically connected to the first wiring of the package substrate”, “a first wireless communication element disposed within the logic chip; a second wireless communication element below the chip structure, electrically connected to the first through-electrode, and overlapping the first wireless communication element in a vertical direction”, and “(a conductive vertical structure) electrically connecting the second through-electrode of the chip structure and the second wiring of the package substrate”. Farooq does, however, teach that the conductive vertical structure (Farooq [0062]; Fig. 7A, pillars 74) connects the chip structure to the package substrate (Farooq Fig. 7A; note that the pillars 74 connect the translator chip 80 to the packaging substrate 71).
Chuang, on the other hand, does teach “(a package substrate) including a first wiring” (Chuang [0043] and [0055]; Fig. 1, first substrate 10 and first wirings) “and a second wiring” (Chuang [0087]; Fig. 1, second wirings), “a first wireless communication element disposed within the logic chip” (Chuang [0038]; Fig. 1, note that the first wireless communication portion 22 is inside the first semiconductor die 20; also see [0061]); “a second wireless communication element” (Chuang [0039]; Fig. 1, second wireless communication element 33), “and overlapping the first wireless communication element in a vertical direction” (Chuang Fig. 1; note that the second wireless communication element 33 vertically overlaps the first wireless communication element 22). In addition, Chuang teaches a second wiring in the substrate that is electrically connected to the memory dies (Chuang [0045] and [0087]; Fig. 1, note that the second wirings are connected to the second semiconductor dies 31 through the signal line 41 in the second substrate 40).
The wiring in the first substrate of Chuang can be incorporated into the device of Farooq as wiring in the packaging substrate, such that some of the wiring is connected to the logic chip (Chuang [0055]; Fig. 1, first wirings) and some is connected to the pillars (Chuang [0087]; Fig. 1, second wirings). In addition, the wireless communication elements of Chuang can be incorporated into the device of Farooq by introducing a wireless communication element inside the translator chip 80 as a substitute for the connections 81 between the translator chip 80 and logic chip 75 and electrically connected to the fanout wiring within the backside 80B and another wireless communication element within the logic chip 75 that is coupled to the element inside the translator chip. The combined device teaches “(a second wireless communication element) electrically connected to the first through-electrode” (Farooq [0062]; Fig. 7A, portion of backside 80B above the logic chip 75; Chuang [0038]; Fig. 1, second wireless communication portion 33).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to introduce two sets of wirings in the packaging substrate of Farooq as taught by Chuang, one connected to the logic chip and one connected to the pillars, because doing so allows for power delivery to the logic chip and memory chips, respectively, and it would be a simple combination of elements of the two disclosures. Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the application to introduce a wireless communication chip inside the translator chip of Farooq connected to the fanout wiring within the backside and a second wireless communication element within the logic chip, both as taught by Chuang, because the use of wireless communication would speed up data transfer between the two chips compared to traditional electrical coupling through wires, the fanout wiring providing the required power for the first wireless communication chip, and it would be a simple combination of elements of the two disclosures.
The combination of Farooq and Chuang just described, however, does not teach “(a second wireless communication element) below the chip structure”.
Meyer, on the other hand, teaches pairs of inductive coils that are used to provide wireless coupling of semiconductor dies (Meyer [0013]: “The signal can be conducted through the trace 209 of the PCB 205 to another point. At the other point, the signal can be wirelessly transferred to the second integrated circuit package 202 using a pair of couplers 210. In certain examples, this wireless transfer of the signal can be achieved by the use of couplers 210, 211, 212, 213 that include coils or inductive lines.”; Fig. 2, couplers 210-213) and lie outside of said dies (Meyer Fig. 2; note that the couplers 210-213 lie outside the PCB 205 and the first and second integrated circuit packages 201 and 202).
The placement of the inductive coils of Meyer outside of their respective semiconductor dies can be incorporated into the combined device of Farooq and Chuang by placing the first wireless communication portion directly on the top of the logic chip and the second wireless communication portion directly on the bottom of the translator chip. The combined device teaches “wherein the second wireless communication element is disposed between the buffer chip and the logic chip” (Farooq [0062]; Fig. 7A, logic chip 75 and translator chip 80; Chuang [0039]; Fig. 1, second wireless communication portion 33; Meyer [0013] Fig. 2, coupler 210; note that the second wireless communication portion 33 of Chuang would be located between the logic chip 75 and translator chip 80 of Farooq in the combined device).
It would have been obvious to one of ordinary skill in the art to place the two wireless communication portions of the combined device of Farooq and Chuang directly on top of the logic chip and directly on the bottom of the translator chip as taught by Meyer because doing so would bring the two portions into closer proximity, enhancing their ability to communicate with one another, and it would be a simple combination of elements of the two disclosures.
Regarding claim 20, the combination of Farooq, Chuang, and Meyer described in the discussion of claim 19 teaches “The semiconductor package of claim 19”, but does not teach “further comprising a heat dissipation member on the logic chip and spaced apart from the chip structure.”
Farooq, on the other hand, teaches an embodiment of their invention (Farooq [0070]; Fig. 8, semiconductor structure 800) that has a lid (Farooq [0070]; lid 110) and a heat sink (Farooq [0070]; Fig. 8, heat sink 120) enclosing the device. Furthermore, the heat sink lies directly over the logic chip (Farooq Fig. 8; note that the heat sink 120 is disposed directly above the logic chip 5) and is vertically spaced apart from the memory chip (Farooq Fig. 8; note that the heat sink 120 is separated from the memory chip 15 by the lid 110).
The lid and heat sink of the embodiment of Farooq shown in Fig. 8 can be incorporated into the combined device of Farooq, Chuang, and Meyer described in the discussion of claim 19 by placing a lid over the device and disposing a heat sink on top of the lid. The combined device teaches “further comprising a heat dissipation member on the logic chip” (Farooq Fig. 8; note that the heat sink 120 is disposed directly above the logic chip 5) “and spaced apart from the chip structure” (Farooq Fig. 8; note that the heat sink 120 is separated from the memory chip 15 by the lid 110).
It would have been obvious to one of ordinary skill in the art to introduce a lid and heat sink as taught by the embodiment of Farooq shown in Fig. 8 into the combined device of Farooq, Chuang, and Meyer described in the discussion of claim 19 because doing so would allow for the device to be cooled and it would be a simple combination of elements of the disclosures.
Allowable Subject Matter
Claims 10 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 12 would be allowable if rewritten to overcome the rejection under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record, whether taken singularly or in combination, especially when all claim limitations are considered, fails to teach or suggest the full limitations of:
Claim 10, which recites “wherein the second wireless communication element further includes a front pad in direct contact with the lower surface pad of the buffer chip.”
Claim 12, which recites “wherein the semiconductor package further includes a support structure between a lower surface of the second wireless communication element and the package substrate.”
Claim 18, which recites “wherein the first wireless communication element further includes front pads in contact with the second lower surface pads.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Robert E Throckmorton whose telephone number is (571) 272-7014. The examiner can normally be reached 7:30 AM - 11:30 AM and 12:30 PM - 4:30 PM ET Monday to Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H Loke can be reached at (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/R.E.T./Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
Prosecution Insights