DETAILED ACTION
The instant action is in response to application 13 May 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification is objected to for the following informalities:
The title is not descriptive. Examiner suggests Low Pass Filtered Phase Voltage to Improve Transient Response in a Buck Converter.
¶3 “are easy to cause” should be “easily cause”.
¶6 “cross in the load fluctuation, so as to” should be “cross when the load fluctuates, in order to”.
¶6 “signal, to eliminate” should be “signal, eliminating”.
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Taiwan on29 December 2023.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
For method claims, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated. (The claims have been condensed.)
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Tateshi (US 20090140708) in view of Lee (US 9013164).
As to claim 11, Tateshi discloses (see image below) A power convertor circuit, configured to convert an input voltage signal to output an output voltage signal at a load terminal, and comprising: a power stage circuit, configured to receive the input voltage signal, and configured to output a phase voltage signal at a phase output terminal, wherein the phase output terminal is coupled to the load terminal through an inductor; and a control circuit, coupled to the power stage circuit, the phase output terminal and the load terminal, configured to generate a first ripple signal according to the phase voltage signal, configured to generate a second ripple signal according to a direct current (DC) signal generated by processing the first ripple signal, a reference voltage signal and a feedback signal related to the output voltage signal, and configured to control the power stage circuit to operate according to a preset off time when the second ripple signal continuously transcends the first ripple signal, so that an inductor current flowing through the inductor is increased (the circuit always operates at a predetermined minimum ff time, not just on the conditional),
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Tateshi does not disclose wherein the control circuit comprises a DC offset calibration circuit, and the DC offset calibration circuit is configured to calibrate the reference voltage signal, to eliminate an offset between the reference voltage signal and the feedback signal.
Lee teaches wherein the control circuit comprises a DC offset calibration circuit, and the DC offset calibration circuit is configured to calibrate the reference voltage signal, to eliminate an offset between the reference voltage signal and the feedback signal (Lee, items 110, 115).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use the reference adjustment of Lee in the device above in order to improve ripple tolerance (Lee, Col.2, lines 15-30).
As to claim 19, Tateshi in view of Lee teaches a feedback circuit, coupled to the load terminal and the control circuit, and configured to output the feedback signal to the control circuit according to the output voltage signal (divider 40,42).
As to claim 20, Tateshi in view of Lee teaches wherein the first ripple signal is related to the inductor current (phase voltage is related to inductor current), and the DC signal is related to a DC component of the output voltage signal (a low pass filter on phase voltage should produce something similar to the output).
Allowable Subject Matter
Claims 1-10 allowed.
Claims 12-18 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) and 35 U.S.C. 112(a) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 1, the prior art fails to disclose: “DC offset calibration circuit, configured to calibrate the reference voltage signal to eliminate an offset between the reference voltage signal and the feedback signal; and a buffer circuit, coupled to the signal processing circuit, and configured to buffer the DC signal to output a buffered DC signal, wherein the buffered DC signal is related to the second ripple signal; and a comparison circuit, coupled to the first ripple generation circuit and the buffer circuit, configured to compare the first ripple signal and the second ripple signal, and configured to trigger an on-time generation circuit to control the power stage circuit to operate according to a preset off time when the second ripple signal continuously transcends the first ripple signal, so that the inductor current is increased.” in combination with the additionally claimed features, as are claimed by the Applicant.
As to claim 12, the prior art fails to disclose: “wherein the control circuit further comprises: a first ripple generation circuit, coupled to the phase output terminal, and configured to filter the phase voltage signal to output the first ripple signal; a signal processing circuit, coupled to the first ripple generation circuit, and configured to process the first ripple signal to output the DC signal; a second ripple generation circuit, coupled to the signal processing circuit, and configured to output the second ripple signal according to the DC signal, the reference voltage signal and the feedback signal, wherein the second ripple generation circuit comprises: the DC offset calibration circuit; and a buffer circuit, coupled to the signal processing circuit, configured to buffer the DC signal to output a buffered DC signal, wherein the buffered DC signal is related to the second ripple signal; and a comparison circuit, coupled to the first ripple generation circuit and the second ripple generation circuit, and configured to compare the first ripple signal and the second ripple signal; and an on-time generation circuit, coupled to the comparison circuit and the power stage circuit, and configured to be triggered by the comparison circuit to control the power stage circuit to operate according to a minimum off time when the second ripple signal continuously transcends the first ripple signal.” in combination with the additionally claimed features, as are claimed by the Applicant.
Please note: while objected or allowed claims have been indicated, only the presented claims have been examined for compliance with form and 35 USC 112 consideration. As a reminder, claims that are dependent upon objected claims still require examination for form and 35 USC 112 issues even if they overcome 35 USC 102 and 103 rejections. Similarly, amendments incorporating allowable subject matter into independent claims requires reconsideration for dependent claim form and any possible 35 USC 112 issues that arise through amendments even if the 35 USC 102 and 103 rejections are overcome. As such, applicant is advised that while examiner can enter previously allowed claims or previously objected claims rewritten into independent form after final rejection, any other claims may not be entered.
Conclusion
Examiner has cited particular column, paragraph, and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER M NOVAK whose telephone number is (571)270-1375. The examiner can normally be reached on 9AM-5PM,Monday through Thursday, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal Hammond can be reached on 571-270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER M NOVAK/ Primary Examiner, Art Unit 2839