Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. There are a total of 20 claims and claims 1-20 are pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/12/2025 and 06/03/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 2022/0013992 A1; filing date: Sept. 25, 2018) in view of Osiander et al. (US 2006/0193356 A1 ).
Regarding claim 1, Wang discloses a Vertical-Cavity Surface-Emitting Laser (VCSEL) die comprising ([see in Fig. 2]-VSCEL 1, VSCEL 2, and VSCEL 3 ): a VCSEL array configured for flip chip bonding to a substrate([see in Fig.9]- FIG. 9 illustrates an exemplary VCSEL array 900 in a cross-sectional view, according to the present invention. A VCSEL array die is flip-chip bonded on a sub-mount 909; [ see also abstract]), wherein the VCSEL array is designed for emission from a substrate side of the chip([see in Fig. 8-9]- FIG. 8 illustrates an exemplary sub-mount 801 in a cross-sectional view, according to the present invention. In above discussions, VCSELs are of the top-emitting type, which means that laser beams are emitted through the p-type DBR in a direction opposite to the substrate. In some other cases, a VCSEL chip is turned upside down and packaged using flip-chip methods. For a VCSEL chip with flip-chip bonding, output laser beams go through the substrate and the chip's contact regions face downward towards a submount); integrated beam shaping optics([see in Fig. 5]- FIG. 5 illustrates an exemplary optical component 501 and an exemplary VCSEL array chip 502, according to one embodiment of the present invention. The ring shaped objects represent metallic annular rings. Arranged on a downward facing surface of optical component 501, the annular rings are contact pads and represent a mirror image of a predetermined pattern, such as an irregular pattern. The contact pads are electrically connected to each other by a metal layer which contains bar-shaped connection lines made by metal plating. The annular rings on VCSEL array chip 502 represent metal contacts of the VCSELs. Each annular ring encircles a laser beam output window of a VCSEL).
However, Wang does not explicitly disclose electrical contacts including a top surface contact and an etched metal connection through a top mirror structure to a bottom n-mirror, or to an n-doped buffer layer under the bottom n-mirror or to the substrate.
In an analogous art, Osiander discloses electrical contacts including a top surface contact and an etched metal connection through a top mirror structure to a bottom n-mirror, or to an n-doped buffer layer under the bottom n-mirror or to the substrate([para 0036];[0051]- The design of the PIN diode for the Fabry-Perot interferometer is important. Due to the thin silicon layers the PIN diode is made by laterally placing p doped, intrinsic and n doped areas next to each other and repeating until the desired size of the diode is reached. In most diodes the p and n doped silicon would be covered with contacts for electrical connection to a metal interconnect layer in the CMOS process). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the technique of Osiander to the modified system of Wang a scalable architecture based in silicon on sapphire (SOS) CMOS for building an interferometric optical detection system and is the first such system to be implemented in a commercial CMOS process. As such the invention offers easier integration than other similar optical readout architectures including providing for all signal processing to be performed on the same chip as the sensing photodetector [Osiander; para 009].
Regarding claim 2, Wang discloses wherein a back side of a wafer on which the VCSEL die is built is polished and/or an anti-reflective coating is applied thereto([see in Fig. 3]- FIG. 3 shows an exemplary optical component 300 in a cross-sectional view, which may be used to create a VCSEL array of an irregular pattern from a regular-patterned array. Optical component 300 may be made from a material which is transparent or substantially transparent at the wavelengths of interest. It has an upward facing surface 303 and a downward facing surface 301. Both surfaces may be coated with an antireflection layer to reduces reflection).
Regarding claim 3, Wang discloses wherein the substrate comprises GaAs([[para 0010-0011]- a VCSEL array comprises forming a plurality of VCSEL structures in a regular pattern on a substrate. The plurality of VCSEL structures share one electrode (e.g., the cathode terminal). The method further comprises disabling a selected number but not all of the plurality of VCSEL structures by ion implantation such that the remaining VCSEL structures form an array of a predetermined irregular pattern; etching contacts, each corresponding to one of the plurality of VCSEL structures, including the disabled ones; and depositing a metal layer to electrically connect all contacts, depositing a metal layer to electrically connect all contacts is equivalent to the substrate comprises GaAs).
Regarding claim 4, Osiander discloses wherein the VCSEL die is adaptable to emission wavelengths greater than 870 nm for applications in mobile devices or LiDAR systems([para 0016; 0034]- a Fabry-Perot-type interferometer is constructed to measure vertical deflections of a moving device. This implementation relies on the thickness of the PIN photodiode available from the 100 nm thick active silicon layer in the Peregrine SOS CMOS process. When the proper wavelength of light is sent through the thin PIN photodiode and is reflected back into the photodiode a standing wave is produced. The intensity of the standing wave is dependent on the position of the MEMS or other movable device. The light intensity absorbed in the photodiode allows determination of the position of the device).
Regarding claim 5, Osiander discloses wherein a contact of the electrical contacts is brought to a surface by a metal trace along side walls to a top surface, by plating the contact, or by using a stud bumping process([para 0036]- In most diodes the p and n doped silicon would be covered with contacts for electrical connection to a metal interconnect layer in the CMOS process. These metal lines inside the photodiode form a grating which could interfere with and possibly destroy the standing wave. One solution is to keep the contacts to the p and n doped regions at the periphery of the diode (FIG. 3)).
Regarding claim 6, Wang discloses wherein the integrated beam shaping optics are formed from a curable polymer material deposited and patterned on a back side of the VCSEL die([see in Fig. 5]- FIG. 5 illustrates an exemplary optical component 501 and an exemplary VCSEL array chip 502, according to one embodiment of the present invention. The ring shaped objects represent metallic annular rings. Arranged on a downward facing surface of optical component 501, the annular rings are contact pads and represent a mirror image of a predetermined pattern, such as an irregular pattern. The contact pads are electrically connected to each other by a metal layer which contains bar-shaped connection lines made by metal plating. The annular rings on VCSEL array chip 502 represent metal contacts of the VCSELs. Each annular ring encircles a laser beam output window of a VCSEL).
Regarding claim 7, Wang discloses wherein the curable polymer material is an epoxy resin([see in Fig. 1-2,4 and ]-see in VCSEL 1-3, top side down a curable epoxy on the back surface as VCSEL die).
Regarding claim 8, Wang discloses wherein a lens structure is embossed on a back side of the VCSEL die([see in Fig. 6-7]- a convex lens shape).
Regarding claim 9, Wang discloses wherein lenses of the lens structure are offset relative to the VCSEL([see in Fig. 6-7]- Surface 604, on the other hand, has protruded structures 603 in a convex lens shape. Structure 603 make an output beam from a VCSEL less divergent and may have applications in certain cases).
Regarding claim 10, Wang discloses wherein the substrate comprises GaAs([see in Fig. 1,2 and 4-7]-see in Fig. 1, GaAs layer) wherein a pattern of the curable polymer material is etched or embossed, and wherein the curable polymer material is a mask for transferring the pattern directly into the substrate([see in Fig. 1-2]- . VCSEL array 200 is manufactured by forming a plurality of VCSEL structures (including VCSELs 1, 2, and 3) on a substrate in a regular pattern and depositing a metal layer 204 under the substrate to serve as the shared cathode of the plurality of VCSEL structures. Up to this point, these manufacturing steps are accomplished by using the manufacturing process of a regular-patterned VCSEL array. Then, an insulation layer is deposited on top of the plurality of VCSEL structures. Here, different from the remaining fabrication steps of manufacturing a regular-patterned VCSEL array, contact vias including 201 and 203 are etched for only a selected number but not all of the VCSEL structures so that after a metal layer 205 is deposited, only the selected VCSEL structures having the vias are electrically connected. In one embodiment, the selected VCSEL structures form an irregular pattern).
Regarding claim 11, Wang discloses wherein vias are etched in the curable polymer material and thin metal contact strips are patterned on the substrate and/or on a top of the curable polymer material([see in Fig. 5]- FIG. 5 illustrates an exemplary optical component 501 and an exemplary VCSEL array chip 502, according to one embodiment of the present invention. The ring shaped objects represent metallic annular rings. Arranged on a downward facing surface of optical component 501, the annular rings are contact pads and represent a mirror image of a predetermined pattern, such as an irregular pattern. The contact pads are electrically connected to each other by a metal layer which contains bar-shaped connection lines made by metal plating. The annular rings on VCSEL array chip 502 represent metal contacts of the VCSELs. Each annular ring encircles a laser beam output window of a VCSEL).
Regarding claim 12, Wang discloses wherein, on a back side of the VCSEL die, a dielectric layer is positioned between the VCSEL die and an embossed or patterned curable polymer material material([see in Fig. 1-2 and 4-5]- FIG. 5 illustrates an exemplary optical component 501 and an exemplary VCSEL array chip 502, according to one embodiment of the present invention. The ring shaped objects represent metallic annular rings. Arranged on a downward facing surface of optical component 501, the annular rings are contact pads and represent a mirror image of a predetermined pattern, such as an irregular pattern. The contact pads are electrically connected to each other by a metal layer which contains bar-shaped connection lines made by metal plating. The annular rings on VCSEL array chip 502 represent metal contacts of the VCSELs. Each annular ring encircles a laser beam output window of a VCSEL).
Regarding claim 13, Wang discloses wherein a dielectric layer is positioned on top of the substrate([see in Fig. 1-3]- a VCSEL, VCSEL structure, and VCSEL emitter have the same meaning and may be used interchangeably. As shown, each VCSEL includes an active region 101 and reflector regions 102 and 103. For a typical VCSEL, active region 101 may contain a multiple-quantum-well (MQW), reflector region 102 may contain an n-type Distributed Bragg Reflector (DBR), and reflector region 103 may contain a p-type DBR. The quantum well and DBRs are grown on substrate 106 in an epitaxial process. Substrate 106 has n-type doping. Reflector regions 102 and 103 and substrate 106 are electrically conductive. An insulation layer 107 (e.g. Silicon Nitride) is deposited on the top surfaces of reflector regions 103 and a plurality of vias are etched on the insulation layer 107. Then, metal layer 104 is deposited on the insulation layer. Metal layer 105 is deposited on the bottom surface of substrate 106. Metal layers 104 and 105 serve as the anode and cathode terminals, respectively).
Regarding claim 14, Wang discloses wherein a pattern of the curable polymer material is etched or embossed, wherein the curable polymer material is a mask for transferring the pattern directly into the substrate; and wherein the substrate is a dielectric layer([see in Fig. 1-2 and 4-5]- FIG. 5 illustrates an exemplary optical component 501 and an exemplary VCSEL array chip 502, according to one embodiment of the present invention. The ring shaped objects represent metallic annular rings. Arranged on a downward facing surface of optical component 501, the annular rings are contact pads and represent a mirror image of a predetermined pattern, such as an irregular pattern. The contact pads are electrically connected to each other by a metal layer which contains bar-shaped connection lines made by metal plating. The annular rings on VCSEL array chip 502 represent metal contacts of the VCSELs. Each annular ring encircles a laser beam output window of a VCSEL).
Regarding claim 15, Wang discloses further comprising pockets etched into the substrate comprising GaAs, with unetched pillars between the pockets([[para 0010-0011]- a VCSEL array comprises forming a plurality of VCSEL structures in a regular pattern on a substrate. The plurality of VCSEL structures share one electrode (e.g., the cathode terminal). The method further comprises disabling a selected number but not all of the plurality of VCSEL structures by ion implantation such that the remaining VCSEL structures form an array of a predetermined irregular pattern; etching contacts, each corresponding to one of the plurality of VCSEL structures, including the disabled ones; and depositing a metal layer to electrically connect all contacts, depositing a metal layer to electrically connect all contacts is equivalent to the substrate comprises GaAs).
Regarding claim 16, Wang discloses wherein the vertical-cavity surface-emitting laser die comprises one pocket per vertical-cavity surface emitting laser ([see in Fig. 1]- Array 100 comprises VCSELs 1, 2, and 3 on a substrate 106. It should be noted that the array 100 may comprise thousands of VCSELs and only three VCSELs are shown here for simplification purposes. Similarly, in other figures and descriptions below, only a few VCSELs or part of an array are shown for simplification purposes. VCSEL 1, 2, or 3 represents a VCSEL structure or VCSEL emitter which emits a laser beam when charged with an electrical current. As used herein, a VCSEL, VCSEL structure, and VCSEL emitter have the same meaning and may be used interchangeably).
Regarding claim 17, Wang discloses further comprising a diffuser or lens structure on another transparent substrate mounted with a optically patterned side down, facing the substrate comprising GaAs([see in Fig. 1 and para 0005]- A regular-patterned VCSEL array may be made by the same fabrication method as an irregular-patterned VCSEL array. Take a top-emitting VCSEL array for example. When a regular-patterned VCSEL array is made, VCSELs are formed on a substrate in a regular pattern. The VCSELs share a common cathode terminal and are separated from each other by isolation trenches. A contact is formed on top of each VCSEL. In the last fabrication step(s), a metal layer is deposited above the VCSELs to connect all these top contacts. When an irregular-patterned VCSEL array is made, VCSELs are formed on a substrate in a predetermined irregular pattern).
Regarding claim 18, Wang discloses wherein the pockets of the substrate comprising GaAs extend to a bottom side mirror, with a frame of GaAs substrate left around an emitting area of VCSELs of the VCSEL array([see in Fig.3-5]- . The VCSEL array chip may be fabricated by using the manufacturing process of a regular-patterned VCSEL array but without the metallization that completes the connection of all VCSELs. The optical component has an upward facing surface 405 and a downward facing surface 406. Surface 406 faces the VCSEL array chip and has contact pads 403 which are arranged in a mirror image of a predetermined irregular pattern. The optical component is mounted on the VCSEL chip such that contact pads 403 are bonded with metal contacts 401 of the VCSEL array chip. Metal contacts 401 are contacts for the p-type DBRs of the VCSELs. Contacts 403 and 401 are bonded by an electrically conductive adhesive material 402. Material 402 may be cured at an elevated temperature. As shown in the figure, VCSELs 1 and 3 are selected and electrically connected to contact pads 403, but VCSEL 2 is not selected because the optical component does not have contact pad 403 corresponding to VCSEL 2).
Regarding claim 19, the claim is interpreted and rejected for the same reason as set forth in claim 1. Hence; all limitations for claim 19 have been met in claim 1. Osiander discloses a photodetector([para 009-0010]- photodetector); wherein the VCSEL die is attached to a circuit board or sub-mount with a solder or bump bonds on the VCSEL die([para 0015]- VCSEL drivers, VCSEL power output stabilization circuits and Analog to Digital converters. Analog and digital CMOS circuits can be used for a wide range of signal processing); and wherein the photodetector is placed on a same circuit board or sub-mount right next to the VCSEL die([see FIGS. 1A, 1B, 2, 7, and 8 ]- an array of photodetectors and VCSELs).
Regarding claim 20, Osiander discloses a glass optics layer positioned over the VCSEL die([see in Fig. 9A-9B]), wherein the photodetector is a thin film transistor disposed on a top surface of the said glass optics layer or at comers or edges of the VCSEL array([see FIGS. 1A, 1B, 2, 7, and 8 ]- an array of photodetectors and VCSELs).
Citation of Pertinent Prior Art
The prior art are made of record and not relied upon but considered pertinent to applicant’s disclosure:
1. Chen et al., US 2017/0353004 A1, discloses a VCSEL illuminator module includes a module forming a physical cavity having electrical contacts positioned on an inner surface of the module that feed through the module to electrical contacts positioned on an outer surface of the module.
2. Mor et. al., US 2016/0197452 A1, discloses optoelectronic devices, and specifically to integrated projection devices.
3. Hibbs-Brenner et al., US. Pat. No. 9,088,134 B2, discloses devices, systems, and fabrication methods for vertical-cavity surface-emitting lasers (VCSELs), including those emitting wavelengths in the visible red spectrum (e.g., in some embodiments, in a range of about 600-700 nm), those having hybrid mirrors and those emitting near-infrared light (e.g., in some embodiments, about 720 nm).
4. Dummer et al., US. Pat. No. 8,989,230 B2, discloses a tunable-output vertical-cavity surface-emitting solid-state laser that uses a movable suspended mirror for adjusting the length of the cavity of the laser.
5. CARSON et al., US 2019/0036308 A1, discloses vertical-cavity surface-emitting laser (VCSEL) arrays, and devices, methods, and systems related to series-connected architectures.
6. Yeh, US 2003/0031218 A1, discloses Vertical Cavity Surface Emitting Lasers (VCSELs).
Conclusion
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/MD N HAQUE/ Primary Examiner, Art Unit 2487
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