Prosecution Insights
Last updated: July 17, 2026
Application No. 18/661,813

SEMICONDUCTOR MODULE AND HEAT DISSIPATION PLATE

Non-Final OA §102
Filed
May 13, 2024
Priority
Jun 12, 2023 — JP 2023-096298
Examiner
WATTS, JEREMY DANIEL
Art Unit
Tech Center
Assignee
MIRISE Technologies Corporation
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
1y 1m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
72 granted / 85 resolved
+24.7% vs TC avg
Moderate +14% lift
Without
With
+13.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
26 currently pending
Career history
113
Total Applications
across all art units

Statute-Specific Performance

§103
97.7%
+57.7% vs TC avg
§102
1.5%
-38.5% vs TC avg
§112
0.8%
-39.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 85 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yamamoto (US 20170213778 A1). Regarding claim 1, Yamamoto teaches a semiconductor module (Fig 9; semiconductor device, [0007]) comprising: a heat dissipation plate (HP: layers 10/30/40/50) having a plate shape (shown with plate shape); and a semiconductor element (20) mounted (shown mounted) to the heat dissipation plate (HP) in a thickness direction (Z) of the heat dissipation plate (HP) and generating heat when supplied with electricity (well known to generate heat when supplied with electricity), wherein the heat dissipation plate (HP) includes a first heat dissipation portion (11) and a second heat dissipation portion (12) formed of a material (graphite, [0028]) having anisotropic thermal conductivity (anisotropic, [0028]), the first heat dissipation (11) portion includes a position facing (shown facing) the semiconductor element (20) in the thickness direction (Z), and has higher (higher, [0028]) thermal conductivity (1700 W/m*K, [0028]) in a planar direction (X, [0029]) of a first virtual plane (XZ) parallel (shown parallel) to the thickness direction (Z) than in a direction (Y) perpendicular (shown perpendicular) to the planar direction (X) of the first virtual plane (XZ), and the second heat dissipation portion (12) is connected (shown connected) to the first heat dissipation portion (11) in a direction parallel (X) to the planar direction (X) of the first virtual plane (XZ) and perpendicular (shown perpendicular) to the thickness direction (Z), and has higher (higher, [0028]) thermal conductivity (1700 W/m*K, [0028]) in a planar direction (Y) of a second virtual plane (XY) perpendicular (shown perpendicular) to the thickness direction (Z) than in a direction (Z) perpendicular (shown perpendicular) to the planar direction (Y) of the second virtual plane (XY). Regarding claim 2, Yamamoto teaches the module of claim 1 and goes on to teach the second heat dissipation portion (12, Fig 9) is connected (shown connected) to a portion of the first heat dissipation portion (11) extending (shown extending) in a direction (X) parallel (shown parallel) to the planar direction (X) of the first virtual plane (XZ) and perpendicular (shown perpendicular) to the thickness direction (Z) of the heat dissipation plate (HP) from the position facing the semiconductor element (20), and is also connected (shown connected) to a portion of the first heat dissipation portion (11) extending (shown extending) in a direction (Z) perpendicular (shown perpendicular) to the planar direction (X) of the first virtual plane (XZ) from the position facing the semiconductor element (20). Regarding claim 3, Yamamoto teaches the module of claim 1 and goes on to teach the heat dissipation plate (HP, Fig 9) further includes a third heat dissipation portion (50), and the third heat dissipation portion (50) is connected (shown indirectly connected) to the second heat dissipation portion (12) in a direction parallel (Y) to the planar direction (Y) of the second virtual plane (XY), and has higher (higher, [0061]) thermal conductivity (1700 W/m*K, [0028]) in a planar direction (Z) of a third virtual plane (YZ) that is not perpendicular (shown not perpendicular) to a direction (Z) in which the third heat dissipation portion (50) is connected (shown connected) to the second heat dissipation portion (12) and is parallel (shown parallel) to the thickness direction (Z) than in a direction (X) perpendicular (shown perpendicular) to the planar direction (Z) of the third virtual plane (YZ). Regarding claim 4, Yamamoto teaches the module of claim 3 and goes on to teach the third virtual plane (YZ, Fig 9) is parallel (shown parallel) to a direction (Z) in which the third heat dissipation portion (50) is connected (shown connected) to the second heat dissipation portion (12) and is parallel (shown parallel) to the thickness direction (Z). Regarding claim 5, Yamamoto teaches the module of claim 3 and goes on to teach the first virtual plane (XZ, Fig 9) and the third virtual plane (YZ) are parallel (shown parallel) to a direction (Z) in which the first heat dissipation portion (11), the second heat dissipation portion (12), and the third heat dissipation portion (50) are arranged. Regarding claim 6, Yamamoto teaches the module of claim 1 and goes on to teach the heat dissipation plate (HP, Fig 9) further includes a metal plate (30), and the metal plate (30) is disposed on (shown on) a surface (10T: top surface of 10) of the heat dissipation plate (HP) facing (shown facing) the thickness direction (Z) or at an intermediate position in the thickness direction of the heat dissipation plate. Regarding claim 7, Yamamoto teaches the module of claim 1 and goes on to teach the heat dissipation plate (HP, Fig 9) further includes an insulator (40) having a plate shape (shown with plate shape), and the insulator (40) is disposed on (shown on) a surface (10B: bottom surface of 10) of the heat dissipation plate (HP) facing (shown facing) the thickness direction (Z) or at an intermediate position in the thickness direction of the heat dissipation plate. Regarding claim 8, Yamamoto teaches the module of claim 1 and goes on to teach the heat dissipation plate (HP, Fig 9) further includes a metal plate (30), and the metal plate (30) covers (shown covering) surfaces (11a/12a) of the heat dissipation plate (HP) facing (shown facing) the thickness direction (Z) and surfaces (11c/12c: left side surfaces of 11 and 12) of the heat dissipation plate (HP) facing (shown facing) a direction (X) perpendicular (shown perpendicular) to the thickness direction (Z). Regarding claim 9, Yamamoto teaches the module of claim 1 and goes on to teach the heat dissipation plate (HP, Fig 9) further includes a metal plating layer (30) disposed on (shown on) a surface (10T: top surface of 10) of the heat dissipation plate (HP) facing (shown facing) the thickness direction (Z). Regarding claim 10, Yamamoto teaches a heat dissipation plate (HP: layers 10/30/40/50, Fig 9) comprising: a first heat dissipation portion (11) and a second heat dissipation portion (12) formed of a material (graphite, [0028]) having anisotropic thermal conductivity (anisotropic, [0028]), wherein the first heat dissipation portion (11) includes a position to face (shown facing) a semiconductor element (20) that is to be mounted (shown mounted) to the heat dissipation plate (HP) in a thickness direction (Z) of the heat dissipation plate (HP), and has higher (higher, [0028]) thermal conductivity (1700 W/m*K, [0028]) in a planar direction (X, [0029]) of a first virtual plane (XZ) parallel (shown parallel) to the thickness direction (Z) than in a direction (Y) perpendicular (shown perpendicular) to the planar direction (X) of the first virtual plane (XZ), and the second heat dissipation portion (12) is connected (shown connected) to the first heat dissipation portion (11) in a direction parallel (X) to the planar direction (X) of the first virtual plane (XZ) and perpendicular (shown perpendicular) to the thickness direction (Z), and has higher (higher, [0028]) thermal conductivity (1700 W/m*K, [0028]) in a planar direction (Y) of a second virtual plane (XY) perpendicular (shown perpendicular) to the thickness direction (Z) than in a direction (Z) perpendicular (shown perpendicular) to the planar direction (Y) of the second virtual plane (XY). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chou (US 20110186270 A1) - multiple graphite heat spreaders attached to a metal housing Deguchi (US 20190139858 A1) - top and bottom heat spreaders comprised of graphite layers Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeremy D Watts whose telephone number is (703)756-1055. The examiner can normally be reached M-R 8:00am-4:30pm, F 8:00-3pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JEREMY DANIEL WATTS/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

May 13, 2024
Application Filed
Jul 02, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
99%
With Interview (+13.9%)
3y 3m (~1y 1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 85 resolved cases by this examiner. Grant probability derived from career allowance rate.

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