DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-4 and 7-11 are rejected under 35 U.S.C. 102(a) (1) as being anticipated by
Gotou et al. (US 2005/0231286 and Gotou hereinafter)
Regarding claim 1, Gotou discloses a radio frequency amplifier circuit [figs. 1-2] comprising: a Doherty amplifier [10, fig. 1] including a main amplifier [16] and a peak amplifier [18], the main amplifier including: a first input end [node connected to 16 and 44]; a first output end [output node 16]; a first transistor [16b] having a control terminal [control terminal 16b] connected to the first input end and a current terminal [drain 16b] connected to the first output end; and only a first harmonic processing circuit [44] among the first harmonic processing circuit and a first fundamental matching circuit [16a], the first harmonic processing circuit being connected to the control terminal of the first transistor and configured to suppress a harmonic to be input to the first transistor [inherent to the structure], the first fundamental matching circuit being connected between the first input end and the control terminal of the first transistor and configured to attain matching with an input impedance of the first transistor [par. 0071-0081], the peak amplifier including: a second input end [node connected to 18 and 46]; a second output end [output node 18]; a second transistor [18b] having a control terminal [control terminal 18b] connected to the second input end and a current terminal [drain terminal 18b] connected to the second output end; and only a second fundamental matching circuit [18a] among a second harmonic processing circuit [46] and the second fundamental matching circuit, the second harmonic processing circuit being connected to the control terminal of the second transistor and configured to suppress a harmonic to be input to the second transistor [inherent to the structure], the second fundamental matching circuit being connected between the second input end and the control terminal of the second transistor and configured to attain matching with an input impedance of the second transistor [par. 0071-0081].
Regarding claim 3, Gotou discloses a radio frequency amplifier device [figs. 1-2] comprising: a Doherty amplifier [10, fig. 1] including a main amplifier [16] and a peak amplifier [18], the main amplifier including: a first input end; a first output end [node connected to 16 and 44]; a first transistor [16b] having a control terminal [control terminal 16b] connected to the first input end and a current terminal [drain terminal 16b] connected to the first output end; and only a first harmonic processing [44] element among the first harmonic processing element and a first fundamental matching element [16a], the first harmonic processing element being connected to the control terminal of the first transistor and configured to suppress a harmonic to be input to the first transistor [inherent to the structure], the first fundamental matching element being connected between the first input end and the control terminal of the first transistor and configured to attain matching with an input impedance of the first transistor [par. 0071-0081], the peak amplifier including: a second input end [node connected to 18 and 46]; a second output end [output node 18]; a second transistor [18b] having a control terminal [control terminal 18b] connected to the second input end and a current terminal [drain terminal 18b] connected to the second output end; and only a second fundamental matching element [18a] among a second harmonic processing element [46] and the second fundamental matching element, the second harmonic processing element being connected to the control terminal of the second transistor and configured to suppress a harmonic to be input to the second transistor [inherent to the structure], the second fundamental matching element being connected between the second input end and the control terminal of the second transistor and configured to attain matching with an input impedance of the second transistor [par. 0071-0081].
Regarding claim 4, Gotou discloses wherein an output of the peak amplifier is larger than an output of the main amplifier [par. 0078].
Regarding claim 7, Gotou discloses [see figs. 1-2, 3 and 7] wherein the main amplifier includes: a first wire [70] configured to make a connection between the control terminal of the first transistor and the first harmonic processing element; and a sixth wire [72a, fig. 7] configured to make a connection between the first input end and the control terminal of the first transistor, and a direction in which the first wire extends and a direction in which the sixth wire extends cross in plan view [see figs. 1-2, 3 and 7].
Regarding claim 8, Gotou discloses further comprising: an integrated passive device [12, fig. 1, par. 0052-0054] including the first harmonic processing element and the second fundamental matching element.
Regarding claim 9, Gotou discloses [fig. 1] wherein the integrated passive device includes: a substrate [14a, par. 52-74]; a second metal film [14c1] and a fourth metal film [14c3] that are provided on one surface of the substrate; a dielectric film [between 14a and 14b] provided on the second metal film and the fourth metal film; and a first metal film [wires connecting 14c1 and 16a] and a third metal film [wires connecting 14c3 and 18a] that are provided on the dielectric film, the first harmonic processing element is constituted by the second metal film, the dielectric film, and the first metal film, the second fundamental matching element is constituted by the fourth metal film, the dielectric film, and the third metal film, the first metal film and the control terminal of the first transistor are connected to each other, the third metal film and the control terminal of the second transistor are connected to each other, and the second metal film and the fourth metal film are connected to a reference potential.
Regarding claim 10, Gotou discloses [fig. 1] wherein the integrated passive device includes a fifth metal film [34] provided on the one surface between the first harmonic processing element and the second fundamental matching element and connected to the reference potential.
Regarding claim 11, Gotou discloses [fig. 1] wherein the integrated passive device includes: a via [36] provided in the substrate and connected to the fifth metal film; and a back-side metal film provided on a surface opposite to the one surface and connected to the via and the reference potential [the metal line is implicitly grounded through via/bond wire/backside metal, which is standard multilayer RF substrates ].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Gotou et al. in view of Min et al. (US 2018/0248521 and Min hereinafter).
Regarding claim 2, Gotou discloses all the features with respect to claim 1 as outlined
above. Gotou further discloses wherein the first harmonic processing circuit [44] includes: a first capacitor [44a] having one electrode connected to a reference potential [ground]; and a first wire [44c] configured to connect another electrode of the first capacitor with the control terminal of the first transistor and including a first inductance [44c has inducive behavior, inherent], and the second fundamental matching circuit [18a] includes: a second capacitor [C, fig. 3]; a second wire [L] configured to connect another electrode of the second capacitor with the second input end and including a second inductance [inductor]. Gotou does not explicitly discloses the second capacitor having one electrode connected to the reference potential and a third wire configured to connect the control terminal of the second transistor with the another electrode of the second capacitor and including a third inductance.
However, Min discloses matching circuit [820, fig. 8] includes: a capacitor [capacitor not labeled] having one electrode connected to the reference potential, a second wire [left inductor] configured to connect another electrode of the second capacitor with the second input end and a third wire [right inductor] configured to connect the control terminal of the second transistor with the another electrode of the second capacitor. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the invention of Gotou as taught in Min in order to provide known impedance matching circuit.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Gotou et al.
Regarding claim 5, Gotou discloses all the features with respect to claim 4 as outlined
above. Gotou further discloses wherein the main amplifier includes: a fourth wire [74/76] configured to make a connection between the first output end and the current terminal of the first transistor, the peak amplifier includes: a fifth wire [84/86] configured to make a connection between the second output end and the current terminal of the second transistor. Gotou does not explicitly discloses the fourth wire has a length longer than a length of the fifth wire. One
of ordinary skill in the art would have been motivated to have used the fourth wire has a length longer than a length of the fifth wire since such a range, absent any criticality (i.e. unobvious and/or unexpected result(s)), is generally achievable through routine optimization/ experimentation, and since discovering the optimum or workable ranges, where the general conditions of a claim are disclosed in the prior art, involves only routing skill in the art, In re Alter, 105 USPQ 233 (CCPA 1955). Moreover, in the absence of any criticality (i.e. unobvious and/or unexpected result(s)), the parameter set forth above would have been obvious to a person having ordinary skill in the art at the time the invention was made, In re Woodruff, 919 .2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 6, Gotou discloses all the features with respect to claim 3 as outlined above. Gotou does not explicitly discloses wherein the first harmonic processing element is disposed between the first transistor and the peak amplifier. In view of such teaching, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to Gotou semiconductor device to provide the first harmonic processing element is disposed between the first transistor and the peak amplifier to utilize well known capable option, since it has been held to be within the general skill of a worker in the art to select a known package on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 227 F.2d 197, 125 USPQ416 (CCPA 1960).
Conclusion
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/METASEBIA T RETEBO/ Primary Examiner, Art Unit 2836
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