DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-29 are pending in this application. Claims 11-12 are withdrawn.
Election/Restrictions
Applicant's election with traverse of species 2 claims 7-10, 19-21, and 27-29 in the reply filed on 05/05/26 is acknowledged. The traversal is on the grounds that claims 1-6, 13-18, and 22-26 are generic. This is found persuasive. Claims 1-6, 13-18, and 22-26 are examined as generic claims. Claims 11-12 are withdrawn.
The requirement is still deemed proper and is therefore made FINAL.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 08/11/25. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings were received on 05/13/24. These drawings are acceptable.
Claim Objections
Claims 5, 17, and 25 are objected to because of the following informalities:
The claims are grammatically confusing, “wherein the current sense circuit samples the first inductor current further during the first switch is operated at OFF state for output current limit control for an output current flowing to the second voltage” appears it should be replaced with “wherein the current sense circuit samples the first inductor current ’s turn-off state for output current limit control for an output current flowing to the second voltage.” or similar correction for clarity.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 6-8, 10, 13-14, 18-20, 22, 26-28 are rejected under 35 U.S.C. 103 as being unpatentable over Kotikalapoodi (US 20180367033A1) and further in view of Yen et al. (US 20220311339A1) hereinafter Yen.
Regarding claims 1, 13, and 22, Kotikalapoodi discloses a control circuit/method configured to operably control a switched capacitor converter (figs 4A and 10, converter switched capacitor array 401) which is configured to convert a first voltage into a second voltage and vice versa (fig 4A and 10, VIN to VOUT; par [0086] “bidirectional power supply in FIG. 10”) wherein the switched capacitor converter includes: a plurality of switches which include at least four switches with a first switch included (fig 4A and 10, switched capacitor array 401 including switches S1, S2, S3, S1B, S2B, S3B), wherein the first switch is coupled between the first voltage and a first inductor switching node (fig 4A, S1 is coupled between VIN and SW); a first inductor coupled between the first inductor switching node and the second voltage (fig 4A, inductor 402 coupled between SW and VOUT); and a first flying capacitor coupled to the plurality of switches and configured as a capacitive voltage divider to reduce voltage stress to the plurality of switches (fig 4A, flying capacitors C1 and C2 connected to switches; it is well known that flying capacitors connected in this manor act as a capacitive voltage divider to reduce voltage stress across the switches); wherein the control circuit comprises: a current sense circuit coupled with the first inductor for detecting a first inductor current flowing through the first inductor (fig 9A, current sense components R1, C4 and C5 coupled to inductor L; par [0076] “Components R1, C4 and C5 are optional compensation components which inject a ripple voltage onto the node FB wherein this ripple can be made to emulate the inductor L ripple current”) and sampling the first inductor current during the first switch's turn-on state to generate a sensed current signal (fig 9A, Ramp1; par[0077]);
Kotikalapoodi fails to disclose a first error amplifier configured to compare the sensed current signal with a reference current signal to generate a first amplified signal; and a PWM generator configured to compare the first amplified signal with a first ramp signal for generating switching control signals to control the plurality of switches to control a first switch current flowing to or from the first voltage.
Yen discloses a power supply circuit with current sensing at the input of an inductor. Yen discloses a first error amplifier configured to compare the sensed current signal with a reference current signal to generate a first amplified signal (fig 6, 616 compares IOUT signal from current-sensing circuit 614 and VTH threshold reference; par [0058]); and a PWM generator (fig 6, components pulse-width-modulation (PWM) comparator 604, PWM logic 606, Div2 logic 608) configured to compare the first amplified signal with a first ramp signal for generating switching control signals to control the plurality of switches to control a first switch current flowing to or from the first voltage (fig 6, Ramp and COMP input to 604).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Kotikalapoodi and incorporate the use inductor current sensing and comparator to generate PWM signals for switch control as taught by Yen. The advantage of this design is to use the current senses from the input of the inductor to control the switches and reduce power loss for the power supply.
Regarding claims 2 and 14, Kotikalapoodi and Yen disclose the switched capacitor converter control circuit of claims 1/13, wherein the current sense circuit includes a sense resistor and a sense capacitor coupled to the first inductor for sensing the first inductor current by sensing the voltage across the sense capacitor to generate the sensed current signal (Kotikalapoodi fig 9A, current sense components R1, C4 and C5 coupled to inductor L; par [0076] “inject a ripple voltage onto the node FB wherein this ripple can be made to emulate the inductor L ripple current”).
Regarding claims 6, 18, and 26, Kotikalapoodi and Yen disclose the switched capacitor converter control circuit of claims 1/13/22, wherein the first ramp signal operates with a fixed switching frequency for the switched capacitor converter (Yen, par [0004] switching frequency for the charge pump; fig 6 RAMP signal to PWM comparator 604).
Regarding claims 7, 19, and 27, Kotikalapoodi and Yen disclose the switched capacitor converter control circuit of claims 1/13/22, further comprising a second error amplifier configured to compare the second voltage with a reference voltage signal to generate a second amplified signal for controlling the second voltage (Yen fig 6, comparator 618 with VOUT and VIN/2 reference voltage; par [0059])( Kotikalapoodi, fig 6, error amplifier 507).
Regarding claims 8, 20, and 28, Kotikalapoodi and Yen disclose the switched capacitor converter control circuit of claims 1/13/22, wherein the switching control signals includes a first switching control signal and a second switching control signal (Kotikalapoodi fig 5; par [0053] control signals Phi1, Phi2, and Phi3); wherein the PWM generator (Kotikalapoodi fig 5, PWM control loop 500) includes a first comparator configured to compare the first amplified signal with the first ramp signal for generating the first switching control signal (Kotikalapoodi fig 5, comparator 523 Phi1) and a second comparator configured to compare the first amplified signal with a second ramp signal for generating the second switching control signal (Kotikalapoodi fig 5, comparator 524 or 525 Phi2 or Phi3), wherein the plurality of switches are controlled by the first switching control signal and the second switching control signal for controlling the first switch current flowing to or from the first voltage (Kotikalapoodi fig 5; switches in switching array 530 are controlled by the PWM control loop signals) wherein a starting time point of a pulse of the first control signal determines a first valley of the first inductor current, and a starting time point of a pulse of the second control signal determines a second valley of the first inductor current, thereby achieving valley current mode control for the switched capacitor converter (Kotikalapoodi fig 5; pars [0058] and [0059] describes the valley current at ΔT of time duration of Phi1); wherein the first ramp signal and the second ramp signal are generated based on a first clock signal and a second clock signal respectively, and are related to the inductor current signal (Kotikalapoodi fig 5; par [0048]).
Regarding claim 10, Kotikalapoodi and Yen disclose the switched capacitor converter of claim 1, further comprising: a second switch, a third switch, and a fourth switch, where the first switch is coupled between the first voltage and a first capacitor switching node, the first flying capacitor is coupled between the first capacitor switching node and a second capacitor switching node, the second switch is coupled between the first capacitor switching node and the first inductor switching node, the third switch is coupled between the second capacitor switching node and the first inductor switching node, and the fourth switch is coupled between the second capacitor switching node and a ground potential (Kotikalapoodi fig 4A, switched capacitor array 401 with first switch S1, second switch S2, third switch S2B, fourth switch S1B, flying capacitor C1, first capacitor switching node VMID, second capacitor switching node VMIDB, inductor switching node SW, and ground (symbol) connected to fourth switch S1B; par [0040]).
Claims 9, 21, and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Kotikalapoodi (US 20180367033A1) and Yen et al. (US 20220311339A1) and further in view of Granato et al. (US 9748841 B2) hereinafter Granato
Regarding claims 9, 21, and 29, Kotikalapoodi and Yen disclose the switched capacitor converter control circuit of claims 8/20/28.
Kotikalapoodi and Yen wherein a phase shift between the first ramp signal and the second ramp signal is 180 degrees to ensure balanced control of the switched capacitor converter.
Granato discloses control circuit operates the switching circuit to control a voltage signal across the output nodes using a first clock signal and a phase shifted second clock signal to reduce output ripple current and enhance converter efficiency using valley current control. Granato discloses a phase shift between the first ramp signal and the second ramp signal is 180 degrees to ensure balanced control of the switched capacitor converter (col 3 lines 53-67; col 5 line 49- col 6 line 5 The switching control signals φ1, φ2, φ2′ and φ1′ are generated using ramp circuits 202 and 204 according to the first clock signal CLK0 and a phase shifted second clock signal CLK180 generated by a phase shift circuit 206 according to the first clock signal CLK0).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Kotikalapoodi and Yen and incorporate the use ramp clock signals with 180 phase shift as taught by Granato. The advantage of this design is to reduce output ripple current and enhance converter efficiency using valley current control.
Claims 3, 15, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Kotikalapoodi (US 20180367033A1) and Yen et al. (US 20220311339A1) and further in view of Zhang (US 20130015830 A1).
Regarding claims 3 and 15, Kotikalapoodi and Yen disclose the switched capacitor converter control circuit of claims 1/13.
Kotikalapoodi and Yen fail to disclose the current sense circuit includes a sampling circuit and a low-pass filter for detecting the first inductor current and generating the sensed current signal.
Zhang discloses a current mode controlled switching power supply where current through the inductor is sensed to determine when to turn off or on the switching transistors. Zhang discloses a current sense circuit includes a sampling circuit and a low-pass filter for detecting the first inductor current and generating the sensed current signal (fig 9, 78 sample time sensor and sample and hold 76 and low pass filter 70).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Kotikalapoodi and Yen and incorporate the sampling circuit and low pass filter as taught by Zhang. The advantage of this design is to sample the voltage across the MOSFET 86 at the midway point and hold the voltage during the time the power MOSFET 88 is on. The sampled voltage, after being amplified and filtered, is then summed with the AC sense signal during the time the power MOSFET 88 is on to create the composite current sense signal.
Regarding claim 23, Kotikalapoodi, Yen and Zhang disclose the control method of claim 22, wherein the step of generating the sensed current signal further includes: sampling the first inductor current to generate a sampling current signal; and averaging of the sampling current signal to generate the sensed current signal (Zhang figs 5 and 9, S.H. 76 and sample time sensor 78; par [0047] “The sample and hold circuit 76 further reduces noise and ripple by sampling the voltage across the capacitor C2 at a time when the voltage is a midpoint of the voltage ramp, representing an average current”).
Claims 4-5, 16-17, and 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Kotikalapoodi (US 20180367033A1) and Yen et al. (US 20220311339A1) and further in view of Shao (US 20140253083 A1).
Regarding claim 4, 16, and 24, Kotikalapoodi and Yen disclose the switched capacitor converter control circuit/method of claims 1/13/22.
Kotikalapoodi and Yen fail to disclose wherein the current sense circuit samples the first inductor current during the first switch's turn-on state for input current limit control for the first switch current.
Shao discloses controlling current by method of sampling inductor current in which timing of sampling is performed relative to one of switching on or off of a transistor configured to pass current through an inductor to a load. Shao discloses wherein the current sense circuit samples the first inductor current during the first switch's turn-on state for input current limit control for the first switch current (par [0007] method includes sampling a signal associated with an inductor current of a switching regulator to generate a sampled level, in which timing of sampling is performed relative to one of switching on or off of a transistor configured to pass current through an inductor to a load; par [0027] describes the control circuit 110 having the ability to monitor an indication of the current output to the load via the first switch 130 and compare the indication to a reference, such as a reference current and adjust a current limit threshold based on the comparison.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Kotikalapoodi and Yen and incorporate the current limit control by sampling the inductor current during the on/off time of the first switch by Shao. The advantage of this design is to reduce switching power loss and improve accuracy of average current of the inductor to limit current in the converter.
Regarding claim 5, 17, and 26, Kotikalapoodi, Yen and Shao disclose the switched capacitor converter control circuit/method of claims 1/13/22, wherein the current sense circuit samples the first inductor current further during the first switch is operated at OFF state for output current limit control for an output current flowing to the second voltage (Shao par [0007]; par [0027]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kim et al. (US 11063516 B1) - power converter with four power switches and a current sensing circuit
Lidsky (US 20200218301 A1) - power converter with four power switches and a current sensing circuit
Yan (US 11489445 B2) - switching converter circuit with inductor current sensing for current mode control of pulse width modulation (PWM), for fault protection/overcurrent protection, and load current limiting
Lee et al. (US 20230155507 A1) - bidirectional switching converter including first to fourth switching elements connected in series, an inductor connected to a third switching element, and a capacitor connected to a second switching element and the third switching element, and a controller configured to generate, a first PWM signal and a second PWM signal based on current sensor that senses the inductor current IL
Ogata (US 20240305196 A1) - DC-DC converter with inductor current sensing
Pagano (US 8129953 B2) - DC-DC converter with inductor current sensing
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/LAUREN ASHLEY SHAW/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
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