DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor Package with Second Lead Frame Comprising a Hole that Overlaps the Second Contacting Portion.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Meguro (US 2009/0236721).
Regarding Claim 1, Meguro discloses a semiconductor package (semiconductor package 20: 20A, 20B, 20C and flip chips 21 [00043] Fig 1), comprising:
a first lead frame (third lead frame 23c [0045] Fig 1) and a second lead frame (first lead frame 23a [0044] Fig 1) that face each other; and
a semiconductor element (flip chip 21 and package 20A-C [0043] Fig 1) that is disposed between the first lead frame (23c Fig 1) and the second lead frame (23a Fig 1),
wherein the semiconductor element (21 Fig 1) is connected to the first lead frame (23c Fig 1) through a first contacting portion (wiring portions 11 [0041] Fig 1), and is connected to the second lead frame (23a Fig 1) through a second contacting portion (metal bumps 22 [0042] Fig 1), and
wherein the second lead frame (23a Fig 1) comprises a hole (through holes 26 [0044] Fig 1) that overlaps the second contacting portion (22 Fig 1).
Allowable Subject Matter
Claims 15-20 are allowable.
Regarding Claim 15, Meguro discloses a semiconductor package (semiconductor package 20: 20A, 20B, 20C and flip chips 21 [00043] Fig 1), comprising:
a first lead frame (third lead frame 23c [0045] Fig 1) comprising:
a first frame portion (shown in annotated Fig 1) on which a semiconductor element (flip chip 21 and package 20A-C [0043] Fig 1) is mounted,
a second frame portion (shown in annotated Fig 1) that is spaced apart from the first frame portion (shown in annotated Fig 1), is configured to receive a first signal from an external source, and is disposed in a nonoverlapping manner with regard to the semiconductor element (flip chip 21 and package 20A-C [0043] Fig 1), and
a third frame portion (shown in annotated Fig 1) that is spaced apart from the second frame portion (shown in annotated Fig 1) and is disposed in a nonoverlapping manner with regard to the semiconductor element (flip chip 21 and package 20A-C [0043] Fig 1);
a second lead frame (first lead frame 23a [0044] Fig 1) that faces the first lead frame (third lead frame 23c [0045] Fig 1);
a contacting portion (metal bumps 22 [0042] Fig 1) that is disposed between the second frame portion (shown in annotated Fig 1) and the second lead frame (23a Fig 1) and is configured to have conductivity.
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The reason for the indication of allowability of Claim 15 is the inclusion of
a spacer disposed between the third frame portion and the second lead frame.
Specifically, the prior art reference Meguro does not disclose this claim limitation and further should another reference be found that discloses a spacer, it would not be obvious to a person of ordinary skill in the art to combine the references and modify Meguro to include this feature.
It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Claims 2-12 and 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 2;
The reason for the indication of allowability of Claim 2 is the inclusion of
wherein the second lead frame comprises a plurality of protrusions that protrude toward the semiconductor element.
Specifically, the prior art reference Meguro does not disclose these protrusions as shown in Fig 2 of the instant application and further should another reference be found that discloses a spacer, it would not be obvious to a person of ordinary skill in the art to combine the references and modify Meguro to include this feature.
It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Claims 3-12 would be allowable based on their dependency on Claim 2.
Claim 13:
Regarding Claim 13, Meguro discloses
wherein the first lead frame (third lead frame 23c [0045] Fig 1) comprises: a first frame portion (shown in annotated Fig 1) on which the semiconductor element (flip chip 21 and package 20A-C [0043] Fig 1) is mounted, a second frame portion (shown in annotated Fig 1) that is spaced apart from the first frame portion (shown in annotated Fig 1), is configured to receive a first signal from an external source, and is disposed in a nonoverlapping manner with regard to the semiconductor element (flip chip 21 and package 20A-C [0043] Fig 1), and a third frame portion (shown in annotated Fig 1) that is spaced apart from the second frame portion (shown in annotated Fig 1), and is disposed in a nonoverlapping manner with regard to the semiconductor element (flip chip 21 and package 20A-C [0043] Fig 1).
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The reason for the indication of allowability of Claim 13 is the inclusion of
wherein the semiconductor package further comprises: a third contacting portion disposed between the second lead frame and the semiconductor element, a fourth contacting portion disposed between the second frame portion and the second lead frame and configured to have conductivity, and a spacer disposed between the third frame portion and the second lead frame.
Specifically, the prior art reference Meguro does not disclose these claim limitations and further should another reference be found that discloses these limitations, it would not be obvious to a person of ordinary skill in the art to combine the references and modify Meguro to include this feature.
It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Claim 14 would be allowable based on its dependency on Claim 13.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Zhou et al (US 2020/0098671) which discloses a power module may include a plurality of leads coupled to a second side of the substrate and a molding compound over a portion of five or more surfaces of the substrate [0004], and Park et al (US 6677181) which discloses a stack package and method of manufacturing the same [column 1, lines 1-26].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID PAUL SEDOROOK whose telephone number is (571)272-4158. The examiner can normally be reached Monday - Friday 7:30 am -5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge can be reached on (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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