Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED OFFICE ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 2024-06-12 in compliance with the provisions of 37 CFR 1.97 has been considered by the examiner and made of record in the application file.
Claim Status
Claims 1-20 are pending in this Office Action. No claims have been allowed.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention
Claims 11, 12, 13, 14, 15, 16,17,18,19 and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claim 11
Claim 11 recites, in relevant part, “causing the optical transmitter to transmit a remote fault signal …”. However, claim 11 is a method claim and does not previously introduce an “optical transmitter.” Accordingly, the term “the optical transmitter” lacks antecedent basis and renders the scope of Claim 11 unclear.
See MPEP §2173.05(e) (Antecedent Basis) (noting that lack of antecedent basis may render a claim indefinite when the scope is unclear).
Additionally, claim 11 recites “receiving a disable signal identifying a first channel” after already reciting “a first channel” earlier in the claim, and therefore should be amended for consistency (e.g., “identifying the first channel”).
Regarding claims 12 -17
Claims 12–17 depend from Claim 11. Therefore, claims 12-17 are also indefinite under 35 U.S.C. §112(b) because they incorporate the indefiniteness of Claim 11.
Regarding claim 18
Claim 18 recites, in relevant part, “cause the optical transmitter to transmit the modified multiplexed signal to the remote device over the optical link.” However, claim 18 previously introduces a “second optical communication device” and does not introduce a “remote device.” Thus, the term “the remote device” lacks antecedent basis (or is at least ambiguous as to whether it is the “second optical communication device”), rendering the scope of Claim 18 unclear. See MPEP §2173.05(e) (Antecedent Basis).
Regarding claims 19-20
Claims 19–20 depend from Claim 18. Therefore, claims 19-20 are also indefinite under 35 U.S.C. §112(b) because they incorporate the indefiniteness of Claim 18.
Claim Rejections – 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for the obviousness rejections set forth in this Office Action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
As reiterated by the Supreme Court in KSR, and as set forth in MPEP 2141 (R-01.2024), II, the factual inquiries of Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), applied for establishing a background for determining obviousness under 35 U.S.C. §103, are summarized as follows:
Determining the scope and content of the prior art;
Ascertaining the differences between the prior art and the claims at issue;
Resolving the level of ordinary skill in the pertinent art; and
Considering objective evidence indicative of obviousness or non-obviousness, if present.
This application currently names joint inventors. In considering patentability of the claims, the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 C.F.R. § 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. § 102(b)(2)(C) for any potential 35 U.S.C. § 102(a)(2) prior art against the later invention.
Claims 1,4,7,8 ,9,10,11 and 17 are rejected under 35 U.S.C. §103 as being unpatentable over Florit et al. (WO 2017/134419 A1) in view of Coli et al. (US 10,419,116 B2) and OIF-CMIS-05.2 and further in view of Xilinx PG292 (v2.6) and Lin et al. (US 9,001,846 B2).
Claim 1
Florit teaches multiplexing of words across lanes in a multi-lane link and dynamically updating lane active status while leaving other lanes unchanged, “first data interface providing a first channel, one or more additional data interfaces providing one or more additional channels, a multiplexer configured to generate a multiplexed signal encoding the first channel”, “Figure 3 is a conceptual diagram illustrating the use of each type of word described herein and how they are multiplexed. Figure 4 shows examples of how specific control words can be defined to implement the Align and Active words in accordance with an embodiment of the present invention. [Florit, Brief description of drawings] ……………...In conventional approaches such as Rapid 10 and PCI Express the lane status are not independent. In such approaches, one end of the link decides a configuration and tries to start all lanes with this configuration. The other end does the same, and both ends receive the information of the configuration that the other end is using. If an end determines that the configuration does not match, it restarts everything again with a new configuration that it is more likely to match the other side. Thus, the link is reinitialised by resetting all lanes, not maintaining bit or symbol synchronisation. This system does not support changes in configuration when the system is initializing. Examples of a change of configuration are when a user disables a lane or a lane stops working, as described with reference to Figure 2. Figure 3 is a conceptual diagram illustrating the use of each type of data unit described herein and how they are multiplexed. Lanes 302 send information in a multiple of a data unit called a word. Different types of words are now described. Data words 304 are generated by the application 306 and carry user data content. Control words 308 are generated by an arbitrary communication protocol 310. The protocol 310 selects (dotted line) data or control words to be output from the multiplexer 312. Align and Active words 314 are control words related to the link status and lane status 316. The link status is related to the multi-lane alignment mechanism described with reference to Figure 5. Align and Active words 314 which convey the status of each lane are selected for output by the multiplexer 318 depending on the link status 320. Align and Active words 314 multiplexed with Data words 304 and other Control words 308 are distributed by multi-lane distribution 322 over the N lanes 302 following the lane ordering defined by the lane numbers 0 ... N-1.” [Florit, Description of embodiments].
Florit further teaches changing a specific lane status to inactive while leaving other lanes unchanged and adapting to link configuration changes using remaining lanes/channels, “cause the multiplexer to generate a modified multiplexed signal encoding the one or more additional channels and not the first channel; and cause the optical transmitter to transmit the modified multiplexed signal to the remote device over the optical link”, “………….Preferably, the multi-lane communication interface further comprises logic to, upon detection of the change in lane status by receiving the far-end lane-status control word sent from the far-end interface, update the active status of a near-end lane accordingly, while leaving the lane status of other lanes unchanged. Preferably, the multi-lane communication interface comprises logic to update the active status of the near-end lane by disabling a near-end lane that is not active at the far end. Preferably, the multi-lane communication interface further comprises logic to detect the change in lane status by detecting data errors or configuration changes at the near end, and upon detection of the change in lane status, update the active status of a near-end lane accordingly, while leaving the lane status of other lanes unchanged. Preferably, the multi-lane communication interface further comprises logic to stop passing received data words to a data link layer of the link while the near-end is not ready to send data words……………………………….Preferably, the multi-lane communication interface further comprises logic to determine that the near end is not ready to send data words if an error is detected in a period of time after it is determined that the near end is ready to send data words, the period of time being the round-trip delay of the link including any processing delay. Preferably, in step (c) the near-end lane-alignment signals sent to the far end include information on the lane transmit status at the near end. Preferably, the link has an arbitrary number of physical lanes that comprise both unidirectional and bidirectional lanes. Preferably, the multi-lane communication interface further comprises logic to detect, for each lane, if the far-end interface has disabled a transmit or receive driver, so a respective lane becomes unidirectional, wherein the multi-lane communication interface is operable to adapt to a dynamic configuration change of the link, using remaining bandwidth of the link. Preferably, data words that cannot be sent upon detection of the change in lane status and while the near end is not ready to send data words are stored in the multi-lane communication interface, to prevent an external data source from detecting that data words cannot be sent by the multi-lane communication interface……………...” [Florit, Summary of invention], “…………...This enables a unidirectional transmit-only lane to reach the Active state. It also allows to detect when, at the far end, the lane is set as a unidirectional receive-only lane for power saving reasons. In this case, the lane is set as a transmit-only lane if it was previously not set as a such. A lane in the active state can exit this state when one or more of the following conditions are fulfilled: • When the lane is disabled by the user; • When the lane is set to be able to receive data but the receiver driver indicates that there is not a valid signal, or the measured Bit Error Rate of this lane is too high. The Bit Error Rate can be measured, for example, by counting the number of 881 OB decoding errors; • When the lane receives words indicating that the other end is going to disable the lane because it wants to save power or because it is detecting too many errors and cannot receive data correctly; or • When the lane is set as a unidirectional transmit-only lane and other lanes of the link have received the information that, at the far end of the link, this lane is not in the Active state. If one lane fails due to errors received on that lane, only that lane status is updated, while leaving the lane status of other lanes unchanged. This is different from other approaches, in which if there are errors in one lane, it causes the whole link to restart all lanes. A multi-lane link is made up of two or more lanes. Each lane of multi-lane link has a lane number assigned, starting with value O up to the N-1 value, where N is the number of lanes that the link has…………………” [Florit, Description of embodiments].
Florit does not expressly teach optical modules managed by a network device/host (network management), including sending instructions to enable/disable a transmitter and to tune a transmission wavelength However, in an analogous art, Coli teaches optical modules managed by a network device/host (network management), including sending instructions to enable/disable a transmitter and to tune a transmission wavelength “an optical transmitter configured to transmit the multiplexed signal over an optical link to a remote device”, “…………………………. As used herein, the term "module" may refer to any physical device able to transmit and/or receive optical signals over a network. Examples of modules may include any variant of transceivers, single- or multi-lane active optical cables, transponders, board mounted optics, etc. As used herein, the term "host" may refer to a network device such as a switch, a router, a muxponder or another multiplexing device, etc. Stated another way, the host may be a network device that receives and/or processes data from customers, for network management, etc. The module may 20 be the physical device that receives electrical signals from the host and converts those signals into optical signals to be transmitted across an optical fiber, or receives optical signals from across an optical fiber and converts the optical signals into electrical signals for the host………………...” [Coli, Column 3].
Coli does not expressly teach host control to disable/enable individual Tx lanes (OutputDisableTx<N>) and DataPath disable logic, while allowing selective reconfiguration without affecting other Data Paths However, in an analogous art, CMIS teaches host control to disable/enable individual Tx lanes (OutputDisableTx<N>) and DataPath disable logic, while allowing selective reconfiguration without affecting other Data Paths, “Controller receives a disable signal identifying the first channel” , “disable the first channel”, “…………DPDeactivateS (DataPathDeactivateS) The DPDeactivateS (DataPathDeactivateS) transition signal is defined by the logic equation DPDeactivateS = DPReDeinitS OR DPTxDisableT OR DPTxForceSquelchT (Eq. 6-12) where DPTxDisableT = OutputDisableTx<N> (Eq. 6-13) OR OutputDisableTx<N+1> OR OutputDisableTx<N+M-1> DPTxForceSquelchT = OutputSquelchForceTx<N> (Eq. 6-14) OR OutputSquelchForceTx<N+1> OR OutputSquelchForceTx<N+M-1> N = first media lane in the Data Path M = number of media lanes in the Data Path 1 Note: When in DPActivated or DPTxTurnOn states, setting OutputDisableTx or OutputSquelchForceTx on one media lane of a Data Path intentionally causes that entire Data Path to transition to DPInitialized via DPTxTurnOff. Although some media lanes of the Data Path may continue to be operational (i.e. media lanes with output neither disabled nor squelched), as long as some media lanes are not operational, the Data Path as a whole is considered not activated…………….” [CMIS, 6.3.3.1], .…………...The Rx output squelch function is controlled only by a module-internal squelch controller (if supported) that 2 automatically activates the output squelch function when no suitable media side Rx input signal is available 3 to be forwarded on the host side output. Note: A single Rx input lane may feed more than one Rx output lane, and the data transmitted on one Rx output lane may originate from more than one Rx input lane. The internal controller squelches an Rx electrical output lane until all associated Rx input lanes have detected a valid input signal and all associated internal resources are fully initialized and capable of forwarding a valid stable signal, in order to avoid link flaps. The automatic Rx output squelch controller itself (if supported) can be enabled or disabled by the host. This section lists the specific controls for the purposes discussed above. Tx Output Controls The host can disable and un-disable Tx output lane N using OutputDisableTx<N>. The host can force and unforce squelching of Tx output lane N using OutputSquelchForceTx<N>. The host can disable or enable the internal squelch controller for lane N using AutoSquelchDisableTx<N>. 15 Tx Input Controls The host can switch the host side input signal polarity of lane N using InputPolarityFlipTx<N>. The host can freeze the host side input equalizer adaptation for lane N using AdaptiveInputEqFreezeTx<N>. The host can store the current equalizer setting of lane N for later recall using AdaptiveInputEqStoreTx<N>. Rx Output Controls The host can disable and un-disable Rx output lane N using OutputDisableRx<N>. Note: There is no OutputSquelchForceRx<N> corresponding to OutputSquelchForceTx<N>. The host can switch the output signal polarity of lane N using OutputPolarityFlipRx<N>. The host can disable or enable the internal squelch controller for lane N using AutoSquelchDisableRx<N>………... Note: It is recommended that hosts configure the same auto-squelch disable settings for all lanes (of one 25 direction) within a Data Path (media lanes for Tx and host lanes for Rx), otherwise behavior may be unexpected, [CMIS, 8.9.2].
CMIS further teaches cause the multiplexer to generate a modified multiplexed signal encoding the one or more additional channels and not the first channel and cause the optical transmitter to transmit the modified multiplexed signal to the remote device over the optical link, “DPActivated State (Operational) The DPActivated (DataPathActivated) state is a steady state. In this state Data Paths are fully operational (initialized and ready to transmit traffic). Autonomous Behavior On entry to this state, the module updates the Data Path state register (see Table 8-76) and the Data Path State Changed Flag (Table 8-80) for all lanes in the Data Path according to the rules described in section 6.3.3.3. 31 All Tx outputs associated with the Data Path in DPActivated are unmuted and operational throughout the state. Note: While operational, Tx outputs may still be auto squelched, overriding the host configured output status. Reactive Behavior (on Host Actions) The module reacts to all events at all interfaces in this DPSM state of providing regular transmission service for the fully operational Data Path Exit The Data Path state transitions to DPTxTurnOff if the host causes the DPDeactivateS transition signal to become TRUE for that Data Path. One way for the DPDeactivateS transition signal to become TRUE is if the host triggers the ApplyDPInit bits associated with the Data Path. The host may reconfigure one or more Data Paths while in DPActivated by a new Application in one of the Staged Control Sets and then using ApplyDPInit. The host shall set ApplyDPInit to the same value for all lanes in the Data Path being reinitialized. Note: When ApplyDPInit bits are triggered, the Data Path State Machine will transition through the DPTxTurnOff → DPInitialized → DPDeinit → DPDeactivated → DPInit → DPInitialized → DPTxTurnOn → DPActivated state sequence, reinitializing the new Data Path configuration in DPInit. Prior to triggering the ApplyDPInit bits for applicable lanes, the host shall provide a valid high-speed input signal at the required signaling rate and encoding type. The ApplyDPInit bits for all lanes in the Data Path shall be triggered with one register access. The host may request reinitialization of multiple Data Paths in the same register access. Data Paths excluded from the ApplyDPInit selector are not affected. Note: This selective control allows host reconfiguration of individual Data Paths without affecting the operation of other Data Paths in the module. The DPDeactivateS transition signal will also become TRUE if the host sets Tx Output Disable or Tx Force Output Squelch for any lane of the Data Path…….” [CMIS, 6.3.3.9].
CMIS does not expressly teach Ethernet PCS/MAC subsystem behavior for transmitting Remote Fault Indication (RFI) code words and detecting remote fault status However, in an analogous art, PG292 teaches Ethernet PCS/MAC subsystem behavior for transmitting Remote Fault Indication (RFI) code words and detecting remote fault status, and ties PCS operation to IEEE 802.3 Clause 49, “In response to receiving the disable signal cause the optical transmitter to transmit a remote fault signal to the remote device on the first channel of the multiplexed signal”, “………TX Path Control/Status/Statistics Signals, Table 59: TX Path Control/Status/Statistics Signals, ctl_tx_send_rfi_*, Size 1, I/O 1, Transmit Remote Fault Indication (RFI) code word. If this input is sampled as a 1, the TX path only transmits Remote Fault code words. This input should be set to 1 until the RX path is fully aligned and is ready to accept data from the link partner………” [PG292, AXI4-Stream User Interface Signals]
PG292 does not expressly teach MAC/PHY link-fault detection and generation, including identification of local vs remote faults and a link fault generator However, in an analogous art, Lin teaches MAC/PHY link-fault detection and generation, including identification of local vs remote faults and a link fault generator, “In response to receiving the disable signal cause the optical transmitter to transmit a remote fault signal to the remote device on the first channel of the multiplexed signal”, “………..In an example embodiment, the media-side MAC block 106 may receive signals, such as either packets or a link fault signal, at an input 602 from its PHY block 102. The mediaside MAC block 106 may include a fault detector 604, which may determine whether the signal is a regular packet or a link fault signal. The fault detector 604 may indicate whether the signal is a local fault, a remote fault, or neither, via control lines such as a local fault detect line 606 and/or a remote fault detect line 608. The ingress data pipeline 206 may be controlled by either the local fault detect line 606 and/or the remote fault detect line 608, such as via an inverter 610. If the fault detector 604 determines that the received signal is a regular packet, then the inverter 610, based on a signal received from the local fault detect line 606 and/or the remote fault detect line 608, may allow the ingress data pipeline 206 to process the packet as described above with reference to FI GS. 2 and 3. If the fault detector 604 determines that the received signal is a fault signal, then the inverter 610 may prevent the ingress data pipeline 206 from processing the received signal; the ingress data pipeline 206 may, for example, discard the packet……….” [Lin, Column 8].
A person of ordinary skill in the art (POSITA) at the time of the invention would have been motivated to combine Florit’s multi-lane architecture for multiplexing words across lanes and dynamically disabling/updating the status of only the affected lane (while leaving other lanes unchanged and continuing operation using remaining bandwidth) with Coli’s host-managed optical module/transceiver environment, CMIS’s standardized per-lane transmit disable / datapath deactivation and selective datapath reinitialization controls, and PG292/Lin’s standardized link-fault generation and Remote Fault Indication (RFI) signaling, because these references address complementary portions of the same real engineering problem: how to gracefully degrade a multi-lane optical link when a particular lane/channel must be disabled, while ensuring the far-end receives a clear, standardized fault indication and the system continues transmitting over the remaining lanes without restarting the entire link.
In particular, Florit already teaches the foundational behavior required by Claim 1—namely multiplexing words for a multi-lane link and adapting to configuration changes such as when a user disables a lane or a lane stops working, by updating only that lane’s active state while leaving other lanes unchanged. However, Florit by itself does not focus on a standardized host/module control interface for lane disable nor on Ethernet-style Remote Fault messaging that a far-end device can interpret consistently across vendors. In real optical Ethernet deployments, a POSITA would recognize strong design incentives and market pressure to implement lane disable and fault signaling using standardized mechanisms to avoid link flaps, minimize downtime, and ensure interoperability between the local device and a heterogeneous population of remote devices.
Accordingly, a POSITA would look to Coli for the conventional implementation context in which a host/network device manages an optical module and issues control instructions to the transmitter (i.e., the practical environment for receiving a “disable signal”). A POSITA would then implement the “disable first channel” operation using CMIS, because CMIS provides an explicit, standardized control framework that allows a host to disable a specific Tx lane/data path and to selectively reinitialize/reconfigure datapaths without affecting other datapaths, which directly supports Florit’s goal of changing only the affected lane while leaving the remainder of the link operational. This is a predictable substitution of one known control mechanism (standard module datapath/lane disable and selective reinit) to achieve a known objective (selective lane/channel disable with continued operation on remaining channels).
Further, a POSITA would incorporate PG292’s Ethernet PCS behavior for transmitting Remote Fault Indication (RFI) code words (and Lin’s link fault detection/generation concepts distinguishing local vs remote faults) into the Florit/CMIS multi-lane system because Ethernet Remote Fault signaling is a well-known and widely implemented mechanism for ensuring the remote device receives an unambiguous, standardized indication of link impairment. Without Remote Fault signaling, disabling a lane locally could appear at the far end as an unexplained impairment, leading to non-deterministic recovery behavior or unnecessary re-training/restart. Embedding/associating the Remote Fault signal with the identified channel is therefore an obvious and predictable design choice to ensure the far end can promptly and consistently interpret the lane/channel disable condition.
The proposed combination would have yielded predictable results with a reasonable expectation of success: (1) the host/controller receives a disable request in the standard host-managed module context (Coli), (2) the controller disables the identified lane/data path using standardized per-lane disable and selective datapath control (CMIS) while leaving other lanes/datapaths unaffected, consistent with Florit’s dynamic lane status behavior, (3) the controller causes standardized Remote Fault signaling (PG292/Lin) to be transmitted so the remote device receives an explicit fault indication associated with the affected channel, and (4) the multiplexed transmission naturally becomes a “modified multiplexed signal” that excludes the disabled channel while continuing to carry the remaining channels over the same optical link (Florit + CMIS selective datapath behavior). Importantly, this combination does not change the principle of operation of any reference; it merely uses standardized control and standardized fault signaling in a multi-lane multiplexing environment to achieve the well-recognized goals of fault isolation, graceful degradation, interoperability, and reduced recovery time, which are conventional objectives in high-speed optical multi-lane systems.
Claim 4
With respect to claim 4, all claim limitations of claim 1 are taught by Florit, Coli, CMIS, PG292 and Lin except wherein the remote fault signal is processed by the remote device without the remote device implementing CMIS 5.2. However, within analogous art, PG292 teaches that PCS operation (including block lock) is defined by IEEE 802.3 Clause 49 and provides remote-fault indication status independent of CMIS management, “the remote fault signal is configured to be processed by the remote device without the remote device implementing a CMIS 5.2 standard.”, “…………. the features of the 1G/10G/25G Ethernet Subsystem dynamically switching PCS/PMA and MAC core. The 10G/25G Ethernet Subsystem is defined by the 25G Ethernet Consortium. 10G PCS functionality is defined by IEEE Standard 802.3, 2015, Clause 49, Physical Coding Sublayer (PCS) for 64B/66B, type 10GBASE-R. 1G PCS functionality is defined in Clause 36. For 25G operation, clock frequencies are increased to provide a serial interface operating at 25.78125 Gb/s to leverage the latest high-speed serial transceivers. The low latency design is optimized for UltraScale+™ architecture devices………….” [PG292, Subsystem Overview] …………………………. Table 13: AXI4-Stream Interface–RX Path Control/Status Signals (cont'd)…………. stat_rx_block_lock1…… I/O is 0……... Block lock status. A value of 1 indicates that block lock is achieved as defined in Clause 49.2.14 and MDIO register 3.32.0 This output is level sensitive……… Clock Domain is rx_clk_out………”, [ PG292, Table 13, P.24].
Accordingly, a POSITA would have found it obvious for the remote device to process the remote fault signal using standard PCS remote-fault semantics (e.g., Clause 49 remote-fault indication) for interoperability and backward compatibility independent of any CMIS 5.2 module-management implementation.
Claim 7
With respect to claim 7, all claim limitations of claim 1 are taught by Florit, Coli, CMIS, PG292 and Lin except wherein the disable signal is received from a network management system. However, within analogous art, Coli teaches the host as a network device used for network management and controlling a module, “the disable signal is received from a network management system”, “………...A system may include a first module at a far end, and an optical fiber coupled to the first module. The system may also include a second module at a near end that is configured to generate and transmit instructions to the first module to control operation of the first module…………” [Coli, Abstract], “………. As used herein, the term "module" may refer to any physical device able to transmit and/or receive optical signals over a network. Examples of modules may include any variant of transceivers, single- or multi-lane active optical cables, transponders, board mounted optics, etc. As used herein, the term "host" may refer to a network device such as a switch, a router, a muxponder or another multiplexing device, etc. Stated another way, the host may be a network device that receives and/or processes data from customers, for network management, etc. The module may be the physical device that receives electrical signals from the host and converts those signals into optical signals to be transmitted across an optical fiber, or receives optical signals from across an optical fiber and converts the optical signals into electrical signals for the host. In some situations, the first host 111 may not have direct access to hardware and/or software of the second module 153 and/or the third module 156. Instead, the first host 111 may generate a message that is provided to the first module 110, converted to an optical signal by the first module 110, transmitted to the second module 153 and/or the third module 156, the optical signal converted to an electrical signal by the second module 153 and/or the third module 156, and the electrical signal provided to the second host 151. The second host 151 may communicate the message to the second module 153 and/or the third module 156. In some embodiments of the present disclosure, the first module 110 may communicate directly with the second module 153 and/or the third module 156. For example, the
first module 110 may communicate instructions to perform certain tasks or may request certain data directly from the second module 153 and/or the third module 156, without having to send such instructions to the second host 151 to be communicated to the second module 153 and/or the third module 156. In these and other embodiments, such instructions may be communicated at a physical layer, or in terms of the Open Systems Interconnection (OSI) model, at Layer 1…………” [Coli, Column3].
A POSITA would have understood such management instructions to be generated under control of a network management function (NMS/controller) in a coherent optical network, and thus the disable signal being received from an NMS would have been an obvious design choice.
Accordingly, receiving the disable signal from a network management system (via the host) is taught/obvious.
Claim 8
With respect to claim 8, all claim limitations of claim 1 are taught by Florit, Coli, CMIS, PG292 and Lin except wherein the first data interface comprises a medium access control (MAC) associated with the first channel. However, within analogous art, Lin teaches a MAC/PHY architecture and MAC-level link-fault signaling, “the first data interface comprises a medium access control (MAC) associated with the first channel”, “According to one example embodiment, an apparatus may include a media-side physical layer (PHY) block configured to receive a received signal via at least one medium, decode the received signal into data, and send the data to a media-side medium access control (MAC) block, the media-side MAC block configured to receive the data from the media-side PHY layer block, determine a time of receipt of the data, prevent a system-side MAC block from forwarding the data until a predetermined delay after the time of receipt, perform MAC functions on the data, and send the data to the system-side MAC block, the system side MAC block configured to receive the data and the control time from the media-side MAC block and send the data to a system-side PHY block after the predetermined delay based on signals received from the media-side MAC block, and the system-side PHY block configured to receive the data from the system-side MAC block, encode the data into a transmitted signal, and transmit the transmitted signal to a computing system” [Lin, Abstract], …………In an example embodiment, the media-side MAC block may include a link fault detector, which may recognize a media-side link fault signal received from the media-side PHY block 102. In response to recognizing the media-side link fault signal, the media-side MAC block 106 may assert a MAC-level link fault signal to the system-side MAC block 108. In this example, the system-side MAC block 108 may include a link fault generator. The link fault generator may generate and send a system-side link fault signal to the system- side PHY block 104 in response to receiving the MAClevel link fault signal………. [Lin, Column 3].
Therefore, implementing the first data interface as a MAC associated with a channel is taught/obvious in view of Lin’s MAC/PHY architecture.
Claim 9
With respect to claim 9, all claim limitations of claim 1 are taught by Florit, Coli, CMIS, PG292 and Lin except wherein the controller causes the first data interface to generate the remote fault signal and the multiplexer incorporates the remote fault signal on the first channel, while excluding that channel from the modified multiplexed signal. However, within analogous art Florit teaches multiplexing across lanes/channels “the multiplexer is configured to receive the remote fault signal and to generate the multiplexed signal to incorporate the remote fault signal on the first channel of the multiplexed signal”, “………. The other end does the same, and both ends receive the information of the configuration that the other end is using. If an end determines that the configuration does not match, it restarts everything again with a new configuration that it is more likely to match the other side. Thus the link is reinitialised by resetting all lanes, not maintaining bit or symbol synchronisation. This system does not support changes in configuration when the system is initializing. Examples of a change of configuration are when a user disables a lane or a lane stops working, as described with reference to Figure 2. Figure 3 is a conceptual diagram illustrating the use of each type of data unit described herein and how they are multiplexed……” [ Florit, Description of embodiments].
Florit further teaches transmission over a fiber-optic link “the optical transmitter is configured to transmit the multiplexed signal, incorporating the remote fault signal, to the remote device on the first channel” “…………The Physical Layer 114 serialises the BB/1 OB symbols and sends them over the physical medium via a Physical Interface 116. In the receiver the Physical Layer recovers the clock and data from the serial bit stream, determines the symbol boundaries and recovers the BB/1 OB symbols. Both electrical cables and fibre-optic cables are supported by SpaceFibre……” [Florit, Background Art].
In an analogous art, Florit teaches leaving other lane status unchanged while one lane becomes inactive “the multiplexer is configured, in response to the disabling of the first channel, to generate the modified multiplexed signal encoding the one or more additional channels and not the first channel” “…………..A lane in the active state can exit this state when one or more of the following conditions are fulfilled When the lane is disabled by the user; When the lane is set to be able to receive data but the receiver driver indicates that there is not a valid signal, or the measured Bit Error Rate of this lane is too high. The Bit Error Rate can be measured, for example, by counting the number of 881 OB decoding errors; When the lane receives words indicating that the other end is going to disable the lane because it wants to save power or because it is detecting too many errors and cannot receive data correctly; or When the lane is set as a unidirectional transmit-only lane and other lanes of the link have received the information that, at the far end of the link, this lane is not in the Active state……….” [Florit, Description of embodiments].
Further, Florit teaches optical link transmission “the optical transmitter is configured to transmit the modified multiplexed signal to the remote device over the optical link” “…………. In the receiver the Physical Layer recovers the clock and data from the serial bit stream, determines the symbol boundaries and recovers the BB/1 OB symbols. Both electrical cables and fibre-optic cables…………” [Florit, Background Art].
Florit does not expressly teach selective control so other Data Paths remain unaffected However, in an analogous art, CMIS teaches selective control so other Data Paths remain unaffected, “the multiplexer is configured, in response to the disabling of the first channel, to generate the modified multiplexed signal encoding the one or more additional channels and not the first channel” “………. The ApplyDPInit bits for all lanes in the Data Path shall be triggered with one register access. The host may request reinitialization of multiple Data Paths in the same register access. Data Paths excluded from the ApplyDPInit selector are not affected…………” [CMIS, 6.3.3.9 DPActivated State (Operational)].
CMIS further supports selective DataPath control consistent with continued transmission on remaining lanes, “the optical transmitter is configured to transmit the modified multiplexed signal to the remote device over the optical link” “……. The host may request reinitialization of multiple Data Paths in the same register access……..” [CMIS, 6.3.3.9 DPActivated State].
CMIS does not expressly teach the RFI code word as the remote-fault signal transmitted on the TX path However, in an analogous art, PG292 teaches the RFI code word as the remote-fault signal transmitted on the TX path, “the controller is configured to receiving the disable signal, cause the first data interface to generate the remote fault signal” “…………TX Path Control/Status/Statistics Signals Table 59: TX Path Control/Status/Statistic Signals, Name ctl_tx_send_rfi_*, Size 1, I/O 1, Description Transmit Remote Fault Indication (RFI) code word. If this input is sampled as a 1, the TX pat only transmits Remote Fault code words. This input should be set to 1 until the RX path is fully aligned and is ready to accept data from the link partner………….” [PG292, Table 59].
PG292 further teaches RFI code words carried on a lane/channel stream, “the multiplexer is configured to receive the remote fault signal and to generate the multiplexed signal to incorporate the remote fault signal on the first channel of the multiplexed signal” “………Description Transmit Remote Fault Indication (RFI) code word. If this input is sampled as a 1, the TX pat only transmits Remote Fault code words. This input should be set to 1 until the RX path is fully aligned and is ready to accept data from the link partner………….” [PG292, Table 59].
In an analogous art, PG292 teaches transmitting the RFI (remote-fault) code word toward the remote peer, “the optical transmitter is configured to transmit the multiplexed signal, incorporating the remote fault signal, to the remote device on the first channel” “………This input should be set to 1 until the RX path is fully aligned and is ready to accept data from the link partner………….” [PG292, Table 59].
PG292 does not expressly teach a link-fault generator producing link fault indications However, in an analogous art, Lin teaches a link-fault generator producing link fault indications, “the controller is configured to receiving the disable signal, cause the first data interface to generate the remote fault signal” “……. In an example embodiment, the media-side MAC block may include a link fault detector, which may recognize a media-side link fault signal received from the media-side PHY block 102. In response to recognizing the media-side link fault signal, the media-side MAC block 106 may assert a MAC-level link fault signal to the system-side MAC block 108. In this example, the system-side MAC block 108 may include a link fault generator. The link fault generator may generate and send a system-side link fault signal to the system- side PHY block 104 in response to receiving the MAClevel link fault signal………...” [Lin, Column 3].
A POSITA would generate standardized RFI fault code words at the channel interface and carry them in the identified channel stream so the peer detects the affected channel using PCS semantics (predictable fault isolation).
Claim 10
With respect to claim 10, all claim limitations of claim 9 are taught by Florit, Coli, CMIS, PG292 and Lin except wherein the controller simulates a local fault, and the first data interface generates the remote fault signal in response to the simulated local fault. However, within analogous art, PG292 teaches transmitting standardized RFI (remote-fault) code words once asserted, “the first data interface generating the remote fault signal in response to the simulation of the local fault” “…………TX Path Control/Status/Statistics Signals Table 59: TX Path Control/Status/Statistic Signals, Name ctl_tx_send_rfi_*, Size 1, I/O 1, Description Transmit Remote Fault Indication (RFI) code word. If this input is sampled as a 1, the TX pat only transmits Remote Fault code words. This input should be set to 1 until the RX path is fully aligned and is ready to accept data from the link partner………….” [PG292, Table 59].
PG292 does not expressly teach a link-fault generation responsive to fault conditions However, in an analogous art, Lin teaches link-fault generation responsive to fault conditions “the first data interface generating the remote fault signal in response to the simulation of the local fault” “……. In an example embodiment, the media-side MAC block may include a link fault detector, which may recognize a media-side link fault signal received from the media-side PHY block 102. In response to recognizing the media-side link fault signal, the media-side MAC block 106 may assert a MAC-level link fault signal to the system-side MAC block 108. In this example, the system-side MAC block 108 may include a link fault generator. The link fault generator may generate and send a system-side link fault signal to the system- side PHY block 104 in response to receiving the MAClevel link fault signal………...” [Lin, Column 3].
Lin further teaches a fault detector identifying local fault states; simulating/forcing the local-fault condition is within this fault-state framework, “the controller causing the first data interface to generate the remote fault signal, the controller causing the first data interface to simulate a local fault” “………..The mediaside MAC block 106 may include a fault detector 604, which may determine whether the signal is a regular packet or a link fault signal. The fault detector 604 may indicate whether the signal is a local fault, a remote fault, or neither, via control lines such as a local fault detect line 606 and/or a remote fault detect line 608…………” [Lin, Column 8].
A POSITA would simulate/assert a local fault to trigger standardized remote-fault signaling for diagnostics and rapid peer notification, a known link-management technique with predictable results.
Claim 11
Claim 11 recites a method corresponding to the apparatus of claim 1
Florit teaches multiplexed multi-lane transmission over a fiber-optic link with explicit lane/channel structure, “transmitting a multiplexed signal to a second optical communication device over an optical link, the multiplexed signal encoding a first channel provided by a first data interface and one or more additional channels” “…………The Physical Layer 114 serialises the BB/1 OB symbols and sends them over the physical medium via a Physical Interface 116. In the receiver the Physical Layer recovers the clock and data from the serial bit stream, determines the symbol boundaries and recovers the BB/1 OB symbols. Both electrical cables and fibre-optic cables are supported by SpaceFibre……” [Florit, Background Art], “………. The other end does the same, and both ends receive the information of the configuration that the other end is using. If an end determines that the configuration does not match, it restarts everything again with a new configuration that it is more likely to match the other side. Thus the link is reinitialised by resetting all lanes, not maintaining bit or symbol synchronisation. This system does not support changes in configuration when the system is initializing. Examples of a change of configuration are when a user disables a lane or a lane stops working, as described with reference to Figure 2. Figure 3 is a conceptual diagram illustrating the use of each type of data unit described herein and how they are multiplexed……” [ Florit, Description of embodiments].
Florit further teaches leaving other lanes unchanged while one lane becomes inactive, “generating a modified multiplexed signal encoding the one or more additional channels and not the first channel” “…………..A lane in the active state can exit this state when one or more of the following conditions are fulfilled When the lane is disabled by the user; When the lane is set to be able to receive data but the receiver driver indicates that there is not a valid signal, or the measured Bit Error Rate of this lane is too high. The Bit Error Rate can be measured, for example, by counting the number of 881 OB decoding errors; When the lane receives words indicating that the other end is going to disable the lane because it wants to save power or because it is detecting too many errors and cannot receive data correctly; or When the lane is set as a unidirectional transmit-only lane and other lanes of the link have received the information that, at the far end of the link, this lane is not in the Active state If one lane fails due to errors received on that lane, only that lane status is updated,cwhile leaving the lane status of other lanes unchanged. This is different from other approaches, in which if there are errors in one lane, it causes the whole link to restart all lanes.……….” [Florit, Description of embodiments].
In an analogous art, Florit teaches continued optical transmission over the fiber link “transmitting the modified multiplexed signal to the second optical communication device over the optical link” “………...In the receiver the Physical Layer recovers the clock and data from the serial bit stream, determines the symbol boundaries and recovers the BB/1 OB symbols. Both electrical cables and fibre-optic cables…………” [Florit, Background Art].
Florit does not expressly teach host-provided OutputDisableTx<N> which identifies the specific lane/channel to disable However, in an analogous art, CMIS teaches host-provided OutputDisableTx<N> which identifies the specific lane/channel to disable, “receiving a disable signal identifying a first channel” “…………Control of Rx Output Squelching Function The Rx output squelch function is controlled only by a module-internal squelch controller (if supported) that automatically activates the output squelch function when no suitable media side Rx input signal is available to be forwarded on the host side output. Note: A single Rx input lane may feed more than one Rx output lane, and the data transmitted on one Rx output lane may originate from more than one Rx input lane. The internal controller squelches an Rx electrical output lane until all associated Rx input lanes have detected a valid input signal and all associated internal resources are fully initialized and capable of forwarding a valid stable signal, in order to avoid link flaps. The automatic Rx output squelch controller itself (if supported) can be enabled or disabled by the host. 8.9.2.3 Lane-specific Tx and Rx Control Fields This section lists the specific controls for the purposes discussed above. Tx Output Controls The host can disable and un-disable Tx output lane N using OutputDisableTx<N> The host can force and unforce squelching of Tx output lane N using OutputSquelchForceTx<N>. The host can disable or enable the internal squelch controller for lane N using AutoSquelchDisableTx<N>………….” [CMIS, 8.9.2.2 Rx Output Muting Functions and Their Control]
CMIS further teaches per-lane disable and DataPath TX disable logic responsive to OutputDisableTx bits, “disabling the first channel” “………eactivateS 1 The DPDeactivateS DataPathDeactivateS transition signal is defined by the logic equation 2 DPDeactivateS DPReDeinitS OR DPTxDisableT OR DPTxForceSquelchT Eq 6-12 3 where 4” (OIF-CMIS-05.2, Eq. 6-13, PDF p.76) The DPDeinitS transition signal can also be represented by the logic equation DPDeinitS = ( NOT ModuleReadyT ) OR LowPwrS OR DPDeinitT (Eq. 6-6) where ModuleReadyT = (ModuleState = ModuleReady) (Eq. 6-7) DPDeinitT = DPDeinitLane<N> (Eq. 6-8) OR DPDeinitLane<N+1> 6 … OR DPDeinitLane<N+M-1> N = first host lane in the Data Path M = number of host lanes in the Data Path DPReDeinitS (DataPathReDeinitS) when SteppedConfigOnly = 0 The DPReDeinitS (DataPathReDeinitS) transition signal is defined using the truth table shown in Table 6-17 when the module supports intervention-free reconfiguration, which is advertised by SteppedConfigOnly = 0 (see Table 8-5)………….” [CMIS, 6.3.3.1]
In an analogous art, CMIS teaches selective control without affecting other Data Paths, “generating a modified multiplexed signal encoding the one or more additional channels and not the first channel” “………. The ApplyDPInit bits for all lanes in the Data Path shall be triggered with one register access. The host may request reinitialization of multiple Data Paths in the same register access. Data Paths excluded from the ApplyDPInit selector are not affected…………” [CMIS, 6.3.3.9 DPActivated State].
CMIS supports selective continuation on remaining Data Paths,” transmitting the modified multiplexed signal to the second optical communication device over the optical link” “………The host may request reinitialization of multiple Data Paths in the same register access. Data Paths excluded from the ApplyDPInit selector are not affected. Note: This selective control allows host reconfiguration of individual Data Paths without affecting the operation of other Data Paths in the module. The DPDeactivateS transition signal will also become TRUE if the host sets Tx Output Disable or Tx Force Output Squelch for any lane of the Data Path……...” [CMIS, 6.3.3.9]
CMIS does not expressly teach transmitting Remote Fault Indication (RFI) code words toward the peer as the remote-fault signal However, in an analogous art, PG292 teaches transmitting Remote Fault Indication (RFI) code words toward the peer as the remote-fault signal, “in response to receiving the disable signal, causing the optical transmitter to transmit a remote fault signal to the second optical communication device on the first channel of the multiplexed signal” “…………TX Path Control/Status/Statistics Signals Table 59: TX Path Control/Status/Statistic Signals, Name ctl_tx_send_rfi_*, Size 1, I/O 1, Description Transmit Remote Fault Indication (RFI) code word. If this input is sampled as a 1, the TX pat only transmits Remote Fault code words. This input should be set to 1 until the RX path is fully aligned and is ready to accept data from the link partner………….” [PG292, Table 59].
A POSITA would implement the method using standardized per-lane disable plus RFI signaling to obtain predictable graceful degradation and interoperable fault notification.
Claim 17
With respect to claim 17 all claim limitations of claim 11 are taught by Florit, Coli, CMIS, PG292 and Lin except wherein the first data interface comprises a MAC associated with the first channel. However, within analogous art, PG292 teaches an Ethernet subsystem including MAC + PCS/PMA functions, supporting implementing the channel interface as a MAC, “the first data interface comprises a medium access control (MAC) associated with the first channel” “………The Xilinx® 1G/10G/25G Switching Ethernet Subsystem includes MAC+PCS/PMA switching subsystems in two variants as well as a PCS/ PMA switching subsystem variant. It offers a flexible solution for connection to transmit and receive data interfaces using an AXI4-Stream interface for the MAC+PCS/PMA configuration, and an XGMII/GMII interface for the PCS/PMA configuration…………...” [PG292, Introduction]
A POSITA would implement the data interface as a MAC to reuse standard Ethernet MAC/PCS mechanisms for link management and fault signaling, providing predictable interoperability
Claims 2,3,5,6,14,15 and 16 are rejected under 35 U.S.C. §103 as being unpatentable over Florit et al. in view of Coli et al. and OIF-CMIS-05.2 and further in view of Xilinx PG292 (v2.6), Lin et al. and OIF-400ZR-02.0.
Claim 2
With respect to claim 2, all claim limitations of claim 1 are taught by Florit, Coli, CMIS, PG292 and Lin except wherein the multiplexer is configured to support a 100G, 400G, or 800G coherent optics interface and the optical transmitter is a coherent optical transmitter comprising a coherent optical source. However, within analogous art, OIF-400ZR teaches a 400G coherent optical interface and coherent optical transmitter optics, “This Implementation Agreement (IA) specifies a Digital Coherent Optics 400ZR interface, operating as a 400GBASE-R PHY...” [OIF-400ZR p.13], and further provides transmitter optical (laser) specifications, “13.1.2 Transmitter Optical Specifications... 13.1.200 Laser frequency accuracy...” [OIF-400ZR p.61]. “Implementation Agreement created and approved by the Optical Internetworking Forum for a 400ZR Coherent Optical interface. The 400ZR IA Update project start (oif2020.194.03) was approved at the Q2 Technical Meeting, May 2020. The update project addresses known deficiencies and future work items identified in the OIF400ZR-01.0, including support for operation on 75 GHz channel spacings. This Technical Document has been created by the Optical Internetworking Forum (OIF). This document is offered to the OIF Membership solely as a basis for agreement and is not a binding proposal on the companies listed as resources above. The OIF reserves the rights to at any time to add, amend, or withdraw statements contained herein. Nothing in this document is in any way binding on the OIF or any of its members. The user's attention is called to the possibility that implementation of the OIF implementation agreement contained herein may require the use of inventions covered by the patent rights held by third parties. By publication of this OIF implementation agreement, the OIF makes no representation or warranty whatsoever, whether expressed or implied, that implementation of the specification will not infringe any third party rights, nor does the OIF make any representation or warranty whatsoever, whether expressed or implied, with respect to any claim that has been or may be asserted by any third party, the validity of any patent rights related to any such claim, or the extent to which a license to use any such rights may or may not be available or the terms hereof.” [OIF-400ZR, Abstract].
Therefore, the additional coherent-interface/coherent-source limitations of claim 2 are taught by OIF-400ZR, and it would have been obvious to implement the claim 1 channel-disable/fault signaling within a standardized coherent interface to ensure interoperability.
Claim 3
With respect to claim 3, all claim limitations of claim 2 are taught by Florit, Coli, CMIS, PG292, Lin and OIF-400ZR except wherein the coherent optical source comprises a tunable laser configured to adjust a wavelength of the multiplexed signal. However, within analogous art, Coli teaches sending instructions to adjust/tune a transmission wavelength “the coherent optical source comprises a tunable laser configured to adjust a wavelength of the multiplexed signal”, “…………………In addition to the traffic recovery system, automatic BER adjustment, and security check, other features or instructions may be sent from the first module 110 to the second module 153. For example, the first module 110 may send instructions to enable and/or disable a transmitter of the second module 153. As another example, the first module 110 may send instructions to adjust or tune a transmission wavelength of a transmitter of the second module 153. As an additional example, the first module 110 may send instructions to adjust a receive threshold of a receiver of the second module 153. As another example, the first module 110 may send instructions to enable and/or disable squelch of a receiver of the second module 153. As an additional example, the first module 110 may send instructions to receive diagnostic monitor values from the second module 153 ( e.g., transmit and receive optical power, transmit bias current, module temperature, supply voltage, etc.). As another example, the first module 110 may send instructions to enable and/or disable clock and data recovery (CDR) of a transmitter and/or a receiver of the second module 153. As an additional example, the first module 110 may send instructions to enable and/or disable CDR optical loop back of the second module 153. As an additional example, the first module 110 may send instructions to lock an internal CDR at a specific data rate. As another example, the first module 110 may send instructions to perform a read and/or write command to certain memory locations ( e.g., pages A Oh and/or A2h in the case of SFP transceivers) of the second module 153. As an additional example, the first module 110 may send instructions to update firmware or other settings of the second module 153. As another example, the first module 110 may send instructions to reset a microcontroller of the second module 153. As another example, the first module 110 may send instructions to control lights embedded in the second module 153 (e.g., pull-tab LED lights). As an additional example, the first module 110 may exchange host-specific or network-specific data with the second module 153 (e.g., diagnostic data, ID data, administration data, operation data, maintenance data, provision sets of information, commands, etc.). As another example, the first module 110 may send instructions to negotiate a connection with the second module 153 at a particular or different bit rate. Same Side Communications In some embodiments, instructions, queries, etc. or other messages may be communicated between modules on the same side of the network 160. For example, the second module 153 may communicate with and/or otherwise provide instructions to the third module 156. Such communication may be similar or comparable to that described in the present disclosure between any of the communications between modules at opposite ends (e.g., near vs. far) of the network 160. Mid-Stream Communications In some embodiments, the network 160 may include one or more optical network components that may be disposed mid-stream between the near end and far end of the network 160. For example, there may be such a component on the first optical channel 170 and/or the second optical channel 180. Such a component may perform one or more maintenance tasks on an optical signal, such as amplification, regeneration, adding a channel, dropping a channel, etc. For example, there may be a first span along the first optical channel 170 from the first module 110 to one of these mid-stream components, and a second span from the midstream component to the second module 153. In some embodiments the first module 110 may communicate instructions to one or more of these mid-stream components. For example, instructions may be provided to add one or more channels, drop one or more channels, equalize or otherwise modify power, tune one or more filters, report diagnostic information, etc. In some embodiments, these mid-stream components may be passive or otherwise unable to communicate responses out from the mid-stream component. However, even in such embodiments, the mid-stream components may receive and execute instructions from the first module 110. While described as the first module 110 providing instructions to a mid-stream component, it is equally applicable that any other module ( e.g., the second module 153 and/or the third module 156) may also provide instructions to one or more mid-stream components…………… “ [Coli, Column 5-6].
Thus, claim 3 is taught/obvious in view of claim 2’s coherent optics and Coli’s wavelength-tuning instructions, a known technique to select channels/wavelengths in optical modules.
Claim 5
With respect to claim 5, all claim limitations of claim 1 are taught by Florit, Coli, CMIS, PG292 and Lin except wherein the controller maintains an optical source of the optical transmitter as active after the first channel is disabled while the additional channels remain active. However, within analogous art, CMIS teaches that while the host may independently disable/manage a particular data path/lane group, module implementations may share physical laser resources across data paths (i.e., the laser can remain active to support the remaining enabled channels): “However, module implementations are permitted to utilize shared physical resources for items such as lasers, TECs, processors, etc., as long as the control mechanisms presented to the host for individual data paths and their associated behaviors remain independent of other data paths.” [CMIS p.52].
However, in an analogous art, OIF-400ZR teaches maintaining an optical source (LO) enabled/locked even when OutputDisableTx==true, “the controller is configured to maintain an optical source of the optical transmitter in an active state after the first channel is disabled”, “…………13.1.4 Module Requirements Tx - (Informative) The following specifications provide guidance for modules based on the 400ZR IA. Ref. 13.1.400 , Parameter Transmitter laser disable time , Max 100 , Unit ms , Conditions/Comments The maximum transmitter turn-off time from any condition that results in OutputDisableTx==true to reach the Tx output power given by (13.1.221). Rx shall remain locked and thus LO must remain enabled………” [OIF-400ZR, Table 21].…………….13.2.4 Module Requirements Tx - (Informative) The following specifications provide guidance for modules based on the 400ZR IA. Ref. 13.2.400, Parameter Transmitter laser disable time, Max 100, Unit ms, Conditions/Comments The maximum transmitter turn-off time from any condition that results in OutputDisableTX==true to reach the Tx output power given by (13.2.221). Rx shall remain locked and thus LO must remain enabled………… [OIF-400ZR, Table 26]
Therefore, maintaining an optical source active while a specific channel is disabled would have been obvious for coherent optics to maintain lock and enable rapid restoration (predictable results).
Claim 6
With respect to claim 6, all claim limitations of claim 5 are taught by Florit, Coli, CMIS, PG292 and Lin except wherein the controller disables the optical source in response to all channels being disabled. However, within analogous art, CMIS teaches that internal resources associated with a data path are initialized/deinitialized as a group, and thus when all data paths/channels are deinitialized/disabled, associated resources (including lasers) are deinitialized/disabled: “All module internal resources associated with a Data Path are initialized and deinitialized as a group... Separate Data Paths operating in parallel... are initialized, operated, and deinitialized independently...” [CMIS p.52].
CMIS further teaches that DataPath TX disable aggregates per-lane OutputDisableTx values (Eq. 6-13), and a POSITA would have found it obvious to disable the optical source when no channels remain active to reduce power/heat, “the controller is configured to disable the optical source in response to determining that all additional channels have been disabled”, “…………DPDeactivateS (DataPathDeactivateS) The DPDeactivateS (DataPathDeactivateS) transition signal is defined by the logic equation DPDeactivateS = DPReDeinitS OR DPTxDisableT OR DPTxForceSquelchT (Eq. 6-12) where DPTxDisableT = OutputDisableTx<N> (Eq. 6-13) OR OutputDisableTx<N+1> OR OutputDisableTx<N+M-1> DPTxForceSquelchT = OutputSquelchForceTx<N> (Eq. 6-14) OR OutputSquelchForceTx<N+1> OR OutputSquelchForceTx<N+M-1> N = first media lane in the Data Path M = number of media lanes in the Data Path 1 Note: When in DPActivated or DPTxTurnOn states, setting OutputDisableTx or OutputSquelchForceTx on one media lane of a Data Path intentionally causes that entire Data Path to transition to DPInitialized via DPTxTurnOff. Although some media lanes of the Data Path may continue to be operational (i.e. media lanes with output neither disabled nor squelched), as long as some media lanes are not operational, the Data Path as a whole is considered not activated…………….” [CMIS, 6.3.3.1].
Thus, when all channels are disabled (all OutputDisableTx set), disabling the optical source is an obvious power-saving measure consistent with CMIS management.
Claim 14
With respect to claim 14, all limitations of claim 11 are taught by Florit, Coli, CMIS, PG292 and Lin except wherein the multiplexed signal and modified multiplexed signal each comprise a 100G/400G/800G optical multiplexed signal. However, within analogous art, OIF-400ZR teaches a standardized 400G coherent optical interface (400ZR), an example within the claimed high-rate optical multiplexed signal family, “the multiplexed signal and the modified multiplexed signal each comprise a 100G, 400G, or 800G optical multiplexed signal” “…………..Implementation Agreement created and approved by the Optical Internetworking Forum for a 400ZR Coherent Optical interface. The 400ZR IA Update project start (oif2020.194.03) was approved at the Q2 Technical Meeting, May 2020. The update project addresses known deficiencies and future work items identified in the OIF400ZR-01.0, including support for operation on 75 GHz channel spacings………….” [OIF-400ZR, ABSTRACT].
A POSITA would implement the multiplexed/modified multiplexed signals at standardized high-rate coherent interfaces (e.g., 400ZR) to ensure interoperability and predictable throughput.
Claim 15
With respect to claim 15, all claim limitations of claim 11 are taught by Florit, Coli, CMIS, PG292 and Lin except wherein maintaining an optical source of the optical transmitter as active after the disabling of the first channel while the one or more additional channels remain active. However, within analogous art, CMIS teaches shared laser resources across independently controlled data paths, “However, module implementations are permitted to utilize shared physical resources for items such as lasers... as long as the control mechanisms... remain independent of other data paths.” [CMIS p.52].
However, in an analogous art, OIF-400ZR teaches maintaining coherent lock such that LO remains enabled/locked even when output disable is asserted, supporting keeping the source active, “maintaining an optical source of the first optical communication device in an active state after the first channel is disabled” “………….13.2.4 Module Requirements Tx - (Informative) The following specifications provide guidance for modules based on the 400ZR IA. Ref. 13.2.400, Parameter Transmitter laser disable time, Max 100, Unit ms, Conditions/Comments The maximum transmitter turn-off time from any condition that results in OutputDisableTX==true to reach the Tx output power given by (13.2.221). Rx shall remain locked and thus LO must remain enabled…………” [OIF-400ZR, Table 26]
Accordingly, maintaining the optical source active while disabling only the identified channel would have been obvious to keep remaining channels operational and reduce restart/relock latency.
Claim 16
With respect to claim 16, all claim limitations of claim 15 are taught by Florit, Coli, CMIS, PG292 and Lin except wherein disabling the optical source in response to disabling the first channel and disabling the one or more additional channels. However, within analogous art, CMIS teaches deinitializing internal resources as a group when data paths are deinitialized, “All module internal resources associated with a Data Path are initialized and deinitialized as a group...” [CMIS p.52].
CMIS further teaches aggregating OutputDisableTx bits into DataPath TX disable behavior (e.g., Eq. 6-13), supporting determining “all channels disabled” and disabling accordingly, “disabling the optical source in response to determining that all additional channels have been disabled” “………eactivateS 1 The DPDeactivateS DataPathDeactivateS transition signal is defined by the logic equation 2 DPDeactivateS DPReDeinitS OR DPTxDisableT OR DPTxForceSquelchT Eq 6-12 3 where 4” (OIF-CMIS-05.2, Eq. 6-13, PDF p.76) The DPDeinitS transition signal can also be represented by the logic equation DPDeinitS = ( NOT ModuleReadyT ) OR LowPwrS OR DPDeinitT (Eq. 6-6) where ModuleReadyT = (ModuleState = ModuleReady) (Eq. 6-7) DPDeinitT = DPDeinitLane<N> (Eq. 6-8) OR DPDeinitLane<N+1> 6 … OR DPDeinitLane<N+M-1> N = first host lane in the Data Path M = number of host lanes in the Data Path DPReDeinitS (DataPathReDeinitS) when SteppedConfigOnly = 0 The DPReDeinitS (DataPathReDeinitS) transition signal is defined using the truth table shown in Table 6-17 when the module supports intervention-free reconfiguration, which is advertised by SteppedConfigOnly = 0 (see Table 8-5)………….” [CMIS, 6.3.3.1]
Thus, disabling the optical source when all channels are disabled would have been obvious as a routine power-saving measure consistent with data-path deinitialization.
Claims 12,13,18,19 and 20 are rejected under 35 U.S.C. §103 as being unpatentable over Florit et al. in view of Coli et al. and OIF-CMIS-05.2 and further in view of Xilinx PG292 (v2.6), Lin et al. and Bruckman et al. (US8199637B2).
Claim 12
With respect to claim 12, all claim limitations of claim 11 are taught by Florit, Coli, CMIS, PG292 and Lin except wherein at the second device, in response to receiving the remote fault signal, disabling the first channel and continuing to maintain the additional channels. However, within analogous art, Florit teaches leaving other lane status unchanged while one lane becomes inactive “continuing to maintain the one or more additional channels” “…………..When the lane receives words indicating that the other end is going to disable the lane because it wants to save power or because it is detecting too many errors and cannot receive data correctly; or When the lane is set as a unidirectional transmit-only lane and other lanes of the link have received the information that, at the far end of the link, this lane is not in the Active state. If one lane fails due to errors received on that lane, only that lane status is updated, while leaving the lane status of other lanes unchanged. This is different from other approaches, in which if there are errors in one lane, it causes the whole link to restart all lanes.……….” [Florit, Description of embodiments].
Florit does not expressly teach selective control without affecting other Data Paths However, in an analogous art, CMIS supports selective control without affecting other Data Paths, “continuing to maintain the one or more additional channels” “………The host may request reinitialization of multiple Data Paths in the same register access. Data Paths excluded from the ApplyDPInit selector are not affected. Note: This selective control allows host reconfiguration of individual Data Paths without affecting the operation of other Data Paths in the module. The DPDeactivateS transition signal will also become TRUE if the host sets Tx Output Disable or Tx Force Output Squelch for any lane of the Data Path……...” [CMIS, 6.3.3.9]
CMIS does not expressly teach receiver-side remote-fault detection/status However, in an analogous art, PG292 supports receiver-side remote-fault detection/status, “at the second optical communication device to receiving the remote fault signal disabling the first channel” “…………………………. Table 13: AXI4-Stream Interface–RX Path Control/Status Signals (cont'd)…………. stat_rx_block_lock1…… I/O is 0……... Block lock status. A value of 1 indicates that block lock is achieved as defined in Clause 49.2.14 and MDIO register 3.32.0 This output is level sensitive……… Clock Domain is rx_clk_out………”, [ PG292, Table 13].
PG292 does not expressly teach disabling locally connected physical layers upon receiving an RFI message However, in an analogous art, Bruckman teaches disabling locally connected physical layers upon receiving an RFI message “at the second optical communication device to receiving the remote fault signal disabling the first channel”
“………Upon receiving an RFI message, each node disables the physical layers of the primary topology links that are locally connected to the node. Several exemplary mechanisms for disabling the physical layer resources, which are provided by the node to its locally-connected links, are described further below…….” [Bruckman, Column 7]
A POSITA would disable the affected channel at the second device upon RFI to prevent use of a faulted lane while maintaining remaining lanes for continued service (predictable reliability improvement).
Claim 13
With respect to claim 13, all limitations of claim 12 are taught by Florit, Coli, CMIS, PG292, Lin and Bruckman except wherein the second device does not implement a CMIS 5.2 standard and processes the remote fault signal. However, within analogous art, PG292 teaches receiver remote-fault processing/status independent of CMIS management, “...stat_rx_remote_fault... Remote fault indication status... indicates a remote fault condition was detected... remote fault condition does not exist...” [PG292 p.24].
PG292 further teaches IEEE 802.3 Clause 49 PCS remote-fault behavior and receiver remote-fault indication status, supporting processing independent of CMIS 5.2, “the second optical communication device does not implement a CMIS 5.2 standard; and the second optical communication device processes the remote fault signal in accordance with a standard predating the CMIS 5.2 standard” “…………... the features of the 1G/10G/25G Ethernet Subsystem dynamically switching PCS/PMA and MAC core. The 10G/25G Ethernet Subsystem is defined by the 25G Ethernet Consortium. 10G PCS functionality is defined by IEEE Standard 802.3, 2015, Clause 49Physical Coding Sublayer (PCS) for 64B/66B, type 10GBASE-R. 1G PCS functionality is defined in Clause 36. For 25G operation, clock frequencies are increased to provide a serial interface operating at 25.78125 Gb/s to leverage the latest high-speed serial transceivers. The low latency design is optimized for UltraScale+™ architecture devices………...” [PG292, Subsystem Overview], “…………………………. Table 13: AXI4-Stream Interface–RX Path Control/Status Signals (cont'd)…………. stat_rx_block_lock1…… I/O is 0……... Block lock status. A value of 1 indicates that block lock is achieved as defined in Clause 49.2.14 and MDIO register 3.32.0 This output is level sensitive……… Clock Domain is rx_clk_out………”, [ PG292, Table 13].
A POSITA would rely on standard IEEE 802.3 PCS remote-fault semantics for backward compatibility such that the peer can detect/process remote fault indications without requiring CMIS 5.2 management.
Claim 18
recites a system including a first optical communication device implementing the same functional sequence of claim 1
Florit teaches an optical communication device using a fiber-optic link, “system includes a first optical communication device” “……...The Physical Layer 114 serialises the BB/1 OB symbols and sends them over the physical medium via a Physical Interface 116. In the receiver the Physical Layer recovers the clock and data from the serial bit stream, determines the symbol boundaries and recovers the BB/1 OB symbols. Both electrical cables and fibre-optic cables are supported by SpaceFibre. The Management Layer 118 supports the configuration, control and monitoring of all the layers in the SpaceFibre protocol stack via a Management Interface 120. A problem with conventional approaches in multi-laning is that the number of lanes is fixed after configuration and an arbitrary number of mixed bidirectional and unidirectional lanes is not possible. Another problem is that, in conventional approaches, fault recovery time is long so any data not sent while the link is recovering from a lane failure cannot be stored in small internal buffers without affecting end user operation……….” [Florit, Background Art]
Florit further teaches the multiplexer/serializer forming multiplexed streams across multiple lanes/channels, “a multiplexer configured to generate a multiplexed signal encoding a first channel and one or more additional channels” “………. The other end does the same, and both ends receive the information of the configuration that the other end is using. If an end determines that the configuration does not match, it restarts everything again with a new configuration that it is more likely to match the other side. Thus, the link is reinitialised by resetting all lanes, not maintaining bit or symbol synchronisation. This system does not support changes in configuration when the system is initializing. Examples of a change of configuration are when a user disables a lane or a lane stops working, as described with reference to Figure 2. Figure 3 is a conceptual diagram illustrating the use of each type of data unit described herein and how they are multiplexed……” [Florit, Description of embodiments].
In an analogous art, Florit teaches transmitting over fiber-optic link, “an optical transmitter configured to transmit the multiplexed signal over an optical link to a second optical communication device”
“…………the physical medium via a Physical Interface 116. In the receiver the Physical Layer recovers the clock and data from the serial bit stream, determines the symbol boundaries and recovers the BB/1 OB symbols. Both electrical cables and fibre-optic cables are supported by SpaceFibre. The Management Layer 118 supports the configuration, control and monitoring of all the layers in the SpaceFibre protocol stack via a Management Interface 120……………” [Florit, Background Art]
Further, Florit teaches leaving other lanes unchanged while one lane becomes inactive, “cause the multiplexer to generate a modified multiplexed signal encoding the one or more additional channels and not the first channel”“………When the lane receives words indicating that the other end is going to disable the lane because it wants to save power or because it is detecting too many errors and cannot receive data correctly; or When the lane is set as a unidirectional transmit-only lane and other lanes of the link have received the information that, at the far end of the link, this lane is not in the Active state. If one lane fails due to errors received on that lane, only that lane status is updated, while leaving the lane status of other lanes unchanged. This is different from other approaches, in which if there are errors in one lane, it causes the whole link to restart all lanes………” [ Florit, Description of embodiments].
within analogous art, Florit teaches continued optical transmission, “cause the optical transmitter to transmit the modified multiplexed signal to the remote device over the optical link” “……………physical medium via a Physical Interface 116. In the receiver the Physical Layer recovers the clock and data from the serial bit stream, determines the symbol boundaries and recovers the BB/1 OB symbols. Both electrical cables and fibre-optic cables are supported by SpaceFibre………….” [Florit, Background Art].
Florit does not expressly teach receiving/using OutputDisableTx<N> identifying the lane/channel to be disabled, However, in an analogous art, CMIS teaches receiving/using OutputDisableTx<N> identifying the lane/channel to be disabled, “a controller configured to receive a disable signal identifying the first channel” “…………Control of Rx Output Squelching Function The Rx output squelch function is controlled only by a module-internal squelch controller (if supported) that automatically activates the output squelch function when no suitable media side Rx input signal is available to be forwarded on the host side output. Note: A single Rx input lane may feed more than one Rx output lane, and the data transmitted on one Rx output lane may originate from more than one Rx input lane. The internal controller squelches an Rx electrical output lane until all associated Rx input lanes have detected a valid input signal and all associated internal resources are fully initialized and capable of forwarding a valid stable signal, in order to avoid link flaps. The automatic Rx output squelch controller itself (if supported) can be enabled or disabled by the host. 8.9.2.3 Lane-specific Tx and Rx Control Fields This section lists the specific controls for the purposes discussed above. Tx Output Controls The host can disable and un-disable Tx output lane N using OutputDisableTx<N> The host can force and unforce squelching of Tx output lane N using OutputSquelchForceTx<N>. The host can disable or enable the internal squelch controller for lane N using AutoSquelchDisableTx<N>………….” [CMIS, 8.9.2.2 Rx Output Muting Functions and Their Control].
CMIS further teaches per-lane disable and DataPath TX disable logic responsive to OutputDisableTx bits, “disable the first channel” “……………..The automatic Rx output squelch controller itself (if supported) can be enabled or disabled by the host. 8.9.2.3 Lane-specific Tx and Rx Control Fields This section lists the specific controls for the purposes discussed above. Tx Output Controls The host can disable and un-disable Tx output lane N using OutputDisableTx<N> The host can force and unforce squelching of Tx output lane N using OutputSquelchForceTx<N>…………” [CMIS, 8.9.2.2], “………eactivateS 1 The DPDeactivateS DataPathDeactivateS transition signal is defined by the logic equation 2 DPDeactivateS DPReDeinitS OR DPTxDisableT OR DPTxForceSquelchT Eq 6-12 3 where 4” (OIF-CMIS-05.2, Eq. 6-13, PDF p.76) The DPDeinitS transition signal can also be represented by the logic equation DPDeinitS = ( NOT ModuleReadyT ) OR LowPwrS OR DPDeinitT (Eq. 6-6) where ModuleReadyT = (ModuleState = ModuleReady) (Eq. 6-7) DPDeinitT = DPDeinitLane<N> (Eq. 6-8) OR DPDeinitLane<N+1> 6 … OR DPDeinitLane<N+M-1> N = first host lane in the Data Path M = number of host lanes in the Data Path DPReDeinitS (DataPathReDeinitS) when SteppedConfigOnly = 0 The DPReDeinitS (DataPathReDeinitS) transition signal is defined using the truth table shown in Table 6-17 when the module supports intervention-free reconfiguration, which is advertised by SteppedConfigOnly = 0 (see Table 8-5)………….” [CMIS, 6.3.3.1].
within analogous art, CMIS teaches selective DataPath control without affecting others, “cause the multiplexer to generate a modified multiplexed signal encoding the one or more additional channels and not the first channel” “………. The ApplyDPInit bits for all lanes in the Data Path shall be triggered with one register access. The host may request reinitialization of multiple Data Paths in the same register access. Data Paths excluded from the ApplyDPInit selector are not affected…………” [CMIS, 6.3.3.9 DPActivated State].
Further, CMIS supports selective continuation on remaining Data Paths, “cause the optical transmitter to transmit the modified multiplexed signal to the remote device over the optical link” “…………. ApplyDPInit bits for all lanes in the Data Path shall be triggered with one register access. The host may request reinitialization of multiple Data Paths in the same register access………….” [CMIS, 6.3.3.9].
CMIS does not expressly teach transmitting Remote Fault Indication (RFI) code words toward the peer on the TX path, However, in an analogous art, PG292 teaches transmitting Remote Fault Indication (RFI) code words toward the peer on the TX path, “in response to receiving the disable signal cause the optical transmitter to transmit a remote fault signal to the second optical communication device on the first channel of the multiplexed signal” “…………TX Path Control/Status/Statistics Signals Table 59: TX Path Control/Status/Statistic Signals, Name ctl_tx_send_rfi_*, Size 1, I/O 1, Description Transmit Remote Fault Indication (RFI) code word. If this input is sampled as a 1, the TX pat only transmits Remote Fault code words. This input should be set to 1 until the RX path is fully aligned and is ready to accept data from the link partner………….” [PG292, Table 59].
PG292 does not expressly teach transmitting Remote Fault Indication (RFI) code words toward the peer on the TX path, However, in an analogous art, Bruckman teaches optical link devices with laser-driven optical links, “system includes a first optical communication device” “…………….The network according to claim 16, wherein the one or more of the links in the first set of links comprise optical links, and wherein the network nodes comprise respective laser sources for driving the optical links and are arranged to deactivate the physical layer resources by disabling the laser sources………” [Bruckman, Column 13].
Bruckman further teaches optical links driven by laser sources, “an optical transmitter configured to transmit the multiplexed signal over an optical link to a second optical communication device” “………...more of the links in the first set of links comprise optical…….” [Bruckman, Column 13].
A POSITA would assemble the system using standardized per-lane disable and RFI signaling mechanisms to provide predictable end-to-end interoperable behavior and fault isolation.
Claim 19
With respect to claim 19, all limitations of claim 18 are taught by Florit, Coli, CMIS, PG292, Lin and Bruckman except that the system further comprises the second optical communication device configured to, upon receiving the remote fault signal, disable the first channel and continue to maintain the additional channels. However, Florit teaches a remote peer device connected by the fiber-optic link, “system further includes second optical communication device” “……...The Physical Layer 114 serialises the BB/1 OB symbols and sends them over the physical medium via a Physical Interface 116. In the receiver the Physical Layer recovers the clock and data from the serial bit stream, determines the symbol boundaries and recovers the BB/1 OB symbols. Both electrical cables and fibre-optic cables are supported by SpaceFibre. The Management Layer 118 supports the configuration, control and monitoring of all the layers in the SpaceFibre protocol stack via a Management Interface 120. ……….” [Florit, Background Art].
Florit further teaches leaving other lane status unchanged while one lane becomes inactive, “second device continue to maintain additional channels”, “……………………..for example, by counting the number of 881 OB decoding errors; When the lane receives words indicating that the other end is going to disable the lane because it wants to save power or because it is detecting too many errors and cannot receive data correctly; or When the lane is set as a unidirectional transmit-only lane and other lanes of the link have received the information that, at the far end of the link, this lane is not in the Active state If one lane fails due to errors received on that lane, only that lane status is updated, while leaving the lane status of other lanes unchanged. This is different from other approaches, in which if there are errors in one lane, it causes the whole link to restart all lanes.……….” [Florit, Description of embodiments].
Florit does not expressly teach selective control without impacting other Data Paths, However, in an analogous art, CMIS supports selective control without impacting other Data Paths, “second device continue to maintain additional channels” “………. The ApplyDPInit bits for all lanes in the Data Path shall be triggered with one register access. The host may request reinitialization of multiple Data Paths in the same register access. Data Paths excluded from the ApplyDPInit selector are not affected…………” [CMIS, 6.3.3.9 DPActivated State].
CMIS does not expressly teach receiver-side remote-fault status, However, in an analogous art, PG292 supports receiver-side remote-fault status, “second device: in response to receiving remote fault signal, disable first channel” “…………………………. Table 13: AXI4-Stream Interface–RX Path Control/Status Signals (cont'd)…………. stat_rx_block_lock1…… I/O is 0……... Block lock status. A value of 1 indicates that block lock is achieved as defined in Clause 49.2.14 and MDIO register 3.32.0 This output is level sensitive……… Clock Domain is rx_clk_out………”, [ PG292, Table 13].
PG292 does not expressly teach disabling locally connected physical layers upon receiving an RFI message, However, in an analogous art, Bruckman teaches disabling locally connected physical layers upon receiving an RFI message, “second device in response to receiving remote fault signal, disable first channel” “………Upon receiving an RFI message, each node disables the physical layers of the primary topology links that are locally connected to the node. Several exemplary mechanisms for disabling the physical layer resources, which are provided by the node to its locally-connected links, are described further below…….” [Bruckman, Column 7]
A POSITA would have the second device disable the affected channel upon RFI while continuing other channels to maintain partial service and avoid a faulted lane (predictable reliability gain).
Claim 20
With respect to claim 20, all limitations of claim 19 are taught by Florit, Coli, CMIS, PG292, Lin and Bruckman except that the second device does not implement CMIS 5.2 and processes the remote fault under a predating standard. However, PG292 teaches remote-fault signaling/processing at PCS level (Clause 49) and receiver remote-fault status independent of CMIS 5.2 management, “second device does not implement CMIS 5.2” “……………the features of the 1G/10G/25G Ethernet Subsystem dynamically switching PCS/PMA and MAC core. The 10G/25G Ethernet Subsystem is defined by the 25G Ethernet Consortium. 10G PCS functionality is defined by IEEE Standard 802.3, 2015, Clause 49, Physical Coding Sublayer (PCS) for 64B/66B, type 10GBASE-R. 1G PCS functionality is defined in Clause 36. For 25G operation, clock frequencies are increased to provide a serial interface operating at 25.78125 Gb/s to leverage the latest high-speed serial transceivers. The low latency design is optimized for UltraScale+™ architecture devices…………..” [PG292, Overview]
PG292 further teaches receiver remote-fault indication status at the PCS layer: “...stat_rx_remote_fault... Remote fault indication status. If this bit is sampled as a 1, it indicates a remote fault condition was detected... remote fault condition does not exist...” [PG292 p.24], “Subsystem dynamically switching PCS/PMA and MAC core. The 10G/25G Ethernet Subsystem is defined by the 25G Ethernet Consortium. 10G PCS……” [PG292, Subsystem], “…………………………. Table 13: AXI4-Stream Interface–RX Path Control/Status Signals (cont'd)…………. stat_rx_block_lock1…… I/O is 0……... Block lock status. A value of 1 indicates that block lock is achieved as defined in Clause 49.2.14 and MDIO register 3.32.0 This output is level sensitive……… Clock Domain is rx_clk_out………”, [ PG292, Table 13].
A POSITA would process the remote-fault indication using predating IEEE 802.3 PCS behavior to maintain backward compatibility without CMIS 5.2.
A POSITA would process RFI under predating IEEE 802.3 PCS behavior to maintain backward compatibility without CMIS 5.2.
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP 2123.
Conclusion
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/MOHAMMED ABDELRAHEEM/Examiner, Art Unit 2635
/DAVID C PAYNE/Supervisory Patent Examiner, Art Unit 2635