DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 11 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The limitations as recited is not supported by the specification as originally filed.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the recitations of “a first gate contact” and “a second gate contact” are vague because they are not related to other elements in the claim.
The dependent claims 2-8 are also rejected because they are, directly or indirectly, depending from rejected claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-10 and 12-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Do et al. (US 2022/0059460).
Regarding claim 1, Do teaches a semiconductor device comprising: a substrate ([0066]) comprising a standard cell area and an ending cell area that at least partially surrounds the standard cell area ([0047]); a first active pattern in the standard cell (active pattern 105, [0059] and [0065]); a first wiring that extends in a first direction and is on the first active pattern ([0058]); a first gate electrode (145) that extends in a second direction and is on the first active pattern ([0065] and [0113]); a first gate contact ([0078] and [0119]); a second active pattern (active pattern 105, [0059] and [0065]); a second wiring that extends in the first direction and is on the second active pattern ([0058]); a second gate electrode that extends in the second direction and is on the second active pattern ([0065] and [0113]); a second gate contact ([0078] and [0119]) (figs. 4-5C and 11).
Regarding claim 2, Do further teaches wherein the first gate contact is electrically connected to the first gate electrode and the first wiring, and wherein the second gate contact is electrically connected to the second gate electrode and the second wiring ([0117]-[0120]).
Regarding claim 3, Do further teaches wherein the first gate contact and the second gate contact have a same length in at least one of the first direction and the second direction (180, figs. 7 and 11).
Regarding claim 4, Do further teaches a first power rail (PM1) that extends in the first direction; a second power rail (PM2) that extends in the first direction and is spaced apart from the first power rail in the second direction, and a plurality of the second wirings (M1a-M1d), wherein the plurality of the second wirings are between the first power rail and the second power rail in the second direction, wherein the second gate contact is on a given second wiring from among the plurality of the second wirings, and wherein the given second wiring is adjacent to the first power rail or the second power rail (figs. 4B-5B).
Regarding claim 5, Do further teaches a first power rail (PM1) that extends in the first direction; and a second power rail (PM2) that extends in the first direction and is spaced apart from the first power rail in the second direction, wherein the second active pattern (105) comprises a third active sub-pattern that is electrically connected to the first power rail and a fourth active sub-pattern that is electrically connected to the second power rail (fig. 6).
Regarding claim 6, Do further teaches wherein the first wiring and the second wiring are not electrically connected ([0060]-[0065]).
Regarding claim 7, Do further teaches wherein: the first active pattern (105) comprises a first fin-shaped pattern that extends in the first direction and extends from the substrate, the second active pattern (105) comprises a second fin-shaped pattern that extends in the first direction and extends from the substrate, the first gate electrode overlaps the first fin-shaped pattern, and the second gate electrode overlaps the second fin-shaped pattern (fig. 5B and [0065]).
Regarding claim 8, Do further teaches wherein: the first active pattern (105) comprises a first fin-shaped pattern that extends in the first direction and extends from the substrate, the first active pattern comprises a first sheet pattern (channel layers) that is spaced apart from the first fin-shaped pattern, the second active pattern (105) comprises a second fin-shaped pattern that extends in the first direction and extends from the substrate, the second active pattern comprises a second sheet pattern (channel layers) that is spaced apart from the second fin-shaped pattern, the first gate electrode overlaps the first sheet pattern, and the second gate electrode overlaps the second sheet pattern ([0084]-[0088]).
Regarding claim 9, Do teaches a semiconductor device comprising: a substrate (101) comprising a standard cell area (SC) and an ending cell (FC) area that at least partially surrounds the standard cell area ([0047] and [0066]); an active pattern (PN) in the ending cell area (fig. 3); a power rail (PM1 and PM2) that extends in a first direction and is on the active pattern (fig. 4A); a wiring (M1a-M1d) that extends in the first direction and is on the active pattern (fig. 5A); one or more gate electrodes (145) that extend in a second direction and are on the active pattern (figs. 5B and 5C); a gate contact (180) between the gate electrode and the wiring (fig. 5C) a source/drain pattern (120) on the active pattern and on one side of the gate electrode (fig. 5C); and a well contact (NWEL) between the source/drain pattern and the power rail ([0058]).
Regarding claim 10, Do further teaches wherein the wiring is adjacent to the power rail (fig. 5A).
Regarding claim 12, Do further teaches wherein the wiring does not extend into the standard cell area (fig. 5B).
Regarding claim 13, Do further teaches wherein the power rail and the wiring extend by same distance from the substrate (fig. 5B).
Regarding claim 14, Do teaches a semiconductor device comprising: a substrate (101, fig. 5A); a first active pattern (105, fig. 5A) on the substrate; a second active pattern (another of 105, fig. 5A) on the substrate; a first gate electrode (145, II2-II2’, fig. 11) that is on the first active pattern and extends in a second direction; a second gate electrode (another of 145, II2-II2’, fig. 11) that is on the second active pattern and extends in the second direction; a first wiring (M1b, fig. 5B) that extends in a first direction and is on the first active pattern; a second wiring (M1c, fig. 5B) that extends in the first direction and is on the second active pattern; a power rail (PM1 and PM2) that extends in the first direction and is on the substrate; a first gate contact (180, fig. 5C) between the first gate electrode and the first wiring; and a second gate contact (another of 180, II2-II2’, fig. 11) between the second gate electrode and the second wiring, wherein the second active pattern is electrically connected to the power rail, and wherein the first wiring and the second wiring are not electrically connected to each other (fig. 11).
Regarding claim 15, Do further teaches wherein the second wiring is adjacent to the power rail (fig. 5A).
Regarding claim 16, Do further teaches wherein the first active pattern comprises a first fin-shaped pattern and a first sheet pattern that is on and spaced apart from the first fin-shaped pattern (figs. 5A and 7B, [0065] and [0084]), and the second active pattern comprises a second fin-shaped pattern and a second sheet pattern that is on and spaced apart from the second fin-shaped pattern (figs. 5A and 7B, [0065] and [0084]).
Regarding claim 17, Do further teaches wherein the first gate contact and the second gate contact have a same length in at least one of the first direction and the second direction (fig. 7B).
Regarding claim 18, Do further teaches wherein the first gate contact and the second gate contact have a same length in a direction that is perpendicular to an upper surface of the substrate (fig. 7B).
Regarding claim 19, Do further teaches wherein the second active pattern is adjacent to the first active pattern in the first direction or the second direction (fig. 5A).
Regarding claim 20, Do further teaches a source/drain pattern (120) that is on the second active pattern and on one of the second gate electrode; and a well contact between the source/drain pattern and the power rail (fig. 5A and 5B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Do in view of Kang et al. (US 2022/0037495).
Regarding claim 11, Do teaches all subject matter claimed as applied above except for plurality of gate electrodes as claimed.
However, Kang teaches semiconductor comprises plurality of gate electrodes as claimed ([0072]).
In view of Kang’s teaching, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Do by incorporating the teaching as taught by Kang in order to arrive at the claimed invention.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
References: Koh et al. (US 2022/0093630); Lee et al. (US 11,646,305); Baek et al. (US 2022/0059571); Park et al. (US 2019/0123140) and Kumura (US 2010/0052022) are cited because they are related to semiconductor device.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Tuyen Kim Vo whose telephone number is (571)270-1657. The examiner can normally be reached Mon-Thurs: 8AM-6:30PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Paik can be reached at 571-272-2404. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TUYEN K VO/Primary Examiner, Art Unit 2876
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