DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Strydom (US 11435770).
PNG
media_image1.png
496
719
media_image1.png
Greyscale
With respect to claim 1, Strydom (US 11435770) discloses a driver (102) for a power switching device (106), comprising: an input terminal (at PWM), configured to receive a switching control signal (PWM); and an output terminal (at Rext), coupled to a control terminal of the power switching device (at 106), and configured to provide a driving voltage (Vgs) to control turn-on and turn-off switching of the power switching device (106); wherein the driver is configured to generate the driving voltage (Vgs) to control the power switching device according to the switching control signal (Sp and SN) and a current (ig) flowing through the control terminal (at 106) of the power switching device, wherein when the switching control signal (PWM) is at a first state (charge), the driver is configured to control the power switching device to be turned on according to a current flowing (ig) through the control terminal of the power switching device (col. 5 lines 36-41), and when the switching control signal is at a second state (discharge), the driver is configured to control the power switching device (106) to be turned off, and wherein the current (ig) flowing through the control terminal (at 106) of the power switching device indicates a voltage (ig and Rg sufficient to produce vgs to turn on transistor) between two power terminals (ground and power terminal upstream from d) of the power switching device.
With respect to claim 2, Strydom (US 11435770) discloses the driver of claim 1, further comprising: a power supply terminal (at Vcc) , configured to receive a power supply voltage (Vcc); a control circuit (104), configured to generate a driving control signal (at gate input) according to the switching control signal (PWM); and the current (ig) flowing through the control terminal of the power switching device (106); and a driving circuit (SP and SN), coupled between the power supply terminal (at Vcc) and a power terminal (GND) of the power switching device (106), and configured to generate the driving voltage (Vgs) under the control of the driving control signal (PWM).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3-8, 10-12 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Strydom (US 11435770). in view of Gold (6172550) in further view of Ausseresse (US 10355610).
PNG
media_image1.png
496
719
media_image1.png
Greyscale
With respect to claim 3, Strydom discloses the driver of claim 1, but fails to disclose wherein the driver is further configured to adjust, according to the current flowing through the control terminal device (at gate of transistor) of the power switching device, a delay time between a moment when the switching control signal changes to the first state and a moment when the driving voltage starts to change to turn on the power switching device.
PNG
media_image2.png
769
1171
media_image2.png
Greyscale
With respect to claim 3, Gold teaches a similar, wherein the driver is further configured to adjust, according to the current, a delay time (propagation delay) between a moment when the switching control signal changes to the first state (i.e, pull up) and a moment when the driving voltage starts to change to turn on the power switching device but fails to disclose the current sensor adjusting, according to the current flowing through the control terminal device of the power switching device.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use the current sensor and adjusting circuitry in Gold in Strydom for the Gold disclosed purpose of (regulating the deadtime interval for optimal value for loss reduction col. 9 lines 10-25).
PNG
media_image3.png
502
796
media_image3.png
Greyscale
Ausseresse teaches in Fig. 2 current sensing at the gate terminal of a low side switch.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to use the teaching of Ausseresse in the combination of Strydom and Gold for the Ausseree disclosed purpose of using the current sensing circuit to control algorithims of the controller (col. 5 lines 30-36) and use in inductive mode (col. 14 lines 6-12)
With respect to claim 4, the combination above produces the driver of claim 3, wherein the control circuit ( Gold: elements PWM Controller, timing generator clock oscillator and sample &hold) is further configured to control the power switching device (Strydom: 106) to be turned on when the delay time reaches a preset duration (produced by timing generator).
With respect to claim 5, the combination above produces the driver of claim 1, further comprising: a current sensing circuit (Gold: current sensor 110), configured to sense the current flowing through the control terminal of the power switching device (ig) to generate a current sensing signal (into sample and hold); wherein when the switching control signal (at gate driver high side 12) is at the first state, the driver is configured to control the power switching device (high side transistor 12) to be turned on according to a comparison result of the current sensing signal (at sample and hold) and a current threshold.
With respect to claim 6, the combination above produces the driver of claim 2 wherein the driving circuit comprises: a first switch (SP), comprising a first terminal, a second terminal and a control terminal, wherein the first terminal of the first switch is coupled to the power supply voltage (Vcc), and the control terminal of the first switch is coupled to the control circuit (( Gold: elements PWM Controller, timing generator clock oscillator and sample &hold)); and a second switch (SN), comprising a first terminal, a second terminal and a control terminal, wherein the second terminal of the second switch is coupled to one of the power terminals of the power switching device (at gnd), and the control terminal of the second switch is coupled to the control circuit (at gate), and wherein the second terminal of the first switch and the first terminal of the second switch jointly provide the driving voltage (at output going into Rext).
With respect to claim 7, the combination above produces the driver of claim 2, further comprising: a current sensing circuit (current sensor/current sensing), configured to sense the current flowing through the control terminal (ig) of the power switching device (106) to generate a current sensing signal; wherein the control circuit further comprises: a zero-voltage turn-on control circuit (Gold PWM), configured to provide a zero-voltage turn-on control signal according to a comparison result of the current sensing signal (current sense) and a current threshold; and a logic circuit (timing generator or logic and drivers (104)), configured to generate the driving control signal according to the switching control signal and the zero-voltage turn-on control signal. (col. 5 lines 63-67 and col. 6 lines1-2 “Thus, in accordance with the invention, at time t.sub.2, MOSFET device 14 can be turned-on, automatically or by a controller, to serve as a commutating diode. In this way, the inductive load current is allowed to flow through MOSFET device 14 under a zero-voltage switching condition there by minimizing commutation losses.”)
With respect to claim 8, the combination above produces the driver of claim 7, wherein the control circuit further comprises: a signal processing circuit (sample and hold), configured to provide a turn-on control signal and a turn-off control signal according to the switching control signal (PWM from PWM controller).
With respect to claim 10, the combination above produces a driver (102) for a power switching device (106), comprising: an input pin, configured to receive a switching control signal (PWM); a first output pin (at Rext), coupled to a control terminal of the power switching device through a first resistor (Rext); a second output pin (from Rg), coupled to the control terminal of the power switching device through a second resistor (Rg); a power supply pin (at Vcc), configured to receive a power supply voltage (Vcc); a reference ground pin (at Gnd); a control circuit (Strydom :104/ Gold: elements PWM Controller, timing generator clock oscillator and sample &hold), configured to generate a driving control signal according to the switching control signal (at switch) and a current (ig) flowing through the control terminal of the power switching device(106); and a driving circuit (Sp and Sn), coupled between the power supply pin and the reference ground pin, and configured to control turn-on and turn-off switching of the power switching device (106) through the first output pin and the second output pin under the control of the driving control signal (at gates of SP and Sn), wherein the current (ig) flowing through the control terminal of the power switching device (106) indicates a voltage between two power terminals (gnd and power upstream from d) of the power switching device.
With respect to claim 11, the combination above produces the driver of claim 10, wherein the driving circuit comprises: a first switch (Sp), comprising a first terminal, a second terminal and a control terminal, wherein the first terminal of the first switch is coupled to the power supply pin (at Vcc), the second terminal of the first switch is coupled to the first output pin, and the control terminal of the first switch is coupled to the control circuit (from 104/(( Gold: elements PWM Controller, timing generator clock oscillator and sample &hold); and a second switch (SN), comprising a first terminal, a second terminal and a control terminal, wherein the first terminal of the second switch is coupled to the second output pin, the second terminal of the second switch is coupled to the reference ground pin (gnd), and the control terminal of the second switch is coupled to the control circuit(from 104/(( Gold: elements PWM Controller, timing generator clock oscillator and sample &hold.
With respect to claim 12, the combination above produces the driver of claim 11, further comprising: a current sensing circuit (Current sensing 209 / Gold Current sensor), configured to sense a current flowing through the second switch (Sn) to generate a current sensing signal (feedback to controller); wherein when the switching control signal is at a first state, the driver is configured to control the power switching device to be turned on according to a comparison result of the current sensing signal and a current threshold (via algorithm).
With respect to claim 20, the combination above produces a voltage converter (i.e gold would be considered a converter), comprising: a power switching device (106) and a driver (102), wherein the driver comprises: an input terminal, configured to receive a switching control signal (i.e. PWM) ; an output terminal (at gate of 106), coupled to a control terminal of the power switching device (106), and configured to provide a driving voltage to control turn-on and turn-off switching of the power switching device; wherein the driver is configured to generate the driving voltage (Vgs) to control the power switching device according to the switching control signal (Sp and SN) and a current (ig) flowing through the control terminal (at 106) of the power switching device, wherein when the switching control signal is at a first state (i.e. charge), the driver is configured to control the power switching device to be turned on according to the current (ig) flowing through the control terminal of the power switching device (106), and when the switching control signal is at a second state (discharge), the driver is configured to control the power switching device (106) to be turned off (see Stydrom (col. 5 lines 36-41)), wherein the current (ig) flowing through the control terminal (at 106) of the power switching device indicates a voltage (ig and Rg sufficient to produce vgs to turn on transistor) between two power terminals (ground and power terminal upstream from d) of the power switching device.
Allowable Subject Matter
Claims 9 and 13 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 9, the prior art of record fails to suggest or disclose the driver of claim 8, wherein the signal processing circuit comprises: a first isolating capacitor, configured to electrically isolate the turn-on control signal from the switching control signal; and a second isolating capacitor, configured to electrically isolate the turn-off control signal from the switching control signal.
With respect to claim 13, the prior art of record fails to suggest or disclose the driver of claim 11, further comprising: a third resistor, coupled between the power supply pin and the control terminal of the first switch; and a fourth resistor, coupled between the second output pin and the control terminal of the second switch.
Claims 14-19 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 14, the prior art of record fails to suggest or disclose a second power supply voltage; a second reference ground pin; a first control circuit, coupled to the first reference ground pin and the first power supply pin to receive the first power supply voltage, and configured to generate a first driving control signal according to the first switching control signal and a current flowing through the control terminal of the first power switching device; and a first driving circuit, coupled between the second power supply pin and the second reference ground pin, and configured to generate the first driving voltage under the control of the first driving control signal.
Here, there is no second power supply voltage as well as the couplings accordingly disclosed above.
Claims 15-19 are allowable based on their dependence on claim 14.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are not persuasive.
The new amendments still read on Strydom and Strydom in view of Gold.
With response to providing the control current ig according to only the PWM signal, not both the PWM and the current flowing through the control terminal, the Examiner disagrees as ig is produce based on the current flowing through the control terminal as recited.
With response to 103, the Examiner maintains the rejection based on similar arguments above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAREEM E ALMO whose telephone number is (571)272-5524. The examiner can normally be reached M-F (8:00am-4:00pm).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at M-F (8:00am-4:00pm). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KHAREEM E ALMO/Examiner, Art Unit 2849
/Menatoallah Youssef/SPE, Art Unit 2849