DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7 and 13-14 are rejected under 35 U.S.C. 102a1 as being anticipated by US Patent Application Publication to Sugiyama 2017/0033884US.
In terms of Claim 1, Sugiyama teaches an optical integrated device (Figure 8) comprising a first chip (Figure 8: 25) including an optical circuit (Figure 8: portion of 25, 16 and 12 as shown in Figure 3 and along with portion of 30 makes up the optical circuit), and a second chip (Figure 8: 70) including an optical waveguide (Figure 8: 85) including a material with an electro-optic effect (arms 85a-b are similar to arms 21 shown in Figure 3 which are made from lithium niobate which produces electro-optic effects [0035]) larger than the electro-optic effect of a material of the first chip (Modulator arms within 80 mainly 85a-d must have a larger electro-optic effects than 25 otherwise it won’t be able to modulate the signals going through 80), wherein the first chip (25) is mounted in a trench formed on the second chip (70), and the first chip is optically coupled to the second chip by butt coupling (Figure 8: 25 contains waveguide 56a as shown in Figure 6, which couples to waveguide arms 85a-d that is butt coupled via segment 73 on second chip 70).
As for Claim 2, Sugiyama teaches the device of Claim 1, wherein the second chip (Figure 8: 70) includes an optical modulator (Figure 8: 20) connected to the optical waveguide (Figure 8: portion 20 is coupled to waveguide 85 via segment 73 and couples to 1st chip via 56a as shown in Figure 3), and the optical circuit (Figure 8: 30) includes a polarization rotator (Figure 8: PR or 47) that rotates a polarization of signal light from the optical modulator (Figure 8: 20), and a polarization multiplexer (30 can also function as a multiplexer [0037] wherein the signal once it leaves portion 30 is fully multiplex [0037]) that polarization-multiplexes the signal light from the optical modulator and signal light after the polarization rotation performed by the polarization rotator (Figure 8: 20 and 30 and [0037]).
As for Claim 3, Sugiyama teaches the device of Claim 1, wherein the second chip (70) includes a second bonding surface (Figure 8: within recess on 70, wherein 25 is located [0045]), and a second optical waveguide that is located obliquely to the second bonding surface ([0036]), the first chip (25) includes a first bonding surface that is in contact with the second bonding surface (Figure 3: see endface edge 25a-b is inclined or oblique), and a first optical waveguide that is located obliquely to the first bonding surface (Figure 6: 56a to end face of 25 which is shown in Figure 3 as element 25a) and is connected to the second optical waveguide (Figure 6: 56 is coupled segment of waveguide 73 shown in Figure 8 [0035]).
As for Claim 4, Sugiyama teaches the device of Claim 1, wherein the second chip (70) includes a second optical waveguide (73 or arms within 80), and a second bonding surface of the trench that is oblique to the second optical waveguide (Figure 8: 73 contain waveguide 61 of which is coupled to 25, Figure 6: shown that waveguide 56a couples to 73 via the end faces at 25a [shown in figure 3]), the first chip (25) includes a first optical waveguide connected to the second optical waveguide (Figure 6: 56 is coupled 73 as shown in Figure 8), and a first bonding surface that is oblique to the first optical waveguide and is in contact with the second bonding surface (Figure 8: SOA 25 is fit within a recess and bonded to 70 [0035]; Figure 3: is a top view illustrates the ends faces are oblique hence the trench must be oblique in or to fit 25).
As for Claim 5, Sugiyama teaches the device of Claim 1, wherein the second chip (Figure 8: 70) includes a second optical waveguide (Figure 8: 73 contain waveguides 61), and a second oblique waveguide that is oblique to the second optical waveguide (Figure 6: 56 [0035]) and is connected to the second optical waveguide (Figure 8: waveguide within 25 is coupled to 73), the first chip (25) includes a first optical waveguide (Figure 6: 56a), and a first oblique waveguide (See Waveguide 61 coupled to 25 via its front end face 25b, wherein the endface are oblique to the horizontal waveguide in 30 thus 30 can be consider oblique to 56a-b due the inclined end face of 25) that is oblique to the first optical waveguide (61 on portion 30) and is connected to the second oblique waveguide (73 or 61 portion of 20 is connected to each other via 25).
As for Claim 6, Sugiyama teaches the device of Claim 1, wherein the first chip (25) is mounted face-down on the trench formed on the second chip (Figure 8: 25 and 70 at location of 25).
As for Claim 7, Sugiyama teaches the device of Claim 1, wherein the second chip (70) includes a thin-film LN (LiNbO3) crystal material (Figure 8: at 80 or Figure 3: 21; [0035]).
In terms of Claim 13, Sugiyama teaches an optical transmission device (Figure 8) comprising an optical modulator element (Figure 8: modulator module) that modulates light by using an electrical signal and transmits transmission light (Figure 8: modulator module; [0055]), wherein the optical modulator element incorporates an optical integrated device including a first chip (Figure 8: 25) including an optical circuit (Figure 8: 30), and a second chip (Figure 8: 70) including an optical waveguide (Figure 8: 61 or 85) including a material with an electro-optic effect larger than the electro-optic effect of a material of the first chip ([0035]), the first chip (25) is mounted in a trench formed on the second chip (Figure 8: 25 is mounted on 70 in a recess), and the first chip is optically coupled to the second chip by butt coupling (Figure 8: 20 and 70).
In terms of Claim 14, Sugiyama teaches an optical transceiver (Figure 8) comprising an optical modulator element (Figure 8: modulator module) that optically modulates light by using a transmission signal and transmits transmission light ([0055]), and an optical receiver element (Figure 8: 72) that receives a reception signal from received light by using light (Figure 8: 72 receives light from 15), wherein the optical modulator element incorporates an optical integrated device including a first chip (Figure 8: 25) including an optical circuit (Figure 8: 30), and a second chip (Figure 8: 70) including an optical waveguide (85 or 61) including a material with an electro-optic effect (within 21 or 85a-d) larger than the electro-optic effect of a material of the first chip (the optical effects of 20 must be larger than 25 otherwise the signal modulator 20 won’t be able to modulate effectively), the first chip (25) is mounted in a trench formed on the second chip, and the first chip is optically coupled to the second chip by butt coupling (Figure 8: 25 on 70 in a recess).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication to Sugiyama 2017/0033884US in view of the US Patent Application Publication to Makino 2022/0390775US.
In regards to Claim 8, Sugiyama teaches the optical integrated device according to claim 1, wherein a second optical waveguide (Figure 8: 61 within 73) in the second chip (Figure 8: 70) includes a second input waveguide (Figure 6: 73 couples to 56a-b) connected to the first chip (25), and a second output waveguide (Figure 6: 61 that couples to 25 via end face 25b) connected to the optical modulator (20) and to the first chip (25).
Sugiyama does not teach a folded waveguide that is folded back between the second input waveguide and the optical modulator to connect the second input waveguide and the optical modulator.
Makino teaches a folded waveguide (Figure 6: see WI and W2) that is folded back between the second input waveguide and the optical modulator to connect the second input waveguide and the optical modulator (Figure 6: W1 and W2 are fold around electrode arms 15a1 and 15b1 which function as modulating devices; claim 8). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Sugiyama to have folded waveguide configuration in order to reduce the width spacing required for the modulator. This makes the device a smaller form factor.
In regards to Claim 9, Sugiyama / Makino teaches the device of claim 8.
Sugiyama does not teach wherein the optical integrated device has a structure in which a diameter of the folded waveguide is longer than a spacing between the second input waveguide and the second output waveguide at a bonding portion where the first chip and the second chip are butt-coupled to each other.
Makino does teach wherein the optical integrated device has a structure in which a diameter of the folded waveguide (Figure 7: see l2) is longer than a spacing between the second input waveguide and the second output waveguide at a bonding portion (See L2 is longer than the spacing between W1 and W1).
Makino does not teach this relationship occurs where the first chip and the second chip are butt-coupled to each other.
It would have been an obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the dimension taught by Makino to occur at the location where the first chip and the second chip are butt coupled in order to optimize the coupling between the two waveguides of the first and second chips. This modification would have involved a mere change in the size of the component. A change of size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Sugiyama 2017/0033884US / Makino 2022/0390775US as applied to claim 8above, and further in view of Sugiyama 2019/0271896US.
In regards to Claim 10, Sugiyama ‘884 / Makino teaches the device of claim 8 wherein Suyigama teaches wherein a first optical waveguide in the first chip (25 contains waveguide 56a-b); a first output waveguide that connects an output side (Figure 3: 25b on end face couples to a waveguide 61 that output the signal from 25 to 30).
Sugiyama ‘884 and Makino does not teach wherein the waveguides are coupled to side input/output fibers.
Suyiyama ‘896 teaches a folded modulator wherein the folded waveguides are coupled to a fiber output /inputs via the side ports. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Sugiyama ‘884 to couple to optical fiber in order to connect the modulator to external devices.
Sugiyama ‘884 / Makino / Suyiyama ‘896 do not teach and the optical integrated device has a structure in which a spacing between the second input waveguide and the second output waveguide at a bonding portion where the first chip and the second chip are butt-coupled to each other is smaller than a spacing between the first input waveguide and the first output waveguide on a bonding surface between the input-side optical fiber and the output-side optical fiber.
It would have been an obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the dimension spacing where the first chip and the second chip are butt coupled to be smaller relative to input side optical fiber and output side optical fiber in order to optimize the coupling between the two waveguides of the first and second chips along with the fiber ports. Further making the spacing will also reduce the footprint waveguides coupling location and allow for more denser connections or to produce a smaller foot print coupling area. This modification would have involved a mere change in the size of the component. A change of size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Claim 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Sugiyama 2017/0033884US / Makino 2022/0390775US as applied to claim 8above, and further in view of Sugiyama 2019/0372664US.
In regards to Claims 11 and 12, Sugiyama ‘884 / Makino teaches the device of Claim 8.
Sugiyama ‘884 / Makino do not teach wherein the first chip includes a reflective mirror, the second chip includes a third optical waveguide that is connected to the reflective mirror, and a coupler that is connected to the third optical waveguide, and when test light is input from the coupler to the third optical waveguide, the reflective mirror reflects reflected light for the input test light to the coupler; and wherein the second chip includes a fourth optical waveguide, a first coupler that is connected to the fourth optical waveguide, and a first reflective mirror that is connected to the fourth optical waveguide, and when test light is input from the first coupler to the fourth optical waveguide, the first reflective mirror reflects reflected light for the input test light to the first coupler.
Sugiyama ‘664 teaches multiple chip configurate (Figure 1: area of 101 which contains 4 different chips define in each area of 101). The chips contain GC 121/123 in test area coupled to each chips wherein the GC are coupled to the chip via waveguides (Figure 1: 109-3) for the purpose of testing each signal input/output. This provides data to ensure the that modulator or other optical components are output the right signal ([0095]). Sugiyama further indicates that instead of grating couplers GC these devices can be mirrors or reflectors thus meeting the limitation of 3rd waveguide and 4th waveguide coupled to mirror or reflectors to test the input signals. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Sugiyama ‘884 to include mirror reflectors and waveguide on each chip in order to test the optical signal.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent Application Publication to Doi 2018/0120670US teaches using branch shape waveguides as modulators.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOANG Q TRAN whose telephone number is (571)272-5049. The examiner can normally be reached 9:30 am - 5:30pm Monday - Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at 5712722397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HOANG Q TRAN/Examiner, Art Unit 2874
/UYEN CHAU N LE/Supervisory Patent Examiner, Art Unit 2874
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