CTNF 18/662,577 CTNF 89933 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority 02-26 AIA Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 2-14 17 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1, 15, 16, 18 and 19 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Pandey et al., US Patent Application (20240222496), hereinafter “Pandey” . Regarding claim 1 Pandey teaches an electronic device FIG. 5 shows a semiconductor device [Pandey para 0060] comprising: a semiconductor body of silicon carbide the device may be silicon carbide (SiC) based [Pandey para 0040] having an upper surface and a lower surface opposite to each other along a first axis and including: a drain substrate a drain or substrate, is formed under the n-drift region [Pandey para 0061] extending into the semiconductor body starting from the lower surface of the semiconductor body and having a first electrical conductivity type and a first dopant concentration the device may include a drain or collector region located underneath the drift region 105. The device 100 includes two gate trenches 120 extending downwardly into the n-drift region 105 from an upper surface of an n+ contact region 115. During operation, a conduction channel is formed between the n+ contact region 115 and the drift region 105 by application of a positive voltage to the gate [Pandey para 0041 ] a drift layer extending into the semiconductor body forming a drift region of a first conductivity type, forming a body region of a second conductivity type over the drift region, [Pandey para 0029] starting from the upper surface of the semiconductor body and up to the drain substrate A collector layer 450, also referred to as a drain or substrate, is formed under the n-drift region 105 . [Pandey para 0061 and see Fig. 5]; and having the first electrical conductivity type and a second dopant concentration lower than the first dopant concentration f orming a contact region of a first conductivity type located in the mesa region and disposed over the body region, wherein the contact region has a higher doping concentration compared to a doping concentration of the drift region, [Pandey para 0029]; at least one first body region which extends into the semiconductor body starting from the upper surface of the semiconductor body and at a distance from the drain substrate, Above the n-drift region 105, and adjacent to the gate trenches 120, there is a provided a p-body region 110. The p-body region 110 is a p-type doped semiconductor and generally extends to a depth in the device which generally corresponds with the depth of the gate conductive region 140 . [Pandey para 0042 and see Fig. 5]; is accommodated in the drift layer and has a second electrical conductivity type opposite to the first electrical conductivity type; The p-body region 110 is a p-type doped semiconductor and generally extends to a depth in the device which generally corresponds with the depth of the gate conductive region 140. [Pandey para 0061 and see Fig. 5]; and at least one first source region which extends into the semiconductor body starting from the upper surface of the semiconductor body, and has the first electrical conductivity type The source contact 155 extends above an upper surface of the n+ contact region 115 and is electrically connected to a source contact layer 420. [Pandey para 0062 and see Fig. 5] is accommodated in the first body region so as to be spaced from the drift layer Multiple source contacts 155 may be provided between two gate trenches 120, spaced from each other in the z-direction [Pandey para 0047 and see Fig. 5]; at least one first gate structure extending on the upper surface of the semiconductor body and superimposed along the first axis on the first body region in such a way as to form, The device 100 includes two gate trenches 120 extending downwardly into the n-drift region 105 from an upper surface of an n+ contact region 115. [Pandey para 0041 and see Fig. 5] with the first source region, source contact 155 [Pandey see Fig. 5] the first body region, p-body region 110 [Pandey see Fig. 5] t he drift layer the n-drift region 105 . [ see Fig. 5] and the drain substrate, A collector layer 450, also referred to as a drain or substrate, [ see Fig. 5] a first MOSFET portion of a first MOSFET, the device is a silicon based trench-gate MOSFET [Pandey para 0040 and see Fig. 5]; wherein the semiconductor body further includes at least one first doped pocket region which is buried in the drift layer, has the second electrical conductivity type and is at least partially aligned along the first axis with the first source region and/or with the first gate structure The device 100 includes two gate trenches 120 extending downwardly into the n-drift region 105 from an upper surface of an n+ contact region 115. During operation, a conduction channel is formed between the n+ contact region 115 and the drift region 105 by application of a positive voltage to the gate [Pandey para 0041 and see Fig. 5]; PNG media_image1.png 471 433 media_image1.png Greyscale Regarding claim 15 Pandey teaches an electronic device, FIG. 5 shows a semiconductor device [Pandey para 0060] comprising: a semiconductor body of silicon carbide the device may be silicon carbide (SiC) based [Pandey para 0040] and including: a drain substrate a drain or substrate, is formed under the n-drift region [Pandey para 0061] of a first conductivity type and a first dopant concentration f orming a contact region of a first conductivity type located in the mesa region and disposed over the body region, wherein the contact region has a higher doping concentration compared to a doping concentration of the drift region, [Pandey para 0029]; a drift layer above the drain substrate and having the first electrical conductivity type forming a drift region of a first conductivity type, forming a body region of a second conductivity type over the drift region, [Pandey para 0029] and a second dopant concentration lower than the first dopant concentration forming a contact region of a first conductivity type located in the mesa region and disposed over the body region, wherein the contact region has a higher doping concentration compared to a doping concentration of the drift region, [Pandey para 0029]; a body region having a top surface that is coplanar with a top surface of the drift layer and is separated from the drain substrate by the drift layer and has a second electrical conductivity type opposite to the first electrical conductivity type Above the n-drift region 105, and adjacent to the gate trenches 120, there is a provided a p-body region 110. The p-body region 110 is a p-type doped semiconductor and generally extends to a depth in the device which generally corresponds with the depth of the gate conductive region 140 . [Pandey para 0042 and see Fig. 5]; a source region embedded in the body region and separated from the drift layer by the body region and having the first electrical conductivity type The source contact 155 extends above an upper surface of the n+ contact region 115 and is electrically connected to a source contact layer 420. [Pandey para 0062 and see Fig. 5] Multiple source contacts 155 may be provided between two gate trenches 120, spaced from each other in the z-direction [Pandey para 0047 and see Fig. 5]; and a first doped pocket region of the second electrical conductivity type embedded in the drift layer and having a top surface lower than a bottom surface of the body region and a bottom surface higher than a top surface of the drain substrate The device 100 includes two gate trenches 120 extending downwardly into the n-drift region 105 from an upper surface of an n+ contact region 115. During operation, a conduction channel is formed between the n+ contact region 115 and the drift region 105 by application of a positive voltage to the gate [Pandey para 0041 and see Fig. 5]; a gate structure directly above at least a portion first body region and at least a portion of the first doped pocket region, The device 100 includes two gate trenches 120 extending downwardly into the n-drift region 105 from an upper surface of an n+ contact region 115. [Pandey para 0041 and see Fig. 5] the source region, source contact 155 [Pandey see Fig. 5 the body region, p-body region 110 [Pandey see Fig. 5] t he drift layer the n-drift region 105 . [ see Fig. 5] the drift layer the n-drift region 105 . [ see Fig. 5] and the drain substrate A collector layer 450, also referred to as a drain or substrate, [ see Fig. 5] forming a MOSFET. the device is a silicon based trench-gate MOSFET [Pandey para 0040 and see Fig. 5] Regarding claim 16 Pandey teaches claim 15 in addition Pandey teaches wherein the first doped pocked region and the gate structure are aligned on a same vertical axis. [Pandey and see Fig. 5] Regarding claim 18 Pandey teaches a method of forming an electronic device, FIG. 5 shows a semiconductor device [Pandey para 0060] comprising: forming a semiconductor body of silicon carbide the device may be silicon carbide (SiC) based [Pandey para 0040] : forming a drain substrate of a MOSFET a drain or substrate, is formed under the n-drift region [Pandey para 0061] of a first conductivity type and a first dopant concentration in the semiconductor body the device may include a drain or collector region located underneath the drift region 105. The device 100 includes two gate trenches 120 extending downwardly into the n-drift region 105 from an upper surface of an n+ contact region 115. During operation, a conduction channel is formed between the n+ contact region 115 and the drift region 105 by application of a positive voltage to the gate [Pandey para 0041 ]; forming a drift layer of the MOSFET in the semiconductor body above the drain substrate and having the first electrical conductivity type and a second dopant concentration lower than the first dopant concentration forming a drift region of a first conductivity type, forming a body region of a second conductivity type over the drift region, [Pandey para 0029] f orming a contact region of a first conductivity type located in the mesa region and disposed over the body region, wherein the contact region has a higher doping concentration compared to a doping concentration of the drift region, [Pandey para 0029] ; forming a body region of the MOSFET in the semiconductor body forming a drift region of a first conductivity type, forming a body region of a second conductivity type over the drift region, [Pandey para 0029] having a top surface that is coplanar with a top surface of the drift layer A collector layer 450, also referred to as a drain or substrate, is formed under the n-drift region 105 . [Pandey para 0061 and see Fig. 5] and is separated from the drain substrate by the drift layer Above the n-drift region 105, and adjacent to the gate trenches 120, there is a provided a p-body region 110. The p-body region 110 is a p-type doped semiconductor and generally extends to a depth in the device which generally corresponds with the depth of the gate conductive region 140 . [Pandey para 0042 and see Fig. 5] and has a second electrical conductivity type opposite to the first electrical conductivity type The p-body region 110 is a p-type doped semiconductor and generally extends to a depth in the device which generally corresponds with the depth of the gate conductive region 140. [Pandey para 0061 and see Fig. 5]; forming a source region of the MOSFET embedded in the body region and separated from the drift layer by the body region and having the first electrical conductivity type The source contact 155 extends above an upper surface of the n+ contact region 115 and is electrically connected to a source contact layer 420. [Pandey para 0062 and see Fig. 5] ; forming a first doped pocket region of the second electrical conductivity type embedded in the drift layer and having a top surface lower than a bottom surface of the body region and a bottom surface higher than a top surface of the drain substrate The device 100 includes two gate trenches 120 extending downwardly into the n-drift region 105 from an upper surface of an n+ contact region 115. During operation, a conduction channel is formed between the n+ contact region 115 and the drift region 105 by application of a positive voltage to the gate [Pandey para 0041 and see Fig. 5] ; and forming a gate structure of the MOSFET directly above at least a portion first body region and at least a portion of the first doped pocket region. The device 100 includes two gate trenches 120 extending downwardly into the n-drift region 105 from an upper surface of an n+ contact region 115. [Pandey para 0041 and see Fig. 5] Regarding claim 19 Pandey teaches claim 18 in addition Pandey teaches wherein the first doped pocked region and the gate structure are aligned on a same vertical axis. [Pandey and see Fig. 5] Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT J MICHAUD whose telephone number is (571)270-3981. The examiner can normally be reached 8:30 - 5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Patrick Edouard can be reached on 571-272-7603. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ROBERT J MICHAUD/Examiner, Art Unit 2622 Application/Control Number: 18/662,577 Page 2 Art Unit: 2622 Application/Control Number: 18/662,577 Page 3 Art Unit: 2622 Application/Control Number: 18/662,577 Page 4 Art Unit: 2622 Application/Control Number: 18/662,577 Page 5 Art Unit: 2622 Application/Control Number: 18/662,577 Page 6 Art Unit: 2622 Application/Control Number: 18/662,577 Page 7 Art Unit: 2622 Application/Control Number: 18/662,577 Page 8 Art Unit: 2622 Application/Control Number: 18/662,577 Page 9 Art Unit: 2622
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