DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
1. This Office Action is in response to Amendment filed on date: 7/22/2026.
Claims 1-20 are currently pending.
Claims 1-2, 11-12 and 20 have been amended.
Claims 1, 11, and 20 are independent claims.
Response to Arguments
2. Applicant's arguments, see in pages 7-10 in the submitted Remarks, filed on 7/22/2026, with respect to the rejection on claims 1-20 have been fully considered but are moot in view of the new ground(s) of rejection.
Examiner Notes
3. Examiner cites particular paragraphs, columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1-5, 11-15 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Jain et al. (US. Pub. 2025/0110174: hereafter “Jain”) in view of Shimizu et al. (US. Pub. 2018/0136276; hereinafter “Shimizu”) and further in view of Boone et al. (US Pat. 11474576; hereinafter “Boone”).
Regarding claim 1, Jain discloses a method for active thermal control (ATC) of an integrated circuit (IC) (an integrated circuit 200 in Fig. 2A, such as a die in Fig. 1) during a testing procedure (a method for thermal testing within an integrated circuit IC, see abstract), the method comprising: obtaining a plurality of temperature measurements of a die (102 in Fig. 1 or 200 in Fig. 2A) of the IC (a die package 100 in Fig. 1), the plurality of temperature measurements being provided by a plurality of temperature sensors (temperature sensors 150 in Fig. 1 or 230 in Fig. 2A) integrated with the die of the IC (“The die 102 may also include a processor electrically coupled to the temperature controller. The processor can request and receive from the temperature controller the thermal data for each heat detection element 150, and may determine an operating temperature for each heat detection element 150 based on the corresponding thermal data” in para. [0022]; or “a processor 206 is electrically coupled to temperature controller 236, and can receive thermal data for each of the heat detection elements 230 from temperature controller 236” in [0030-31] ); and controlling, based on the plurality of temperature measurements, a temperature forcing system to implement ATC of the IC by: supplying, based on the plurality of temperature measurements multiple heat generating elements 210 in Fig. 2B) of the temperature forcing system (“an electronic component 102 or 200 is activated, and an operating performance value of the electronic component is determined. The operating performance value may then be compared to a threshold performance value to determine whether the electronic component is operating properly at the corresponding temperature. For instance, one or more heat generating elements 210 may be activated as described herein until processor 206 measures a particular temperature from a corresponding heat detection element 230” in [0044], also see [0018-19, 22, 41, 52]), or removing, based on the plurality of temperature measurements indicating a temperature exceeding the desired test temperature range, heat from the IC by a heat sink of the temperature forcing system.
Jain does not explicitly specify that supplying, based on the plurality of temperature measurements indicating a temperature that falls below a desired test temperature range, heat to the IC from a heat source of the temperature forcing system. Shimizu discloses a temperature measurement and inspection system (in Fig. 2) comprising a temperature control portion (3) coupled to heat generators (123, 114, 115) and temperature sensors (125,118, 119), the heat generators and temperature sensors disposed surrounding an IC 22 under tested, wherein the temperature controller controls supplying, based on the plurality of temperature measurements indicating a temperature that falls below a desired test temperature range, heat to the IC from a heat source of the temperature forcing system (“it is possible to compute the heat generation temperature of the hand heater 123 on the basis of the difference between the computed IC temperature TIC and the target temperature and control the heat generation temperature of the hand heater 123 so that the computed IC temperature TIC reaches the target temperature….”, see at least in [0106]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the thermal testing apparatus of Jain by supplying heat to the IC based on the plurality of temperature measurements indicating a temperature that falls below a desired test temperature range as taught by Shimizu for purpose of the failure of the electronic components due to overheating is prevented and the accurate computation of the heat is ensured (see the summary). Jain and Shimizu do not explicitly specify that a plurality of temperature sensors embedded in the die. Boone discloses, Figs. 1A-1F and 2, an electrical device (100) with thermally controlled performance, comprising a die (102) and a plurality of temperature sensors (108) embedded in the die (“a plurality of temperature sensors 108 are disposed upon or at least partially embedded within the die 102….” from Col. 6, lines 17-25). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the thermal testing apparatus of Jain and Shimizu by having a plurality of temperature sensors embedded in the die as taught by Boone for purpose of providing a plurality of temperature sensors and a controller embedded within the die, and thus enables to accurately control thermal loads and distribution within the die.
Regarding claim 2, Jain and Shimizu and Boone disclose the method according to claim 1, Jain further teaches wherein the testing procedure is a system level test (SLT) (see Figs. 2A-B), and wherein the IC is a graphics processing unit (GPU) (“Each processor 206 may be, for example, a graphical processing unit (GPU)…”, see [0027]) comprising a substrate (108 in Fig. 1) and a die (102), the die comprising a plurality of compute units (a system-on-chip 212, CPU 206, temperature controller 236, memory 208, electrical components 220… see Figs. 2A-B), each respective compute unit having integrated therewith a respective temperature sensor (230) of the plurality of temperature sensors (see Fig. 2A).
Regarding claim 3, Jain and Shimizu and Boone disclose the method according to claim 2, Jain further teaches wherein each respective temperature sensor of the plurality of temperatures sensors is an analog temperature sensor (heat detection elements 230 (i.e., temperature sensors) can be thermistors such as thermal diodes, see [0030]).
Regarding claim 4, Jain and Shimizu and Boone disclose the method according to claim 3, Jain further teaches wherein each analog temperature sensor is a semiconductor-based temperature sensor (see [0030]). Regarding claim 5, Jain and Shimizu and Boone disclose the method according to claim 3, Jain further teaches wherein each analog temperature sensor is one of: a diode temperature sensor configured to utilize a temperature-dependent voltage drop across a diode junction to measure temperature, a bandgap temperature sensor configured to utilize a temperature-dependent bandgap voltage to measure temperature, a resistance temperature detector (RTD) configured to utilize a temperature-dependent resistor to measure temperature, or a thermocouple (see [0030]).
Regarding claim 11, Jain discloses a system for active thermal control (ATC) of an integrated circuit (IC) during a testing procedure (a method for thermal testing within an integrated circuit IC, see abstract), the system comprising: a temperature forcing system (a thermal control system in Fig. 2A-2B) comprising a heat source (a multiple of heat sources 210) and a heat sink (a heatsink 120 in Fig. 1); and a processor (such as a processor 206 with a temperature controller 236 in Fig. 2A) configured to: obtain a plurality of temperature measurements of a die (102 in Fig. 1 or 200 in Fig. 2A) of the IC (a die package 100 in Fig. 1), the plurality of temperature measurements being provided by a plurality of temperature sensors (temperature sensors 150 in Fig. 1 or 230 in Fig. 2A) integrated with the die of the IC (“The die 102 may also include a processor electrically coupled to the temperature controller. The processor can request and receive from the temperature controller the thermal data for each heat detection element 150, and may determine an operating temperature for each heat detection element 150 based on the corresponding thermal data” in para. [0022]; or “a processor 206 is electrically coupled to temperature controller 236, and can receive thermal data for each of the heat detection elements 230 from temperature controller 236” in [0030-31] ); and control, based on the plurality of temperature measurements, the temperature forcing system to implement ATC of the IC by: instructing, based on the plurality of temperature measurements an electronic component 102 or 200 is activated, and an operating performance value of the electronic component is determined. The operating performance value may then be compared to a threshold performance value to determine whether the electronic component is operating properly at the corresponding temperature. For instance, one or more heat generating elements 210 may be activated as described herein until processor 206 measures a particular temperature from a corresponding heat detection element 230” in [0044], also see [0018-19, 22, 41, 52]), or instructing, based on the plurality of temperature measurements indicating a temperature that exceeds the desired test temperature range, the temperature forcing system to remove heat from the IC.
Jain does not explicitly specify that supplying, based on the plurality of temperature measurements indicating a temperature that falls below a desired test temperature range, heat to the IC from a heat source of the temperature forcing system. Shimizu discloses a temperature measurement and inspection system (in Fig. 2) comprising a temperature control portion (3) coupled to heat generators (123, 114, 115) and temperature sensors (125,118, 119), the heat generators and temperature sensors disposed surrounding an IC 22 under tested, wherein the temperature controller controls supplying, based on the plurality of temperature measurements indicating a temperature that falls below a desired test temperature range, heat to the IC from a heat source of the temperature forcing system (“it is possible to compute the heat generation temperature of the hand heater 123 on the basis of the difference between the computed IC temperature TIC and the target temperature and control the heat generation temperature of the hand heater 123 so that the computed IC temperature TIC reaches the target temperature….”, see at least in [0106]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the thermal testing apparatus of Jain by supplying heat to the IC based on the plurality of temperature measurements indicating a temperature that falls below a desired test temperature range as taught by Shimizu for purpose of the failure of the electronic components due to overheating is prevented and the accurate computation of the heat is ensured (see the summary).
Jain and Shimizu do not explicitly specify that a plurality of temperature sensors embedded in the die. Boone discloses, Figs. 1A-1F and 2, an electrical device (100) with thermally controlled performance, comprising a die (102) and a plurality of temperature sensors (108) embedded in the die (“a plurality of temperature sensors 108 are disposed upon or at least partially embedded within the die 102….” from Col. 6, lines 17-25). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the thermal testing apparatus of Jain and Shimizu by having a plurality of temperature sensors embedded in the die as taught by Boone for purpose of providing a plurality of temperature sensors and a controller embedded within the die, and thus enables to accurately control thermal loads and distribution within the die.
Regarding claim 12, Jain and Shimizu and Boone disclose the system according to claim 11, Jain further teaches wherein the testing procedure is a system level test (SLT) (see Figs. 2A-B), and wherein the IC is a graphics processing unit (GPU) (“Each processor 206 may be, for example, a graphical processing unit (GPU)…”, see [0027]) comprising a substrate and a die (102), the die comprising a plurality of compute units (a system-on-chip 212, CPU 206, temperature controller 236, memory 208, electrical components 220… see Figs. 2A-B), each respective compute unit having integrated therewith a respective temperature sensor (230) of the plurality of temperature sensors (see Fig. 2A).
Regarding claim 13, Jain and Shimizu and Boone disclose the system according to claim 11, Jain further teaches wherein each respective temperature sensor of the plurality of temperatures sensors is an analog temperature sensor (heat detection elements 230 (i.e., temperature sensors) can be thermistors such as thermal diodes, see [0030]).
Regarding claim 14, Jain and Shimizu and Boone disclose the system according to claim 13, Jain further teaches wherein each analog temperature sensor is a semiconductor-based temperature sensor (see [0030]).
Regarding claim 15, Jain and Shimizu and Boone disclose the system according to claim 13, Jain further teaches wherein each analog temperature sensor is one of: a diode temperature sensor configured to utilize a temperature-dependent voltage drop across a diode junction to measure temperature, a bandgap temperature sensor configured to utilize a temperature-dependent bandgap voltage to measure temperature, a resistance temperature detector (RTD) configured to utilize a temperature-dependent resistor to measure temperature, or a thermocouple (see [0030]).
Regarding claim 20, Jain discloses Non-transitory computer-readable media storing computer instructions for active thermal control (ATC) of an integrated circuit (IC) (an integrated circuit 200 in Fig. 2A, such as a die in Fig. 1) during a testing procedure that, when executed by one or more processors, cause the one or more processors to perform a method (a non-transitory machine-readable storage medium comprises instructions that, when executed by at least one processor, cause the at least one processor to perform operations of a method for thermal testing within an integrated circuit IC, see [0005]) comprising: obtaining a plurality of temperature measurements of a die (102 in Fig. 1 or 200 in Fig. 2A) of the IC (a die package 100 in Fig. 1), the plurality of temperature measurements being provided by a plurality of temperature sensors (temperature sensors 150 in Fig. 1 or 230 in Fig. 2A) integrated with the die of the IC; (“The die 102 may also include a processor electrically coupled to the temperature controller. The processor can request and receive from the temperature controller the thermal data for each heat detection element 150, and may determine an operating temperature for each heat detection element 150 based on the corresponding thermal data” in para. [0022]; or “a processor 206 is electrically coupled to temperature controller 236, and can receive thermal data for each of the heat detection elements 230 from temperature controller 236” in [0030-31] ) and controlling, based on the plurality of temperature measurements, a temperature forcing system to implement ATC of the IC by: supplying, based on the plurality of temperature measurements multiple heat generating elements 210 in Fig. 2B) of the temperature forcing system (“an electronic component 102 or 200 is activated, and an operating performance value of the electronic component is determined. The operating performance value may then be compared to a threshold performance value to determine whether the electronic component is operating properly at the corresponding temperature. For instance, one or more heat generating elements 210 may be activated as described herein until processor 206 measures a particular temperature from a corresponding heat detection element 230” in [0044], also see [0018-19, 22, 41, 52]), or removing, based on the plurality of temperature measurements indicating a temperature exceeding the desired test temperature range, heat from the IC by a heat sink of the temperature forcing system.
Jain does not explicitly specify that supplying, based on the plurality of temperature measurements indicating a temperature that falls below a desired test temperature range, heat to the IC from a heat source of the temperature forcing system. Shimizu discloses a temperature measurement and inspection system (in Fig. 2) comprising a temperature control portion (3) coupled to heat generators (123, 114, 115) and temperature sensors (125,118, 119), the heat generators and temperature sensors disposed surrounding an IC 22 under tested, wherein the temperature controller controls supplying, based on the plurality of temperature measurements indicating a temperature that falls below a desired test temperature range, heat to the IC from a heat source of the temperature forcing system (“it is possible to compute the heat generation temperature of the hand heater 123 on the basis of the difference between the computed IC temperature TIC and the target temperature and control the heat generation temperature of the hand heater 123 so that the computed IC temperature TIC reaches the target temperature….”, see at least in [0106]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the thermal testing apparatus of Jain by supplying heat to the IC based on the plurality of temperature measurements indicating a temperature that falls below a desired test temperature range as taught by Shimizu for purpose of the failure of the electronic components due to overheating is prevented and the accurate computation of the heat is ensured (see the summary).
Jain and Shimizu do not explicitly specify that a plurality of temperature sensors embedded in the die. Boone discloses, Figs. 1A-1F and 2, an electrical device (100) with thermally controlled performance, comprising a die (102) and a plurality of temperature sensors (108) embedded in the die (“a plurality of temperature sensors 108 are disposed upon or at least partially embedded within the die 102….” from Col. 6, lines 17-25). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the thermal testing apparatus of Jain and Shimizu by having a plurality of temperature sensors embedded in the die as taught by Boone for purpose of providing a plurality of temperature sensors and a controller embedded within the die, and thus enables to accurately control thermal loads and distribution within the die.
6. Claims 7-8 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Jain in view of Shimizu and Boone and further in view of Kon et al. (US. Pub. 2006/0290366; hereinafter “Kon”).
Regarding claim 7, Jain and Shimizu and Boone disclose the method according to claim 1, except for explicitly specifying wherein the obtaining the plurality of temperature measurements of the temperature of the die of the IC is performed periodically with a frequency in a range of 5 to 30 Hz, and wherein the controlling, based on the plurality of temperature measurements, the temperature forcing system to implement ATC of the IC is performed by periodically outputting a control signal with a frequency in a range of 5 to 30 Hz.
Kon discloses, in Figs. 1-3, a monitoring system for multiple electronic devices under test, comprises a test board 102 with multiple sockets for receiving multiple dice, each of sockets receiving a single die 112, a plurality of temperature sensors 110 each monitors a temperature for each die, wherein the system configured to obtain the plurality of temperature measurements of the temperature of the die of the IC is performed periodically with a frequency in a range of 5 to 30 Hz, and wherein the controlling, based on the plurality of temperature measurements, the temperature forcing system to implement ATC of the IC is performed by periodically outputting a control signal with a frequency in a range of 5 to 30 Hz (see [0016, 34]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the thermal testing apparatus of Jain and Shimizu and Boone by obtaining the plurality of temperature measurements of the temperature of the die of the IC is performed periodically with a frequency in a range of 5 to 30 Hz, and wherein the controlling, based on the plurality of temperature measurements, the temperature forcing system to implement ATC of the IC is performed by periodically outputting a control signal with a frequency in a range of 5 to 30 Hz as taught by Kon for purpose of providing sensor selection circuitry provides a fast stream of accurate temperature measurement outputs for monitoring the devices under test (see the summary).
Regarding claim 8, Jain and Shimizu and Boone and Kon disclose the method according to claim 7, Kon further teaches wherein the obtaining the plurality of temperature measurements is performed periodically with a frequency in a range of 10 to 20 Hz, and wherein the controlling the temperature forcing system to implement ATC of the IC is performed by periodically outputting a control signal with a frequency in a range of 10 to 20 Hz (see [0016, 34]).
Regarding claim 17, Jain and Shimizu and Boone disclose the system according to claim 11, except for explicitly specifying that wherein the processor is configured to control, based on the plurality of temperature measurements, the temperature forcing system to implement ATC of the IC by periodically outputting a control signal with a frequency in a range of 5 to 30 Hz. Kon discloses, in Figs. 1-3, a monitoring system for multiple electronic devices under test, comprises a test board 102 with multiple sockets for receiving multiple dice, each of sockets receiving a single die 112, a plurality of temperature sensors 110 each monitors a temperature for each die, wherein the system configured to obtain the plurality of temperature measurements of the temperature of the die of the IC is performed periodically with a frequency in a range of 5 to 30 Hz, and wherein the controlling, based on the plurality of temperature measurements, the temperature forcing system to implement ATC of the IC is performed by periodically outputting a control signal with a frequency in a range of 5 to 30 Hz (see [0016, 34]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the thermal testing apparatus of Jain and Shimizu and Boone by obtaining the plurality of temperature measurements of the temperature of the die of the IC is performed periodically with a frequency in a range of 5 to 30 Hz, and wherein the controlling, based on the plurality of temperature measurements, the temperature forcing system to implement ATC of the IC is performed by periodically outputting a control signal with a frequency in a range of 5 to 30 Hz as taught by Kon for purpose of providing sensor selection circuitry provides a fast stream of accurate temperature measurement outputs for monitoring the devices under test (see the summary).
Regarding claim 18, Jain and Shimizu and Boone and Kon disclose the system according to claim 17, Kon further teaches wherein the processor is configured to control the temperature forcing system to implement ATC of the IC by periodically outputting a control signal with a frequency in a range of 10 to 20 Hz (see [0016, 34]).
7. Claims 9-10 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Jain in view of Shimizu and further in view of Boone.
Regarding claim 9, Jain and Shimizu disclose the method according to claim 3, Jain further teaches wherein each respective temperature sensor (230) is configured to measure a temperature of a respective region of the IC (as shown in Fig. 2A, the plurality of temperature sensors 230, each of the temperature sensors 230 is configured to measure temperature of a respective region of the IC 200).
Jain and Shimizu and Boone do not explicitly specify that each respective region having an area in a range of 10-50 mm2. However specifically arranging each respective temperature sensor for measuring a temperature of a respective region of the IC and each respective region having an area in a range of 10-50 mm2 is a known practice in the art and an area in a range of 10-50 mm2 would simply be a matter of inventor design choice.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the thermal testing apparatus of Jain and Shimizu and Boone by arranging each respective temperature sensor for measuring a temperature of a respective region of the IC and each respective region having an area in a range of 10-50 mm2, in order to meet the system design and specification requirement.
Regarding claim 10, Jain and Shimizu and Boone disclose the method according to claim 9, except explicitly specifying wherein each respective region has an area in a range of 15-25 mm2.
However specifically arranging each respective temperature sensor for measuring a temperature of a respective region of the IC and each respective region having an area in a range of 15-25 mm2 is a known practice in the art and an area in a range of 10-50 mm2 would simply be a matter of inventor design choice.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the thermal testing apparatus of Jain and Shimizu and Boone by arranging each respective temperature sensor for measuring a temperature of a respective region of the IC and each respective region having an area in a range of 15-25 mm2, in order to meet the system design and specification requirement.
Regarding claim 19, Jain and Shimizu and Boone disclose the system according to claim 13, Jain further teaches wherein each respective temperature sensor is configured to measure a temperature of a respective region of the I(as shown in Fig. 2A, the plurality of temperature sensors 230, each of the temperature sensors 230 is configured to measures temperature of a respective region of the IC 200).
Jain and Shimizu do not explicitly specify that each respective region having an area in a range of 10-50 mm2. However specifically arranging each respective temperature sensor for measuring a temperature of a respective region of the IC and each respective region having an area in a range of 10-50 mm2 is a known practice in the art and an area in a range of 10-50 mm2 would simply be a matter of inventor design choice.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the thermal testing apparatus of Jain and Shimizu by arranging each respective temperature sensor for measuring a temperature of a respective region of the IC and each respective region having an area in a range of 10-50 mm2, in order to meet the system design and specification requirement.
Allowable Subject Matter
8. Claims 6 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 6, the cited references, alone or in combination, do not disclose nor fairly suggest:
“ … the controlling, based on the plurality of temperature measurements, the temperature forcing system to implement ATC of the IC comprises determining, from the plurality of temperature measurements, a maximum value of the temperature of the die of the IC, wherein the plurality of temperature measurements indicate a temperature that falls below the desired test temperature range based on the maximum value of the temperature of the die of the IC falling below the desired test temperature range, and wherein the plurality of temperature measurements indicate a temperature exceeding the desired test temperature range based on the maximum value of the temperature of the die of the IC exceeding the desired test temperature range” as claimed in claim 1.
Regarding claim 16, the cited references, alone or in combination, do not disclose nor fairly suggest:
“ wherein the processor is further configured to control, based on the plurality of temperature measurements, the temperature forcing system to implement ATC of the IC by determining, from the plurality of temperature measurements, a maximum value of the temperature of the die of the IC, wherein the plurality of temperature measurements indicate a temperature that falls below the desired test temperature range based on the maximum value of the temperature of the die of the IC falling below the desired test temperature range, and wherein the plurality of temperature measurements indicate a temperature exceeding the desired test temperature range based on the maximum value of the temperature of the die of the IC exceeding the desired test temperature range” as claimed in claim 11.
Conclusion
9. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANG LE whose telephone number is (571)272-9349. The examiner can normally be reached on Monday thru Friday 7:30AM-5:00PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached on (571) 272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/THANG X LE/Primary Examiner, Art Unit 2858
10/1/2026
