Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the Request for Continued Examination (RCE) and the amendment filed July 30, 2026. Entry of the RCE under 37 CFR 1.114 withdraws the finality of the Office Action mailed May 20, 2026, and the amendment filed July 30, 2026 has been entered and considered.
This application has been examined. Claims 1-22 are pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art t which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-22 are rejected under AIA 35 U.S.C. § 103 as being unpatentable over Shin et al. (“Shin”) (US Pub No. 2019/0180809) in view of Bloemer et al. (“Bloemer”) (US 11,861,229).
In order to expedite and avoid piecemeal prosecution, the following rejection is made to the extent that the claims are understood, by considering those elements which are understood and interpreting their function in a manner which is consistent with the recited goals of the claims, and then applying the best available art.
The examiner relies on the entire teachings of Shin and Bloemer references; the applicant should carefully consider the entire teachings of the above-mentioned references to better understand the examiner’s position.
In regard to claims 1, 8, 15, Shin et al. disclose a memory device (item 200 of figure 1), a method and the system, comprising: a memory controller (item 100 of figure 1) configured to generate a data clock signal (i.e. WCK) (as shown in Fig. 1, which is reproduced below for ease of reference and convenience, Shin discloses the memory controller 100 may provide data clocks WCK and WCK# to the semiconductor memory device 200. The data clocks WCK and WCK# may be provided through a port P20 in the form of differential signals with complementary phases. See ¶ 47-48);
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and a memory device (item 200 of figure 1) coupled to the memory controller, the memory device configured to: receive the data clock signal from the memory controller (in Shin, the data clocks WCK and WCK# may be provided through a port P20 in the form of differential signals with complementary phases. See ¶ 47); and generate a system clock signal based on the data clock signal received or provide from the memory controller (in Shin, the internal data clock generating circuit 220 may adjust phase to synchronize the second clock WCK (i.e. data clock), having a clock frequency higher than the first clock, with the first clock being the system clock CK. A phase synchronization operation of the internal data clock generating circuit 220 may be performed as a hidden operation of a normal memory operation (a read or write operation) within a column address strobe latency (CL). See ¶ 47-52). Shin does not expressly disclose wherein the system clock signal is not received at the memory device from the memory controller that because in Shin the memory device additionally receives the system clock CK from the controller through port P10 (Shin ¶ 0047). In the same field of endeavor, Bloemer teaches the DRAM clocking architecture in which the memory device receives a single clock signal, the data/command clock (WCK) from the memory controller and uses that single clock to capture commands presented on the command (CA) pins at edges of the single clock, in addition to capturing data (as shown in Fig. 2, which is reproduced below for ease of reference and convenience, Bloemer discloses a memory device that receives only a single data/command clock 202 from the controller and uses that single clock to capture commands, without receiving a separate system/command clock, expressly avoiding the need for a second, lower-speed clock signal for transferring commands to the memory device. See col. 7:55-8:38).
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It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to a person having ordinary skill in the art to modify Shin’s memory system so that the memory device does not receive the system clock CK from the memory controller, and instead uses the clock it already generates internally from the received data clock WCK (Shin ¶ 0067, 0070) as its system/command timing reference, as taught by Bloemer in order to eliminate the separate, second clock signal reduces the number of clock connections/pins between the controller and the memory device, thereby reducing interface pin count, area, and power (col. 3:25-41). This motivation is entirely consistent with Shin’s own stated objective of reducing current consumption in the memory device (Shin ¶ 0051, 0113). Because Shin’s memory device already derives clock signals at the system-clock rate from the received data clock WCK, and because Bloemer teaches that a memory device can capture commands from that single clock without a separate system clock, a person of ordinary skill would have had a reasonable expectation of success in eliminating the received system clock CK and relying on the internally generated, WCK-derived clock.
In regard to claims 2, 9, 16, Shin et al. disclose wherein the system clock signal is generated based on the data clock signal according to a ratio (in Shin, the WCK divider 224 may divide a frequency of a data clock WCK_S by a preset ratio (divide-by-2 in FIG. 4) to output four-phase clock signals WCK_0, WCK_90, WCK_180, and WCK_270 with a 90-degree phase difference from each other through dividing output terminals IW1, IW2, IW3, and IW4. See ¶ 67-70).
In regard to claims 3, 10, 17, Shin et al. disclose wherein the memory device is further configured to use the system clock signal to sample a command signal received from the memory controller (in Shin, an internal data clock generating circuit configured to adjust phase to synchronize a data clock with a system clock, having a clock frequency lower than the data clock, in response to the command. See ¶ 15, 49, 64).
In regard to claims 4, 11, 18, Shin et al. disclose wherein the memory device is further configured to generate a data strobe signal based on the data clock signal (in Shin, a second clocking operating manner in which the data output strobe signal DQS is received in a write operation mode and a read mode of operation. For the second clocking operating manner, the data output strobe signal may be generated from the semiconductor memory device 200a during read operation. See ¶ 104).
In regard to claims 5, 12, 19, Shin et al. disclose wherein the data clock signal is a gated data clock signal (in Shin, the data clocks WCK and WCK# may be provided through a port P20 in the form of differential signals with complementary phases. The data clock may be a clock which is associated with a data input/output rate. See ¶ 47).
In regard to claims 6, 13, 20, Shin et al. disclose wherein the memory controller is configured to provide the data clock signal to the memory device based on a demand from command or data traffic between the memory controller and the memory device (in Shin, data clock WCK or the data output strobe signal DQS may be a clock which is associated with a data input/output rate. See ¶ 107).
In regard to claim 7 and 14, Shin et al. disclose wherein the memory controller is configured to transmit one or more command signals based on the data clock signal, and wherein the memory controller does not transmit an internal system clock signal to the memory device (in Shin, the memory controller 100 may provide system clocks CK and CK# and data clocks WCK and WCK# to the semiconductor memory device 200. See ¶ 47).
In regard to claim 21, Shin et al. disclose wherein the memory device is configured to clock control signals from the memory controller using the system clock signal generated within the memory device (in Shin, discloses a memory device that receives a data clock from the memory controller, generates an internal system clock based on that received data clock, and uses the internally generated system clock to sample/clock control/command signals coming from the memory controller. The memory device necessarily uses its internally generated system clock (derived from the received data clock) to properly sample incoming command/control signals. This is the standard and inherent operation of the system taught by Shin. See ¶ 6, 9, 45, 50, 52: the semiconductor memory device may include a command decoder configured to generate an auto-sync signal in response to a command for writing data to a memory cell or reading data from a memory cell, and an internal data clock generating circuit configured to adjust phase of a second clock to a first clock in response to the auto-sync signal, wherein a frequency of the second clock is higher than a frequency of the first clock).
In regard to claim 22, Shin et al. disclose further configured to: wherein the system clock signal generated by the internal clock generation circuitry is configured to clock control signals received from a memory controller (in Shin, discloses a memory device that receives a data clock from the memory controller, generates an internal system clock based on that received data clock, and uses the internally generated system clock to sample/clock control/command signals coming from the memory controller. The memory device necessarily uses its internally generated system clock (derived from the received data clock) to properly sample incoming command/control signals. This is the standard and inherent operation of the system taught by Shin. See ¶ 6, 9, 45, 50, 52: the semiconductor memory device may include a command decoder configured to generate an auto-sync signal in response to a command for writing data to a memory cell or reading data from a memory cell, and an internal data clock generating circuit configured to adjust phase of a second clock to a first clock in response to the auto-sync signal, wherein a frequency of the second clock is higher than a frequency of the first clock).
Examiner's note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passages as taught by the prior art or disclosed by the Examiner.
Response to Applicant's Amendments & Arguments
The rejection of claims 1-22 under 35 U.S.C. 102(a)(1) as anticipated by Shin (US 2019/0180809) is withdrawn in view of Applicant’s amendment. Independent claims 1, 8, and 15 now recite that the system clock signal is generated by the memory device and is not received at the memory device from the memory controller. Shin’s memory device receives the system clock CK from the memory controller through port P10 (Shin ¶ 0047) and merely phase-synchronizes the received data clock WCK to the received CK (Shin ¶ 0050, 0062); Shin does not disclose a memory device that generates a system clock without receiving it from the controller. Accordingly, Shin alone no longer reads on the amended independent claims, and a new ground of rejection under 35 U.S.C. 103 is set forth below, necessitated by Applicant’s amendment. (CCPA 1978).
Conclusion
Claims 1-22 are rejected.
The prior arts made of record and not relied upon are considered pertinent to applicant's disclosure.
Ryan (US No. 5,749,086) discloses a simplified Clocked DRAM With A Fast Command Input
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/RAYMOND N PHAN/
Primary Examiner, Art Unit 2175
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