Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application has been examined. Claims 1-20 are pending.
The Group and/or Art Unit location of your application in the PTO has changed. To aid in correlating any papers for this application, all further correspondence regarding this application should be directed to Group Art Unit 2175.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Shin et al. (US Pub No. 2019/0180809).
In regard to claims 1, 8, 15, Shin et al. disclose a memory device (item 200 of figure 1), a method and the system, comprising: a memory controller (item 100 of figure 1) configured to generate a data clock signal (i.e. WCK) (as shown in Fig. 1, which is reproduced below for ease of reference and convenience, Shin discloses the memory controller 100 may provide data clocks WCK and WCK# to the semiconductor memory device 200. The data clocks WCK and WCK# may be provided through a port P20 in the form of differential signals with complementary phases. See ¶ 47-48);
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and a memory device (item 200 of figure 1) coupled to the memory controller, the memory device configured to: receive the data clock signal from the memory controller (in Shin, the data clocks WCK and WCK# may be provided through a port P20 in the form of differential signals with complementary phases. See ¶ 47); and generate a system clock signal based on the data clock signal (in Shin, the internal data clock generating circuit 220 may adjust phase to synchronize the second clock WCK (i.e. data clock), having a clock frequency higher than the first clock, with the first clock being the system clock CK. A phase synchronization operation of the internal data clock generating circuit 220 may be performed as a hidden operation of a normal memory operation (a read or write operation) within a column address strobe latency (CL). See ¶ 50-52).
In regard to claims 2, 9, 16, Shin et al. disclose wherein the system clock signal is generated based on the data clock signal according to a ratio (in Shin, the WCK divider 224 may divide a frequency of a data clock WCK_S by a preset ratio (divide-by-2 in FIG. 4) to output four-phase clock signals WCK_0, WCK_90, WCK_180, and WCK_270 with a 90-degree phase difference from each other through dividing output terminals IW1, IW2, IW3, and IW4. See ¶ 67-70).
In regard to claims 3, 10, 17, Shin et al. disclose wherein the memory device is further configured to use the system clock signal to sample a command signal received from the memory controller (in Shin, an internal data clock generating circuit configured to adjust phase to synchronize a data clock with a system clock, having a clock frequency lower than the data clock, in response to the command. See ¶ 15, 49, 64).
In regard to claims 4, 11, 18, Shin et al. disclose wherein the memory device is further configured to generate a data strobe signal based on the data clock signal (in Shin, a second clocking operating manner in which the data output strobe signal DQS is received in a write operation mode and a read mode of operation. For the second clocking operating manner, the data output strobe signal may be generated from the semiconductor memory device 200a during read operation. See ¶ 104).
In regard to claims 5, 12, 19, Shin et al. disclose wherein the data clock signal is a gated data clock signal (in Shin, the data clocks WCK and WCK# may be provided through a port P20 in the form of differential signals with complementary phases. The data clock may be a clock which is associated with a data input/output rate. See ¶ 47).
In regard to claims 6, 13, 20, Shin et al. disclose wherein the memory controller is configured to provide the data clock signal to the memory device based on a demand from command or data traffic between the memory controller and the memory device (in Shin, data clock WCK or the data output strobe signal DQS may be a clock which is associated with a data input/output rate. See ¶ 107).
In regard to claim 7 and 14, Shin et al. disclose wherein the memory controller is configured to transmit one or more command signals based on the data clock signal, and wherein the memory controller does not transmit an internal system clock signal to the memory device (in Shin, the memory controller 100 may provide system clocks CK and CK# and data clocks WCK and WCK# to the semiconductor memory device 200. See ¶ 47).
Examiner's note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passages as taught by the prior art or disclosed by the Examiner.
Conclusion
Claims 1-20 are rejected.
The prior arts made of record and not relied upon are considered pertinent to applicant's disclosure.
Kim et al. (US Pub No. 2024/0265957) disclose a memory device includes: a control logic circuit configured to receive command address (CA) signals and control an operation of the memory device; a clock circuit configured receive a clock signal and divide the clock signal to generate first to fourth phase clock signals that are respectively synchronized with first to fourth rising edges of the CA signals indicating a command start point (CSP) command.
Yoon et al. (US Pub No. 2024/0170085) disclose a memory controller providing a data strobe signal, and a memory device (200) receiving a data signal provided from the memory controller or outputting the data signal to the controller. A clock generation circuit receives the determined number of clock signals when the determined clock signals are smaller than an actual number of the clock signals, and adjusts a duty cycle of a corresponding clock signal according to a correction code.
Oh et al. (US Pub No. 2019/0172512) disclose the operating method involves receiving a write command and data from the outside of the semiconductor memory device (200). The write command is synchronized with a main clock signal, where the data is synchronized with a data clock signal. The data is stored in the memory cell array based on a frequency-divided data clock signal, which is divided from the data clock signal.
Oh et al. (US Pub No. 2018/0005686) disclose read data are transmitted to the memory controller with a selected one of a first strobe signal generated based on a frequency-divided data clock signal and a differential strobe signal generated based on the frequency-divided data clock signal, where the differential strobe signal includes the first and a second strobe signal which is a strobe signal inverted, and a semiconductor memory device (600) does not include a dedicated strobe pin among a set of pins.
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/RAYMOND N PHAN/
Primary Examiner, Art Unit 2175