DETAILED ACTION
This action is in response to the Application filed on 05/13/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d).
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: --CASCODE SWITCHING DEVICE IN A POWER CONVERSION DEVICE--.
Claim Objections
Claim(s) 1 is/are objected to because of the following informalities:
Claim 1 recites “a power switch” in line 3. It appears that it should be “the power switch”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 – 5 and 8 – 10 are rejected under 35 U.S.C. 103 as being unpatentable over US Pub. No. 2024/0178831; (hereinafter Qu) in view of US Pub. No. 2021/0408891; (hereinafter Yao).
Regarding claim 1, Qu [e.g. Fig. 2] discloses a power conversion device, comprising: a power switch circuit [e.g. GaN], comprising: a power switch implemented by a depletion-type gallium nitride field-effect transistor [e.g. paragraph 019 recites “the present disclosure proposes to overcome at least some of the above problems by providing a cascode switching module that includes a normally-on power semiconductor (this may be a depletion-mode GaN HEMT), a normally-off semiconductor device (this may be a low-voltage MOSFET) and a gate driver”], wherein a first terminal of the power switch is coupled to a high-voltage terminal of the power conversion device [e.g. Vout]; a cascade switch [e.g. LV MOS (low voltage MOSFET)], wherein a first terminal of the cascade switch [e.g. upper terminal] is coupled to a second terminal of the power switch [e.g. lower terminal]; and a control circuit [e.g. Isolated Regulator for gate driver supplies, microcontroller, isolators, high-side GaN Gate Driver IC, R1,R2] coupled to the power switch circuit, wherein the control circuit is integrated in a first die [e.g. paragraph 041 recites “The first capacitor may be formed on the gate driver die]; wherein the power switch is integrated in a second die [e.g. paragraph 041 “depletion mode semiconductor device die”]; and wherein a withstand voltage capability of the second die is higher than a withstand voltage capability of the first die [e.g. Qu discloses that the MOSFET is a low-voltage MOSFET, paragraph 019 recites “a normally-off semiconductor device (this may be a low-voltage MOSFET)” and paragraph 030 suggests that GaN is a high voltage transistor, paragraph 030 recites “The cascode switching module allows the beneficial properties of using a GaN power device (such as a large band gap, high breakdown voltage, and fast switching properties), therefore a person having ordinary skills in the art would provide an appropriate withstand voltage for each die according to its component electrical capability, e.g. high voltage withstand voltage for the GaN and a low withstand voltage for the controller].
However, Qu fails to disclose wherein the control circuit and the cascode switch are integrated in a first die.
Yao teaches wherein the control circuit and the cascode switch are integrated in a first die [e.g. paragraph 019 recites “first-type power transistor Q1 can be integrated into the first die, and one or more second-type power transistors can be integrated into the second die… The control circuit can be integrated into the first die or the second die”].
It would have been obvious to one having ordinary skill in the art at the time of the effective filing date to modify Qu, by wherein the control circuit and the cascode switch are integrated in a first die as taught by Yao in order of being able to reduce the size of the module.
Regarding claim 2, Qu [e.g. Fig. 2] discloses wherein the cascade switch [e.g. LV MOS] is implemented by an enhancement-type field-effect transistor [e.g. paragraph 033 recites “The enhancement mode transistor may be referred to a normally-off device. The enhancement mode transistor device may comprise a Silicon MOSFET”].
Regarding claim 3, Qu [e.g. Fig. 2] discloses wherein: a second terminal [e.g. low terminal] of the cascade switch is coupled to a control terminal of the power switch [e.g. low terminal directly connected to control terminal of GaN], and a control terminal [e.g. gate terminal] of the cascade switch is coupled to the control circuit.
Regarding claim 4, Qu [e.g. Fig. 2] discloses wherein the control circuit generates a control signal [e.g. VH] and provides the control signal to the control terminal of the cascade switch.
Regarding claim 5, Qu [e.g. Fig. 2] discloses wherein the cascade switch performs a switching operation of the power switch circuit in response to a duty cycle of the control signal [e.g. paragraph 076 recites “As the gate and source of the GaN device 105 are individually connected with the source and drain of the MOSFET 110 in a cascode configuration, the GaN device 105 can be indirectly turned off by means of turning off the MOSFET 110”. As shown in Fig. 2, the control signal GH is provided to LV MOS, wherein the operation of LV MOS controls the GaN transistor by inputting the source voltage at the gate of the GaN transistor].
Regarding claim 8, Qu, Fig. 2 fails to disclose wherein: a control terminal of the power switch is coupled to the control circuit, and a control terminal of the cascade switch receives an enable signal.
Qu [e.g. Fig. 8] teaches wherein: a control terminal of the power switch [e.g. gate of GaN] is coupled to the control circuit [e.g. integrated gate driver], and a control terminal of the cascade switch receives an enable signal [e.g. VG].
It would have been obvious to one having ordinary skill in the art at the time of the effective filing date to modify Qu, Fig. 2 by wherein: a control terminal of the power switch is coupled to the control circuit, and a control terminal of the cascade switch receives an enable signal as taught by Qu, Fig. 8 in order of being able to significantly simplifies the application since the external gate drivers can be suppressed and there is no need for a converter to provide the supply voltage for the external gate drivers, paragraph 097.
Regarding claim 9, Qu, Fig. 2 fails to disclose wherein the control circuit generates a control signal and the enable signal and provides the enable signal to the control terminal of the cascade switch.
Qu [e.g. Fig. 8] teaches wherein the control circuit [e.g. integrated gate driver] generates a control signal [e.g. VGG] and the enable signal and provides the enable signal to the control terminal of the cascade switch [e.g. VG to LV MOS].
It would have been obvious to one having ordinary skill in the art at the time of the effective filing date to modify Qu, Fig. 2 by wherein the control circuit generates a control signal and the enable signal and provides the enable signal to the control terminal of the cascade switch as taught by Qu, Fig. 8 in order of being able to significantly simplifies the application since the external gate drivers can be suppressed and there is no need for a converter to provide the supply voltage for the external gate drivers, paragraph 097.
Regarding claim 10, Qu, Fig. 2 fails to disclose wherein: the cascade switch is turned on in response to the enable signal, and the power switch performs a switching operation of the power switch circuit in response to the control signal.
Qu [e.g. Fig. 8] teaches wherein: the cascade switch is turned on in response to the enable signal [e.g. VG to control terminal (gate) of LV MOS], and the power switch performs a switching operation of the power switch circuit [e.g. ON/OFF switching operation] in response to the control signal [e.g.VGG to control terminal (gate) of GaN].
It would have been obvious to one having ordinary skill in the art at the time of the effective filing date to modify Qu, Fig. 2 by wherein: the cascade switch is turned on in response to the enable signal, and the power switch performs a switching operation of the power switch circuit in response to the control signal as taught by Qu, Fig. 8 in order of being able to significantly simplifies the application since the external gate drivers can be suppressed and there is no need for a converter to provide the supply voltage for the external gate drivers, paragraph 097.
Examiner's Note
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Allowable Subject Matter
Claim 6 – 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the indication of the allowability of claim 6 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “further comprising: a safety capacitor coupled to the first terminal of the power switch; and a charge and discharge control circuit comprising: a discharge circuit coupled to the second terminal of the power switch and the control circuit and configured to perform a discharge operation on a voltage value located at the safety capacitor, wherein the discharge circuit is integrated in the first die”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alex Torres-Rivera whose telephone number is (571)272-5261. The examiner can normally be reached M-F 9:00-5:30 ET.
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/ALEX TORRES-RIVERA/Primary Examiner, Art Unit 2838