CTNF 18/663,186 CTNF 83587 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA Claim(s) 14 and 15 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Park et al (PG Pub 2024/0379780 A1) . 07-15-02-aia The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. Regarding claim 14, Park teaches a semiconductor device comprising: an active pattern (protruding portion of 105, figs. 1 and 2) extending on a substrate (105) in a first direction (D1); first and second channel structures (112, paragraph [0032] and 122, paragraph [0032]) sequentially stacked on the active pattern, wherein the first and second channel structures include a plurality of first and second channel layers (fig. 2L), respectively, that are stacked to be spaced apart from each other in a vertical direction that is perpendicular to an upper surface of the substrate; an intermediate insulation pattern (117, paragraph [0058]) between the first and second channel structures; a gate structure (150, paragraph [0034]) crossing the active pattern in a second direction, intersecting the first direction, and on the plurality of first and second channel layers; a pair of first source/drain patterns (135, paragraph [0050]) on portions of the active pattern on opposing sides of the gate structure, and connected to opposing ends of the plurality of first channel layers, respectively; an isolation insulating layer having a plurality of insulating films (183 and 142, paragraphs [0066][0054]) stacked on the first source/drain patterns, respectively, wherein a first thickness (pointy corners of 183, fig. 2L) of opposing edge portions thereof in the first direction (D1) is smaller than a second thickness of a portion thereof between the opposing edge portions; a pair of second source/drain patterns (145, paragraph [0064]) connected to opposing ends of the plurality of second channel layers on the opposing sides of the gate structure, respectively; and an interlayer insulating layer (142) on the isolation insulating layer, and on the second source/drain patterns. Regarding claim 15, Park teaches the semiconductor device of claim 14, wherein the plurality of insulating films comprises: a first insulating film (183, fig. 2L, paragraph [0054]) on respective upper surfaces of the first source/drain patterns; and at least one second insulating film (142, paragraph [0066]) stacked on the first insulating film. 07-15-03-aia AIA Claim(s) 20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Shih et al (PG Pub 2024/0321990 A1) . Regarding claim 20, Shih teaches a semiconductor device comprising: an active pattern (protruding region of 202, fig. 9B) extending on a substrate (202) in a first direction; first and second lower channel layers (2080L1 and 2080L2 in leftmost and rightmost 210C regions, fig. 9A, the middle region 210C is shown in fig. 9B) in first and second regions of the active pattern, respectively, and spaced apart from each other in a vertical direction that is perpendicular to an upper surface of the substrate; first and second upper channel layers (2080U1 and 2080U2 in leftmost and rightmost 210C regions) on the first and second lower channel layers, respectively, and spaced apart from each other in the vertical direction; a first intermediate insulation pattern (226M, on the leftmost 210C region) between the first lower channel layers and the first upper channel layers; a second intermediate insulation pattern (226m on the rightmost 210C region) between the second lower channel layers and the second upper channel layers; a first gate structure (254T on the leftmost 210C region) crossing the first region of the active pattern in a second direction, intersecting the first direction, and on the first lower channel layers and the first upper channel layers; a second gate structure (254T on the rightmost 210C region) crossing the second region of the active pattern in the second direction, and on the second lower channel layers and the second upper channel layers; a first source/drain pattern (230, paragraph [0029]) between the first and second gate structures and connected to the first and second lower channel layers; an isolation insulating layer comprising a first insulating film (230, paragraph [0030]) on an upper surface of the first source/drain pattern, and at least one second insulating film (234, paragraph [0030]) stacked on the first insulating film and having opposing ends that are spaced apart from the first and second intermediate insulation patterns along the first direction; and a second source/drain pattern (248, paragraph [0032]) between the first and second gate structures, and connected to the first and second upper channel layers . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim (s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al (PG Pub 2024/0379780 A1) . Regarding claim 19, Park remains as applied in claim 14. Park does not teach the second thickness of the isolation insulating layer is about 5 nm to 20 nm, and respective thicknesses of central portions of the plurality of insulating films are about 2 nm to 5 nm. It would have been obvious to the skilled in the art before the effective filing date of the invention to optimize the second thickness of the isolation insulating layer to be, about 5 nm to 20 nm, for example, and to optimize respective thicknesses of central portions of the plurality of insulating films to be, about 2 nm to 5 nm, for example, according to the intended use of the device. It has been well known in the art that those thicknesses affect electrical characteristics of the device and can be adjusted. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller , 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) . Allowable Subject Matter 12-151-07 AIA 07-97 12-51-07 Claim s 1-13 are allowed. 12-151-08 AIA 07-43 12-51-08 Claim s 16-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: Prior art does not teach “a second gate structure crossing the second region of the active pattern in the second direction and on the second lower channel layers and the second upper channel layers; a first source/drain pattern between the first and second gate structures and connected to the first and second lower channel layers; an isolation insulating layer extending on surfaces of the first source/drain pattern in the second direction and extending to an upper surface of the device isolation layer, wherein a thickness of opposing edge portions of the isolation insulating layer is smaller than a thickness of a central portion therebetween when viewed in cross section along the first direction; a second source/drain pattern between the first and second gate structures and connected to the first and second upper channel layers” (claim 1); “opposing ends of each of the plurality of second insulating films in the first direction has a respective protruding portion” (claim 16). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FEIFEI YEUNG LOPEZ whose telephone number is (571)270-1882. The examiner can normally be reached M-F: 8am to 4pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571 270 7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FEIFEI YEUNG LOPEZ/Primary Examiner, Art Unit 2899 Application/Control Number: 18/663,186 Page 2 Art Unit: 2899 Application/Control Number: 18/663,186 Page 3 Art Unit: 2899 Application/Control Number: 18/663,186 Page 4 Art Unit: 2899 Application/Control Number: 18/663,186 Page 5 Art Unit: 2899 Application/Control Number: 18/663,186 Page 6 Art Unit: 2899 Application/Control Number: 18/663,186 Page 7 Art Unit: 2899
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