Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Application
This Office Action is in response to Applicant’s Amendment filed on 4/06/2026.
Claims 1-22 are pending for this examination.
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 10-16, and 18-22 are rejected under 35 U.S.C. 103 as being unpatentable over Ginzburg et al. (US 2011/0153707), herein referred to as Ginzburg ‘707, in view of Nair et al. (US 6,944,747), herein referred to as Nair ‘747.
Referring to claim 1, Ginzburg ‘707 teaches a processor (see Abstract; see Fig. 1, processing unit 110) comprising:
decode circuitry to decode an instruction (see Fig. 1, decoder 128; see Paragraph 0022), the instruction having a first field to identify data of a source matrix and a second field to identify a destination matrix (see Paragraphs 0028-0029, wherein for an example matrix multiply-add operation, decoder accesses register file unit 134 or a location in memory 140, 112, 104, 118 specified in the instruction which includes SRC1, SRC2, SRC3, and DEST register addresses); and
execution circuitry coupled with the decode circuitry (see Fig. 1, execution unit 136 coupled with decoder 128), the execution circuitry to perform operations corresponding to the instruction, including to store all data elements of the source matrix to corresponding data elements positions of the destination matrix (see Fig. 2, execution unit performs the operation 203 and stores results in register or memory 204; see Paragraphs 0028-0030, wherein the DEST is the address of the destination register where the result data is to be stored).
However, Ginzburg ‘707 does not specifically teach a programmable configuration storage to store configuration information; wherein a number of columns of the source matrix is to be configured based on the configuration information.
Nair ‘747 teaches a matrix data processor system (see Abstract), where the matrix data processor includes a register set having a configuration register that contains a plurality of matrix parameters for at least partially describing and identifying a first logical source matrix, with the number of matrix rows and columns, a second logical source matrix with the number of matrix rows and columns, and at least one destination matrix (see Claim 12; also see Col. 7. Lines 61-67, Col. 8, lines 1-47, wherein the matrix parameters identify source and destination matrices, define the configuration of each matrix, and can be changed by users).
Ginzburg ‘707 and Nair ‘747 apply as analogous prior arts as both pertain to the same field of endeavor of data processors used to perform matrix operations.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ginzburg ‘707 system as set forth above to have the register set include a configuration register that contains a plurality of matrix parameters for describing and identifying matrices including the number of rows and columns, i.e. the configuration of the matrices, as taught by Nair ‘747, as a person of ordinary skill in the art would have been motivated to include the usage of a configurable register holding matrix parameters to prevent wasting processor bandwidth and other processing inefficiencies caused by underutilization of resources from the disparity in the size of data representations (see Col. 1, lines 38-54) which causes processing systems to be data-starved due to lack of timely data presentations which adds additional processing cycles and slows down overall operation of the device (see Col. 2, lines 1-13) where having a configuration register and using matrix parameters to define the size and location of various matrix elements, the signal processing operations can be significantly enhanced (see Abstract) through providing the full specification in a single instruction for the matrices (see Col. 7, lines 63-67, Col. 8, lines 1-8).
As to claim 2, Ginzburg ‘707 teaches the processor of claim 1, wherein the execution circuitry, to store said all data elements, is to store a plurality of rows of data elements of the source matrix to corresponding rows of the destination matrix (see Fig. 2, execution unit performs the operation 203 and stores results in register or memory 204, wherein Examiner points out that matrix operations would have corresponding data elements of the source matrix stored in corresponding positions in the destination matrix after whatever operation is done, i.e. this limitation is inherent to any matrix operation done; also see Paragraph 0036).
As to claim 3, Ginzburg ‘707 teaches the processor of claim 1, wherein the instruction specifies a size of the data elements of the source matrix (see Paragraph 0024, wherein the register being used can be 16, 32, 64, 128, 256, or 512 bit, where an exemplar data layout can be a 4x4 matrix of scalar data elements representing 32 bits, see Paragraph 0031; Examiner points out that specifying the assize of data elements of the source matrix is a matter of design choice that person of ordinary skill in the art could easily determine from the Ginzburg ‘707 system)
As to claim 4, Ginzburg ‘707 teaches the processor of claim 3, wherein the size is any one of 8-bits, 16-bits, 32-bits, and 64-bits (see Paragraph 0024, wherein the register being used can be 16, 32, 64, 128, 256, or 512 bit, where an exemplar data layout can be a 4x4 matrix of scalar data elements representing 32 bits, see Paragraph 0031).
As to claim 5, Ginzburg ‘707 teaches the processor of claim 1, further comprising a plurality of vector registers to store the source matrix (see Paragraphs 0031-0034, wherein the matrixes are stored in the registers as vectors).
As to claim 6, Ginzburg ‘707 teaches the processor of claim 1, further comprising a two-dimensional tile storage to store the destination matrix (see Paragraph 0035, wherein Ginzburg ‘707 teaches 2d matrix multiply-add operations, which means that the storage would hold the data for constructing a 2d matrix).
As to claim 7, Ginzburg ‘707 teaches the processor of claim 1, wherein a dimension of the source matrix depends on a size of the data elements (see Paragraph 0024, wherein the register being used can be 16, 32, 64, 128, 256, or 512 bit, where an exemplar data layout can be a 4x4 matrix of scalar data elements representing 32 bits, see Paragraph 0031; Examiner points out that the dimensions of the source matrix are inherently dependent on the size of the data elements being used to construct the matrix).
As to claim 8, Ginzburg ‘707 teaches the processor of claim 1, wherein the decode circuitry is to decode a second instruction, and further comprising execution circuitry to perform operations corresponding to the second instruction, including to enable tile operations and configure tiles for use (see Paragraphs 0043-0044, where some implementations use fused multiply-add instructions, multi-step matrix operations, and in other implementations the throughput of the system can be one matrix multiplication every four clock cycles showing multiple instructions being executed, i.e. at least a second instruction being processed).
Referring to claim 10, Ginzburg ‘707 teaches a method (see Abstract) comprising:
decoding an instruction (see Fig. 1, decoder 128; see Paragraph 0022) having a first field identifying data of a source matrix and a second field identifying a destination matrix (see Paragraphs 0028-0029, wherein for an example matrix multiply-add operation, decoder accesses register file unit 134 or a location in memory 140, 112, 104, 118 specified in the instruction which includes SRC1, SRC2, SRC3, and DEST register addresses); and
performing operations corresponding to the instruction, including storing all data elements of the source matrix to corresponding data element positions of the destination matrix (see Fig. 2, execution unit performs the operation 203 and stores results in register or memory 204; see Paragraphs 0028-0030, wherein the DEST is the address of the destination register where the result data is to be stored).
However, Ginzburg ‘707 does not specifically teach storing configuration information in a programmable configuration storage; wherein a number of columns of the source matrix is configured based on the configuration information
Nair ‘747 teaches a matrix data processor system (see Abstract), where the matrix data processor includes a register set having a configuration register that contains a plurality of matrix parameters for at least partially describing and identifying a first logical source matrix, with the number of matrix rows and columns, a second logical source matrix with the number of matrix rows and columns, and at least one destination matrix (see Claim 12; also see Col. 7. Lines 61-67, Col. 8, lines 1-47, wherein the matrix parameters identify source and destination matrices, define the configuration of each matrix, and can be changed by users).
Ginzburg ‘707 and Nair ‘747 apply as analogous prior arts as both pertain to the same field of endeavor of data processors used to perform matrix operations.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ginzburg ‘707 system as set forth above to have the register set include a configuration register that contains a plurality of matrix parameters for describing and identifying matrices including the number of rows and columns, i.e. the configuration of the matrices, as taught by Nair ‘747, as a person of ordinary skill in the art would have been motivated to include the usage of a configurable register holding matrix parameters to prevent wasting processor bandwidth and other processing inefficiencies caused by underutilization of resources from the disparity in the size of data representations (see Col. 1, lines 38-54) which causes processing systems to be data-starved due to lack of timely data presentations which adds additional processing cycles and slows down overall operation of the device (see Col. 2, lines 1-13) where having a configuration register and using matrix parameters to define the size and location of various matrix elements, the signal processing operations can be significantly enhanced (see Abstract) through providing the full specification in a single instruction for the matrices (see Col. 7, lines 63-67, Col. 8, lines 1-8).
As to claim 11, Ginzburg ‘707 teaches the method of claim 10, wherein the instruction specifies a size of the data elements of the source matrix, and wherein the size is any one of 8-bits, 16-bits, 32-bits, and 64-bits (see Paragraph 0024, wherein the register being used can be 16, 32, 64, 128, 256, or 512 bit, where an exemplar data layout can be a 4x4 matrix of scalar data elements representing 32 bits, see Paragraph 0031).
As to claim 12, Ginzburg ‘707 teaches the method of claim 11, further comprising a plurality of vector registers storing the source matrix (see Paragraphs 0031-0034, wherein the matrixes are stored in the registers as vectors).
As to claim 13, Ginzburg ‘707 teaches the method of claim 11, further comprising a two-dimensional tile storage storing the destination matrix (see Paragraph 0035, wherein Ginzburg ‘707 teaches 2d matrix multiply-add operations, which means that the storage would hold the data for constructing a 2d matrix).
As to claim 14, Ginzburg ‘707 teaches the method of claim 11, wherein storing said all data elements comprises storing a plurality of rows of data elements of the source matrix to corresponding rows of the destination matrix (see Fig. 2, execution unit performs the operation 203 and stores results in register or memory 204, wherein Examiner points out that matrix operations would have corresponding data elements of the source matrix stored in corresponding positions in the destination matrix after whatever operation is done, i.e. this limitation is inherent to any matrix operation done; also see Paragraph 0036).
As to claim 15, Ginzburg ‘707 teaches the method of claim 11, wherein a dimension of the source matrix depends on a size of the data elements (see Paragraph 0024, wherein the register being used can be 16, 32, 64, 128, 256, or 512 bit, where an exemplar data layout can be a 4x4 matrix of scalar data elements representing 32 bits, see Paragraph 0031; Examiner points out that the dimensions of the source matrix are inherently dependent on the size of the data elements being used to construct the matrix).
As to claim 16, Ginzburg ‘707 teaches the method of claim 11, further comprising decoding a second instruction, and further comprising performing operations corresponding to the second instruction, including enabling tile operations and configuring tiles for use (see Paragraphs 0043-0044, where some implementations use fused multiply-add instructions, multi-step matrix operations, and in other implementations the throughput of the system can be one matrix multiplication every four clock cycles showing multiple instructions being executed, i.e. at least a second instruction being processed).
Referring to claim 18, Ginzburg ‘707 teaches a system (see Abstract; see Fig. 1, processing unit 110) comprising: a central processing unit (CPU) (see Fig. 1, processing unit 110) comprising:
decode circuitry to decode an instruction (see Fig. 1, decoder 128; see Paragraph 0022), the instruction having a first field to identify data of a source matrix and a second field to identify a destination matrix (see Paragraphs 0028-0029, wherein for an example matrix multiply-add operation, decoder accesses register file unit 134 or a location in memory 140, 112, 104, 118 specified in the instruction which includes SRC1, SRC2, SRC3, and DEST register addresses); and
execution circuitry coupled with the decode circuitry (see Fig. 1, execution unit 136 coupled with decoder 128), the execution circuitry to perform operations corresponding to the instruction, including to store all data elements of the source matrix to corresponding data element positions of the destination matrix (see Fig. 2, execution unit performs the operation 203 and stores results in register or memory 204; see Paragraphs 0028-0030, wherein the DEST is the address of the destination register where the result data is to be stored); and
a system memory coupled with the CPU (see Fig. 1, main memory 104).
However, Ginzburg ‘707 does not specifically teach a programmable configuration storage to store configuration information; wherein a number of columns of the source matrix is to be configured based on the configuration information.
Nair ‘747 teaches a matrix data processor system (see Abstract), where the matrix data processor includes a register set having a configuration register that contains a plurality of matrix parameters for at least partially describing and identifying a first logical source matrix, with the number of matrix rows and columns, a second logical source matrix with the number of matrix rows and columns, and at least one destination matrix (see Claim 12; also see Col. 7. Lines 61-67, Col. 8, lines 1-47, wherein the matrix parameters identify source and destination matrices, define the configuration of each matrix, and can be changed by users).
Ginzburg ‘707 and Nair ‘747 apply as analogous prior arts as both pertain to the same field of endeavor of data processors used to perform matrix operations.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ginzburg ‘707 system as set forth above to have the register set include a configuration register that contains a plurality of matrix parameters for describing and identifying matrices including the number of rows and columns, i.e. the configuration of the matrices, as taught by Nair ‘747, as a person of ordinary skill in the art would have been motivated to include the usage of a configurable register holding matrix parameters to prevent wasting processor bandwidth and other processing inefficiencies caused by underutilization of resources from the disparity in the size of data representations (see Col. 1, lines 38-54) which causes processing systems to be data-starved due to lack of timely data presentations which adds additional processing cycles and slows down overall operation of the device (see Col. 2, lines 1-13) where having a configuration register and using matrix parameters to define the size and location of various matrix elements, the signal processing operations can be significantly enhanced (see Abstract) through providing the full specification in a single instruction for the matrices (see Col. 7, lines 63-67, Col. 8, lines 1-8).
As to claim 19, Ginzburg ‘707 teaches the system of claim 18, wherein the system memory comprises a dynamic random- access memory (DRAM), wherein the instruction specifies a size of the data elements of the source matrix, and wherein the size is any one of 8-bits, 16-bits, 32-bits, and 64-bits (see Paragraph 0024, wherein the register being used can be 16, 32, 64, 128, 256, or 512 bit, where an exemplar data layout can be a 4x4 matrix of scalar data elements representing 32 bits, see Paragraph 0031; see Paragraph 0046, wherein the memory can be DRAM).
As to claim 20, Ginzburg ‘707 teaches the system of claim 18, wherein the execution circuitry, to store said all data elements, is to store a plurality of rows of data elements of the source matrix to corresponding rows of the destination matrix, further comprising a data storage device, and wherein the CPU further comprises a plurality of vector registers to store the source matrix (see Paragraphs 0031-0034, wherein the matrixes are stored in the registers as vectors).
As to claim 21, Ginzburg ‘707 teaches the system of claim 18, wherein the execution circuitry, to store said all data elements, is to store a plurality of rows of data elements of the source matrix to corresponding rows of the destination matrix, further comprising a communication device coupled with the CPU, and wherein the CPU further comprises a two-dimensional tile storage to store the destination matrix (see Paragraph 0035, wherein Ginzburg ‘707 teaches 2d matrix multiply-add operations, which means that the storage would hold the data for constructing a 2d matrix).
As to claim 22, Ginzburg ‘707 teaches the system of claim 18, wherein the decode circuitry is to decode a second instruction, further comprising a coprocessor coupled with the CPU, and wherein the CPU further comprises execution circuitry to perform operations corresponding to the second instruction, including to enable tile operations and configure tiles for use (see Paragraphs 0043-0044, where some implementations use fused multiply-add instructions, multi-step matrix operations, and in other implementations the throughput of the system can be one matrix multiplication every four clock cycles showing multiple instructions being executed, i.e. at least a second instruction being processed).
Claims 9 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Ginzburg ‘707, in view of Nair ‘747, and Wang et al. (US 2002/0112148), herein referred to as Wang ‘148.
As to claim 9, Ginzburg ‘707 and Nair ‘747 do not specifically teach the processor of claim 1, wherein the processor is a central processing unit (CPU) (see Fig. 7, processor 710 and Fig. 8, where processor 810 includes multiple processing cores 826), and wherein the CPU further comprises a reorder buffer and register renaming circuitry (not specifically taught).
Wang ‘148 teaches a microprocessor that can perform out of order processing (see Abstract), where the processor includes execution units, register renaming unit, reservation stations, and re-order buffers (see Fig. 1, processor 100 with register renaming unit 110, execution units 140, re-order buffer 120, and reservation stations 130).
Ginzburg ‘707, Nair ‘747, and Wang ‘148 apply as analogous prior arts as all these arts pertain to the same field of endeavor of data processors used to perform matrix operations.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination Ginzburg ‘707 and Nair ‘747 system as set forth above to have the processor include a register renaming unit and re-order buffer, as taught by Wang ‘148, as a person of ordinary skill in the art would have been motivated to include these elements in a processor as reorder buffers and register renaming units are commonly known and used in processor architecture to provide for out-of-order processing of instructions instead of a strict in-order processing of instructions which can allow for effective usage of processing resources instead of waiting on processor stalls that may occur in normal in-order processing while waiting for an instruction to finish processing when other are ready for processing (see Paragraphs 0004-0005).
As to claim 17, Ginzburg ‘707 and Nair ‘747 do not specifically teach the method of claim 11, further comprising: executing the instruction out-of-order; and renaming registers.
Wang ‘148 teaches a microprocessor that can perform out of order processing (see Abstract), where the processor includes execution units, register renaming unit, reservation stations, and re-order buffers (see Fig. 1, processor 100 with register renaming unit 110, execution units 140, re-order buffer 120, and reservation stations 130).
Ginzburg ‘707, Nair ‘747, and Wang ‘148 apply as analogous prior arts as all these arts pertain to the same field of endeavor of data processors used to perform matrix operations.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination Ginzburg ‘707 and Nair ‘747 system as set forth above to have the processor include a register renaming unit and re-order buffer, as taught by Wang ‘148, as a person of ordinary skill in the art would have been motivated to include these elements in a processor as reorder buffers and register renaming units are commonly known and used in processor architecture to provide for out-of-order processing of instructions instead of a strict in-order processing of instructions which can allow for effective usage of processing resources instead of waiting on processor stalls that may occur in normal in-order processing while waiting for an instruction to finish processing when other are ready for processing (see Paragraphs 0004-0005).
Response to Arguments
Applicant’s arguments, mailed 4/06/2026, have been fully considered but they are not deemed to be persuasive.
Applicant’s arguments that the cited prior art does not specifically teach execution circuitry coupled with decode circuitry, where the execution circuitry is to perform operations corresponding to the instruction, including store all data elements of the source matrix to corresponding data positions of the destination matrix, where Ginzburg ‘707 describes a matrix multiply add which does not store elements from source into a destination, and that the storing of data element of the source to corresponding positions in the destination matrix after whatever operation is done is not inherent to matrix operations (see Pages 6-7) are deemed to be unpersuasive. As to the first point, Examiner points out that Ginzburg ‘707 teaches execution unit and decoder unit coupled to the same bus which would make them electrically coupled together (see Fig. 1, execution unit 136, decoder 128, and local bus 124), where a decoder is used to decode instructions (see Paragraph 0022), and the execution circuit is used to execute the decoded instruction (see Paragraph 0035, where the execution unit 136 can be a multiply-add unit operable to perform matrix multiply-add operation on data elements in registers specified by a first, second, and third source operands and writing the resultant matrix back to the register file unit 134). Thereby Examiner finds that the cited art of Ginzburg ‘707 does teach the hardware elements being argued.
As to the second point, Examiner notes that the claim language requires “performing operations corresponding to an instruction, including storing of all data elements of the source matrix to corresponding data element positions of the destination matrix”, which to Examiner is being interpreted as an instruction is being executed to perform a matrix operation using the source matrix and storing the resultant into a destination matrix in “corresponding data element positions”, where corresponding positions are relative to whatever the operation is done, i.e. if the operation is a multiplication operation using a 2x3 matrix with a 3x2 matrix then the resultant would be a 2x2 matrix, or if the operation is an addition operation then the source and destination matrices have to have the same dimensions to work, or if the operation is a transpose operation then the resultant may be completely different as a 2x3 matrix being transposed results in a 3x2 matrix. Thus it can be seen that the operation being done can alter what the dimensions of the destination matrix and likewise where the position of data elements are to be stored in the destination matrix can be different with the example the a transpose operation or a multiply operations. Examiner points out that Applicant’s claim language simply does not specify what the operation is and thus the current claim language has to be given the broadest reasonable interpretation of being inclusive of any type of matrix operation which includes multiply operations, addition operations, multiply-add operations, move operations, transpose operations, etc., where the only restriction is that this has to be matrix operation as the limitations before this argued limitation indicate that the first field of the instruction identifies data of a source matrix and a second field to identify a destination matrix which means the instruction has to be dealing with matrices and matrix operations. Examiner applied Ginzburg ‘707 which teaches performing a multiply-add operation (see Paragraph 0035), where the resultant is stored into a destination indicated by the instruction (see Paragraphs 0028-0030, wherein the DEST is the address of the destination register where the result data is to be stored), where the data elements would be stored in corresponding positions of the destination based on what was done during the matrix operations, which Examiner finds this to properly read upon the current claim language and limitations. Thus Applicants arguments are deemed to be unpersuasive.
Although Applicants are arguing that the “storing of data element of the source to corresponding positions in the destination matrix after whatever operation is done” is not inherent true, the current claim language does not restrict what the operation is so this interpretation has to the one used as different matrix operations result in different destination matrix dimensions where the data elements will not always be in the same positions in the matrix. Examiner believes that Applicants are trying to imply that the matrix operations being done may be something like a move operation where the source and destination matrices and the same dimensions and the positions of the data elements in the source and destination matrix will be the same, but Examiner points out that the current claim language simply is not restricted to just this interpretation and under the broadest reasonable interpretation, Examiner must interpret the operations to include all matrix operations and their resultant matrix. Thus Examiner finds this argument to be unpersuasive.
In summary, Ginzburg ‘707 in view of Nair ‘747 and Wang ‘148 teaches the claimed invention as set forth above.
Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Baum et al. (US 10,719,323) teaches a system for moving matrices between a source and destination, wherein a compress operation is done prior to moving the data and a decompress operation is done after receiving the data.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL SUN whose telephone number is (571)270-1724. The examiner can normally be reached Monday-Friday 8am-4pm EST.
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/MICHAEL SUN/Primary Examiner, Art Unit 2183
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