Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Arguments
Applicant’s arguments filed 02/21/2026 have been fully considered but they are not persuasive.
The applicant argues that Zhang et al. does not disclose the limitation as amended in claim 1. The examiner respectfully disagrees. Zhang et al. (figures 1-6) teaches wherein each of some of the pixel units is provided with a first limit block and a second limit block (20 and 60 of the current and adjacent pixels), each of the some of the pixel units has a preset light outgoing region, and the first limit block and the second limit block are located at two opposite sides of the preset light outgoing region in the second direction, respectively; and each of the first limit block and the second limit block comprises a first limiting pattern and a second limiting pattern that are stacked together (12, 16, 18, or 15), the first limiting pattern is arranged in the same layer as the gate lines, and the second limiting pattern is arranged in the same layer as the data lines (all the layers are disposed in the same layer as the substrate 10; the concave structure restricts the movement of the spacer when the display is pressed, thus avoiding the phenomenon of light leakage from the display panel); and wherein the first limiting pattern and the second limiting pattern are spaced apart from each other in a direction perpendicular to the first base substrate. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the limit blocks as taught by Zhang et al. in order to avoid the phenomenon of light leakage from the display panel.
The claim language therefore does not patentably distinguish over the applied reference[s], and the previous rejections are maintained.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-8, 12-13, 15-16, 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Zhao (CN 111176042) in view of Nishiki et al. (JP 2667586); further in view of Zhang et al. (CN 103323981).
Regarding claim 1, Zhao (figures 2-6) discloses a display substrate, comprising: a first base substrate, and a plurality of gate lines (501) and a plurality of data lines (502), which are on the first base substrate, wherein the gate lines extend in a first direction, the data lines extend in a second direction, the first direction and the second direction intersect each other and are both parallel to a plane where the first base substrate is located;
the plurality of gate lines and the plurality of data lines define a plurality of pixel units, each of the pixel units comprises a thin film transistor (figure 6), a pixel electrode (71) and a common electrode (72), the pixel electrode is on a side of the common electrode distal to the first substrate; in a same pixel unit, a region where the pixel electrode is located and a region where the thin film transistor is located are arranged in the second direction, an end of the pixel electrode proximal to the thin film transistor is a first end, an end of the pixel electrode distal to the thin film transistor is a second end; at least some of the pixel units are configured with conductive bridge lines 73), respectively, the conductive bridge lines are provided in the same layer as the pixel electrode;
in the pixel unit which is configured with the conductive bridge line, a first hollowed-out structure is provided on a first side of the first end or the second end of the pixel electrode, an end of the conductive bridge line is located in the first hollowed-out structure and is connected to the common electrode through a via (figures 4 and 6), and a second hollowed-out structure (212; figure 2) is provided on a second side of the second end of the pixel electrode; and
the first side and the second side are opposite sides of the pixel electrode in the first direction.
Zhao discloses the limitations as shown in the rejection of claim 1 above. However, Zhao is silent regarding parasitic capacitances and a length of the second hollowed-out structure in the first direction is greater than or equal to 6 μm and a first limit block and a second limit block.
Zhao (in at least page 6, 3rd paragraph) teaches the second connecting block 42 through the contact section 522 and the common connection line 52 are electrically connected. wherein the lead portion of smaller width 521 provided lead portions 521 can be reduced and the parasitic capacitance between the data lines. Therefore, Zhao teaches an absolute value of a difference between parasitic capacitances formed respectively by the pixel electrode and nearest data lines located on both sides of the pixel electrode is less than or equal to a preset capacitance difference. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the electrode as taught by Zhao in order to reduce the parasitic capacitances between the wirings.
Nishiki et al. (figures 1-2) teaches the distance between the gate bus 4 and the pixel electrode 6 is 10 μm (see at page 4, first to fifth paragraphs). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the electrode as taught by Nishiki et al. in order to increase the viewing angles and improve the aperture ratio of the pixel areas. In addition, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a length of the second hollowed-out structure in the first direction being greater than or equal to 6 μm, since it has been held that where the general conditions of a claim, including are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art, In re Aller, 105 USPQ 233 (C.C.P.A. 1955). Therefore, Zhao as modified by Nishiki et al. teaches the second end, which is provided with the second hollowed-out structure, of the pixel electrode is spaced by a distance greater than 6 m apart from a data line nearest to the second hollowed-out structure.
Zhang et al. (figures 1-6) teaches wherein each of some of the pixel units is provided with a first limit block and a second limit block (20 and 60 of the current and adjacent pixels), each of the some of the pixel units has a preset light outgoing region, and the first limit block and the second limit block are located at two opposite sides of the preset light outgoing region in the second direction, respectively; and each of the first limit block and the second limit block comprises a first limiting pattern and a second limiting pattern that are stacked together (12, 16, 18, or 15), the first limiting pattern is arranged in the same layer as the gate lines, and the second limiting pattern is arranged in the same layer as the data lines (all the layers are disposed in the same layer as the substrate 10; the concave structure restricts the movement of the spacer when the display is pressed, thus avoiding the phenomenon of light leakage from the display panel); and wherein the first limiting pattern and the second limiting pattern are spaced apart from each other in a direction perpendicular to the first base substrate. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the limit blocks as taught by Zhang et al. in order to avoid the phenomenon of light leakage from the display panel.
Regarding claim 2, Zhao (figures 2-6) discloses wherein a length of the second hollowed-out structure in the second direction is equal to that of the first hollowed-out structure in the second direction (21; figure 2).
Regarding claim 3, Zhao (figures 2-6) discloses wherein a length of the second hollowed-out structure in the first direction is less than or equal to that of the first hollowed-out structure in the first direction (23; figure 2).
Regarding claim 4, Zhao (figures 2-6) discloses wherein the parasitic capacitances formed respectively by the pixel electrode and the nearest data lines located on both sides of the pixel electrode are equal to each other.
One of ordinary skill in the art before the effective filing date of the claimed invention would recognize utilizing a value close to applicant's claimed range, since it has been held that where the general condition of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. Further, it has been held that a prima facie case of obviousness exists where the claimed ranges and prior art ranges do not overlap by are close enough that one skilled in the art would have expected them to have the same properties. Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985).
Regarding claim 6, Zhao (figures 2-6) discloses common electrode lines (111 and 121) which are provided in the same layer as the gate lines; and multiple pixel units arranged in the first direction correspond to a same common electrode line, the common electrodes in the multiple pixel units are electrically connected to a corresponding common electrode line, orthogonal projections of the second ends of the pixel electrodes in the multiple pixel units on the first base substrate overlap with an orthogonal projection of the corresponding common electrode line on the first base substrate.
Regarding claim 7, Zhao (figures 2-6) discloses an orthogonal projection of the second hollowed-out structure on the first base substrate is located in a region defined by the orthogonal projection of the corresponding common electrode line on the first base substrate
Regarding claim 8, Zhao (figures 2-6) discloses wherein each of the gate lines comprises: first conductive patterns and second conductive patterns arranged alternatively in the first direction (portions of the gate line 501 between the bridge and the data line 502; and portion of the gate line 501 between the data line 502 and the bridge; respectively), a length of each of the first conductive patterns in the second direction is greater than that of each of the second conductive patterns (with gate electrode) in the second direction; orthogonal projections of the first conductive patterns on the first base substrate do not overlap with orthogonal projections of the data lines on the first base substrate, and a part of a corresponding first conductive pattern serves as a gate in the thin film transistor; and orthogonal projections of the conductive bridge lines on the first base substrate do not overlap with the orthogonal projections of the first conductive patterns on the first base substrate.
Regarding claim 12, Zhang et al. (figures 1-6) teaches wherein in the first direction, a length of the first limit block is greater than a length of the second limit block.
Regarding claim 13, Zhang et al. (figures 1-6) teaches wherein both the first limit block and the second limit block are located in a same red pixel unit.
Regarding claim 15, Zhao (figures 2-6) discloses a display panel, comprising: a display substrate and an opposite substrate arranged oppositely, and a liquid crystal layer being filled between the display substrate and the opposite substrate, wherein the display substrate is the display substrate of claim 1.
Regarding claim 16, Zhao discloses the limitations as shown in the rejection of claim 11 above. However, Zhao is silent regarding an amount of change in a voltage applied to the pixel electrode in the pixel unit due to the polarity inversion. It would have been obvious to one having ordinary skill before the effective filing date of the claimed invention to calculate an amount of change in a voltage applied to the pixel electrode in the pixel unit due to the polarity inversion ΔVp using ΔVp=Cpd1*ΔVd/(Cpd1+Cpd2+Cst+Clc+Cgp) since it was known in the art that such calculations are common calculation method of capacitance.
Regarding claim 20, Zhao (figures 2-6) discloses a display device, comprising the display panel of claim 11.
Regarding claim 21, Zhao discloses the limitations as shown in the rejection of claim 1 above. However, Zhao is silent regarding wherein the second end, which is provided with the second hollowed-out structure, of the pixel electrode is spaced by a distance greater than 6 μm apart from a data line nearest to the second hollowed-out structure. Nishiki et al. (figures 1-2) teaches the distance between the gate bus 4 and the pixel electrode 6 is 10 μm (see at page 4, first to fifth paragraphs). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the electrode as taught by Nishiki et al. in order to increase the viewing angles and improve the aperture ratio of the pixel areas. In addition, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a length of the second hollowed-out structure in the first direction being greater than or equal to 6 μm, since it has been held that where the general conditions of a claim, including are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art, In re Aller, 105 USPQ 233 (C.C.P.A. 1955). Therefore, Zhao as modified by Nishiki et al. and Zhang et al. teaches the second end, which is provided with the second hollowed-out structure, of the pixel electrode is spaced by a distance greater than 6 m apart from a data line nearest to the second hollowed-out structure.
(New) The display substrate of claim 1, wherein the second end, which is provided with the second hollowed-out structure, of the pixel electrode is spaced by a distance greater than 6 pm apart from a data line nearest to the second hollowed-out structure.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Zhao in view of Nishiki et al. and Zhang et al.; further in view of Qiao et al. (CN 107505782).
Regarding claim 5, Zhao discloses the limitations as shown in the rejection of claim 1 above. However, Zhao is silent regarding the strip shaped common electrode. Qiao et al. (figures 1-5) teaches wherein multiple pixel units arranged in the first direction correspond to a same strip-shaped common electrode, and the strip-shaped common electrode extends in the first direction; and the common electrodes contained respectively in the multiple pixel units corresponding to the same strip-shaped common electrode are parts of the strip-shaped common electrode at different positions. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the electrode as taught by Qiao et al. in order to achieve a liquid crystal display device that can switch between the wide and narrow visual angle switching and can realize the different occasions and improve the picture display is uneven and the problem of flicker.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable Zhao in view of Nishiki et al. and Zhang et al.; further in view of Qu (CN 109976057).
Regarding claim 9, Zhao discloses the limitations as shown in the rejection of claim 1 above. However, Zhao is silent regarding the color pixels. Qu (figures 1-4) teaches wherein all the pixel units in the display substrate comprise: a red pixel unit, a green pixel unit and a blue pixel unit; and the blue pixel unit is configured with the conductive bridge line. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the electrode as taught by Qiao et al. in order to achieve a array substrate structure of thin film transistor liquid crystal display can reduce the risk of horizontal crosstalk.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Zhao Zhao in view of Nishiki et al. and Zhang et al.; further in view of Bi et al. (CN 105551390).
Regarding claim 10, Zhao discloses the limitations as shown in the rejection of claim 1 above. However, Zhao is silent regarding the red pixel unit is provided with the first limit block and the second limit block. Bi et al. (figure 2) teaches wherein all the pixel units in the display substrate comprise: a red pixel unit, a green pixel unit and a blue pixel unit; and the red pixel unit is provided with the first limit block and the second limit block (2). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the limit blocks as taught by Bi et al. in order to improve the display panel has poor blue-point and high color temperature problem.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAUREN NGUYEN whose telephone number is (571)270-1428. The examiner can normally be reached on Monday - Thursday, 8:00 AM -6:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jennifer Carruth, can be reached at 571-272-9791. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Lauren Nguyen/
Primary Examiner, Art Unit 2871