DETAILED ACTION
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICE COMPRISING MULTI-CHANNEL ACTIVE PATTERNS BETWEEN LINE GATE ISOLATION STRUCTURE AND POINT GATE ISOLATION STRUCTURE
Claim Objections
Claim 19 is objected to because of the following informalities: “the second direction” in lines 6-7 should be changed to “a second direction”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4, 6, 8-13, 16, and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Baek et al. (US 2022/0246601 A1; hereinafter “Baek”).
Regarding claim 1, Baek teaches a semiconductor device comprising: a first gate isolation structure (a top one of 160 shown in Fig. 11) (Fig. 11 and paragraphs 52-53 and 79); a second gate isolation structure (a middle one of 160 shown in Fig. 11) spaced apart from the first gate isolation structure in a first direction (a y-direction) (Fig. 11 and paragraphs 52-53 and 79); a first active pattern (112/114) disposed between the first and second gate isolation structures, the first active pattern extending longitudinally in a second direction (a x-direction) crossing the first direction (Figs. 1-2 and 11 and paragraphs 35-38); a second active pattern (114/112) disposed between the first and second gate isolation structures, the second active pattern extending longitudinally in the second direction and spaced apart from the first active pattern in the first direction (Figs. 1-2 and 11 and paragraphs 35-38); and gate structures (120) disposed between the first and second gate isolation structures, the gate structures directly contact the first and second gate isolation structures (Figs. 1-2, 4A-4b, and 11 and paragraphs 43-47 and 54), wherein a length of the first gate isolation structure in the second direction (a length of the top one of 160 in the x-direction) is greater than a length of the second gate isolation structure in the second direction (a length of the middle one of 160 in the x-direction) (Fig. 11).
Regarding claim 4, Baek teaches wherein: the first active pattern is disposed in an NMOS formation region (114 as an n-type transistor region); the second active pattern is disposed in a PMOS formation region (112 as a p-type transistor region); and the first active pattern is closer to the first gate isolation structure than the second active pattern (Fig. 11 and paragraphs 35-38).
Regarding claim 6, Baek teaches wherein: the first gate isolation structure has a linear shape extending longitudinally in the second direction (Fig. 11); and the second gate isolation structure has a contact shape (Fig. 11).
Regarding claim 8, Baek teaches wherein the first and second gate isolation structures include a same material as each other (Fig. 11 and paragraph 52, 160 formed of an insulating material).
Regarding claim 9, Baek teaches wherein: the gate structures include gate electrodes (122) and gate insulating films (124) (Fig. 2 and paragraph 47); and the gate electrodes directly contact sidewalls of the first gate isolation structure (Figs. 4A and paragraph 54).
Regarding claim 10, Baek teaches wherein: the gate structures include gate electrodes (122) and gate insulating films (124) (Fig. 2 and paragraph 47); and the gate insulating films extend in a third direction directly along sidewalls of the first gate isolation structure (Figs. 4B and paragraph 54).
Regarding claim 11, Baek teaches wherein: the first active pattern includes a lower pattern (112B and 112B) and sheet patterns (112NS) that are spaced apart from the lower pattern; and the gate structures surround the sheet patterns (Fig. 2 and paragraph 36).
Regarding claim 12, Baek teaches a semiconductor device comprising: a first gate isolation structure (a top one of 160 shown in Fig. 11) (Fig. 11 and paragraphs 52-53 and 79); a second gate isolation structure (a middle one of 160 shown in Fig. 11) spaced apart from the first gate isolation structure in a first direction (a y-direction) (Fig. 11 and paragraphs 52-53 and 79); a first active pattern (112/114) disposed between the first and second gate isolation structures, the first active pattern extending longitudinally in a second direction (a x-direction) crossing the first direction (Figs. 1-2 and 11 and paragraphs 35-38); a second active pattern (114/112) disposed between the first and second gate isolation structures, the second active pattern extending longitudinally in the second direction and spaced apart from the first active pattern in the first direction (Figs. 1-2 and 11 and paragraphs 35-38); and a plurality of gate structures (120) intersecting the first and second gate isolation structures and extending longitudinally in the first direction (Figs. 1-2 and 11 and paragraphs 43-47), wherein a number of gate structures directly contacting the first gate isolation structure (a number of 120 directly contacting the top one of 160 at one side) is greater than a number of gate structures directly contacting the second gate isolation structure (a number of 120 directly contacting the middle one of 160 at one side) (Fig. 11).
Regarding claim 13, Baek teaches wherein the second gate isolation structure directly contacts the first gate structure (Figs. 4A-4b and 11).
Regarding claim 16, Baek teaches wherein: the first active pattern is disposed in an NMOS formation region (114 as an n-type transistor region); the second active pattern is disposed in a PMOS formation region (112 as a p-type transistor region); and the first active pattern is closer to the first gate isolation structure than the second active pattern (Fig. 11 and paragraphs 35-38).
Regarding claim 18, Baek teaches wherein the first and second gate isolation structures include a same material as each other (Fig. 11 and paragraph 52, 160 formed of an insulating material).
Regarding claim 19, Baek teaches a semiconductor device comprising: a first gate isolation structure (a top one of 160 shown in Fig. 11) (Fig. 11 and paragraphs 52-53 and 79); a second gate isolation structure (a middle one of 160 shown in Fig. 11) spaced apart from the first gate isolation structure in a first direction (a y-direction) (Fig. 11 and paragraphs 52-53 and 79); a first active pattern (112) disposed between the first and second gate isolation structures, the first active pattern including a first lower pattern (112B and 112U) extending longitudinally in the second direction (a x-direction) and first sheet patterns (112NS) that are spaced apart from the first lower pattern in a third direction that is a thickness direction (a thickness direction of 112 in Fig. 2) crossing the first and second directions (Figs. 1-2 and 11 and paragraphs 35-36); a second active pattern disposed between the first and second gate isolation structures, the second active pattern (114) including a second lower pattern (114B and 114U) extending in the second direction and spaced apart from the first lower pattern in the first direction, and second sheet patterns (114NS) that are spaced apart from the second lower pattern in the third direction (Figs. 1-2 and 11 and paragraphs 37-38); gate structures (120) disposed between the first and second gate isolation structures, the gate structures directly contacting the first and second gate isolation structures (Figs. 1-2 and 4A-4B and paragraphs 43-47 and 54); first source/drain patterns (130 formed on 112) disposed on the first lower pattern, the first source/drain patterns are connected to the first sheet patterns and are doped with impurities of a first conductivity type (a p-type impurity for 112 being a p-type transistor region) (Figs. 1-2 and paragraphs 35 and 51); and second source/drain patterns (130 formed on 114) disposed on the second lower pattern, the second source/drain patterns are connected to the second sheet patterns and are doped with impurities of a second conductivity type (an n-type impurity for 114 being an n-type transistor region) that is different from the first conductivity type (Figs. 1-2 and paragraphs 37 and 51), wherein: the first gate isolation structure overlaps with the first source/drain patterns and the second source/drain patterns in the first direction (the top one of 160 overlapping 130 on 112 and 130 on 114 in the y-direction in a region having 26) (Fig. 11); and the second gate isolation structure does not overlap with the first source/drain patterns and the second source/drain patterns in the first direction (the middle one of 160 not overlapping 130 on 112 and 130 on 114 in the y-direction in the region having 26) (Fig. 11).
Regarding claim 20, Baek teaches wherein the first and second gate isolation structures include a same material as each other (Fig. 11 and paragraph 52, 160 formed of an insulating material).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 14-15, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Baek.
Regarding claims 2 and 14, Baek teaches wherein: the first active pattern (114) is closer to the first gate isolation structure than the second active pattern (112) (Fig. 11 and paragraphs 35-38). Baek does not explicitly teach that the first active pattern (114) is disposed in a P-type metal-oxide semiconductor (PMOS) formation region, the second active pattern (112) is disposed in an N-type metal-oxide semiconductor (NMOS) formation region since Baek teaches 114 as an n-type transistor region and 112 as a p-type transistor region (Fig. 11 and paragraphs 35-38). However, it would have been obvious to one of ordinary skill in the art to change the doping characteristics of the first active pattern and the second active pattern from Baek as a routine skill in the art for obtaining the desired conductivity type transistors at the desired regions.
Regarding claims 15 and 17, Baek does not teach that the first and second gate isolation structures include a material having tensile stress characteristics (claim 15) and compressive stress characteristics (claim 17). Nevertheless, it would have been obvious to one of ordinary skill in the art to form the first and second gate isolation structures formed of an insulating material (Baek, paragraph 52) such as silicon nitride, for example, as a tensile stress material for enhancing electron mobility of the n-type transistor and as a compressive stress for enhancing hole mobility of the p-type transistor.
Allowable Subject Matter
Claims 3, 5, and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL B WHALEN whose telephone number is (571)270-3418. The examiner can normally be reached on M-F: 8AM-5PM.
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/DANIEL WHALEN/Primary Examiner, Art Unit 2893
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