DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-10 are pending in this application.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 05/14/2024 is/are in compliance with the provisions of 37 C.F.R. § 1.97. Accordingly, the IDS has/have been considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Applicant Admitted Prior Art Figure 1 (hereinafter “AAPA”) and further in view of Avery U.S. Patent No. 4,567,500 (hereinafter “Avery”).
Regarding claim 1, AAPA teaches an electrostatic discharge protection device (refer to fig.1) comprising: a clamping bipolar junction transistor (i.e. bipolar junction transistor 10)(fig.1) coupled between a first-voltage rail (i.e. Vdd)(fig.1) and a second-voltage rail (i.e. Vss)(fig.1); and at least one electrostatic discharge circuit (refer to diodes 11 and 12)(fig.1), coupled between the first-voltage rail and the second-voltage rail (implicit) and coupled to an input/output (I/O) port (i.e. I/O port 13)(fig.1), comprising: an ESD element (i.e. diode 11)(fig.1) with an anode thereof coupled to the I/O port (implicit), and a cathode of the ESD element is coupled to the first-voltage rail (implicit); and a diode (i.e. diode 12)(fig.1) with a cathode thereof coupled to the anode of the ESD element and the I/O port (implicit)(refer to fig.1), and an anode of the diode is coupled to the second-voltage rail (implicit)(refer to fig.1); wherein an absolute value of a reverse breakdown voltage of the diode is greater than an absolute value of an anode-to-cathode trigger voltage of the ESD element (inherent)(the circuit would not work correctly if this were not true); however, AAPA does not teach the ESD element being a silicon-controlled rectifier and the absolute value of the anode-to-cathode trigger voltage of the silicon-controlled rectifier is greater than an absolute value of a trigger voltage of the clamping bipolar junction transistor; wherein the silicon-controlled rectifier includes a parasitic PNP bipolar junction transistor and a parasitic NPN bipolar junction transistor and a base of the parasitic PNP bipolar junction transistor is decoupled to the I/O port. However, Avery teaches the ESD element being a silicon-controlled rectifier (refer to transistors Q1 and Q2)(fig.2)(refer also to col. 3 lines 1-2); wherein the silicon-controlled rectifier includes a parasitic PNP bipolar junction transistor (i.e. Q2)(fig.2) and a parasitic NPN bipolar junction transistor (i.e. Q1)(fig.2) and a base of the parasitic PNP bipolar junction transistor is decoupled to the I/O port (implicit)(refer to Q2 and bond pad 28)(fig.2). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the electrostatic discharge protection device of AAPA to replace the diode 11 with the SCR of Avery to provide the advantage of using a device with a lower on-state, superior clamping voltage, and smaller size in order to handle higher power transients. However, AAPA and Avery do not teach the absolute value of the anode-to-cathode trigger voltage of the silicon-controlled rectifier is greater than an absolute value of a trigger voltage of the clamping bipolar junction transistor. However, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have wherein the absolute value of the anode-to-cathode trigger voltage of the silicon-controlled rectifier is greater than an absolute value of a trigger voltage of the clamping bipolar junction transistor, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the electrostatic discharge protection device of AAPA and Avery to include wherein the absolute value of the anode-to-cathode trigger voltage of the silicon-controlled rectifier is greater than an absolute value of a trigger voltage of the clamping bipolar junction transistor; to provide the advantage of turning the clamping transistor on before the SCR to prevent ESD from flowing to the I/O port and causing damage.
Regarding claim 3, AAPA and Avery teach the electrostatic discharge protection device according to claim 1, wherein the clamping bipolar junction transistor is an NPN bipolar junction transistor whose base is electrically floating, an NPN bipolar junction transistor whose emitter is coupled to its base, a PNP bipolar junction transistor whose base is electrically floating, or a PNP bipolar junction transistor whose emitter is coupled to its base (refer to AAPA bipolar junction transistor 10)(fig.1).
Claim(s) 2 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over AAPA and Avery as applied to claim 1 above, and further in view of Mallikarjunaswamy U.S. Patent No. 10,141,300 (hereinafter “Mallikarjunaswamy”).
Regarding claim 2, AAPA and Avery teach the electrostatic discharge protection device according to claim 1; however, they do not teach wherein the at least one electrostatic discharge circuit comprises a plurality of electrostatic discharge circuits. However, Mallikarjunaswamy teaches wherein the at least one electrostatic discharge circuit comprises a plurality of electrostatic discharge circuits (refer to I/O1 to I/ON and TVS devices 15)(fig.3). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the electrostatic discharge protection device of AAPA and Avery to include the multiple circuits of Mallikarjunaswamy to provide the advantage of protecting an entire circuit including multiple inputs/outputs.
Regarding claim 4, AAPA and Avery teach the electrostatic discharge protection device according to claim 1, however, they do not teach wherein the first-voltage rail is electrically floating. However, Mallikarjunaswamy teaches wherein the first-voltage rail is electrically floating (refer to N1 (Floating))(fig.4). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the electrostatic discharge protection device of AAPA and Avery to include the floating first-voltage rail of Mallikarjunaswamy to provide the advantage of balancing charge between I/O ports.
Allowable Subject Matter
Claims 5-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for the indication of allowable subject matter: Claims 5 and 6 indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 5, especially wherein the silicon-controlled rectifier comprises: an N-type semiconductor substrate decoupled to the I/O port; a first P-type well formed in the N-type semiconductor substrate; a first P-type heavily-doped area and a first N-type heavily-doped area formed in the first P-type well and coupled to the first-voltage rail; and a second P-type heavily-doped area formed in the N-type semiconductor substrate and coupled to the I/O port and the cathode of the diode, wherein the first P-type heavily-doped area, the first P-type well, the N-type semiconductor substrate, and the second P-type heavily-doped area form the parasitic PNP bipolar junction transistor, the first N-type heavily-doped area, the first P-type well, and the N-type semiconductor substrate form the parasitic NPN bipolar junction transistor, the clamping bipolar junction transistor and the diode are formed in the N-type semiconductor substrate, and the diode is formed between the clamping bipolar junction transistor and each of the first P-type well and the second P-type heavily-doped area; wherein the diode comprises: a second P-type well formed in the N-type semiconductor substrate; and a second N-type heavily-doped area and a third P-type heavily-doped area formed in the second P-type well, wherein the second N-type heavily-doped area is coupled to the second P-type heavily-doped area and the I/O port and the third P-type heavily-doped area is coupled to the second-voltage rail; wherein the clamping bipolar junction transistor comprises: a third P-type well formed in the N-type semiconductor substrate; and a third N-type heavily-doped area and a fourth N-type heavily-doped area formed in the third P-type well and respectively coupled to the second-voltage rail and the first-voltage rail. Claim 6 is indicated as containing allowable subject matter based on its dependency on claim 5. Claims 7 and 8 are indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 7, especially a semiconductor substrate, at least one first isolation trench, and at least one second isolation trench, and the silicon-controlled rectifier comprises: an N-type epitaxial layer formed on the semiconductor substrate, wherein the at least one first isolation trench and the at least one second isolation trench, formed in the N-type epitaxial layer and the semiconductor substrate, divides the N-type epitaxial layer into at least one first N-type epitaxial region, at least one second N-type epitaxial region, and a third N-type epitaxial region, the diode and the clamping bipolar junction transistor are respectively formed in the at least one second N-type epitaxial region and the third N-type epitaxial region, and the at least one first N-type epitaxial region is decoupled to the I/O port; a first P-type well formed in the at least one first N-type epitaxial region; a first P-type heavily-doped area and a first N-type heavily-doped area formed in the first P-type well and coupled to the first-voltage rail; and a second P-type heavily-doped area formed in the at least one first N-type epitaxial region and coupled to the I/O port and the cathode of the diode, wherein the first P-type heavily-doped area, the first P-type well, the at least one first N-type epitaxial region, and the second P-type heavily-doped area form the parasitic PNP bipolar junction transistor, and the first N-type heavily-doped area, the first P-type well, and the at least one first N-type epitaxial region form the parasitic NPN bipolar junction transistor; wherein the diode comprises: a second P-type well formed in the at least one second N-type epitaxial region; and a second N-type heavily-doped area and a third P-type heavily-doped area formed in the second P-type well, wherein the second N-type heavily-doped area is coupled to the second P-type heavily-doped area and the I/O port and the third P-type heavily-doped area is coupled to the second-voltage rail; wherein the clamping bipolar junction transistor comprises: a third P-type well formed in the third N-type epitaxial region; and a third N-type heavily-doped area and a fourth N-type heavily-doped area formed in the third P-type well and respectively coupled to the second-voltage rail and the first-voltage rail. Claim 8 is indicated as containing allowable subject matter based on its dependency on claim 7. Claims 9 and 10 are indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 9, especially a semiconductor substrate, at least one first isolation trench, and at least one second isolation trench, and the silicon-controlled rectifier comprises: an N-type epitaxial layer formed on the semiconductor substrate, wherein the at least one first isolation trench and the at least one second isolation trench, formed in the N-type epitaxial layer and the semiconductor substrate, divides the N-type epitaxial layer into at least one first N-type epitaxial region, at least one second N-type epitaxial region, and a third N-type epitaxial region, the diode and the clamping bipolar junction transistor are respectively formed in the at least one second N-type epitaxial region and the third N-type epitaxial region, and the at least one first N-type epitaxial region is decoupled to the I/O port; a first P-type well formed in the at least one first N-type epitaxial region; a first P-type heavily-doped area and a first N-type heavily-doped area formed in the first P-type well and coupled to the first-voltage rail; and a second P-type heavily-doped area formed in the at least one first N-type epitaxial region and coupled to the I/O port and the cathode of the diode, wherein the first P-type heavily-doped area, the first P-type well, the at least one first N-type epitaxial region, and the second P-type heavily-doped area form the parasitic PNP bipolar junction transistor, and the first N-type heavily-doped area, the first P-type well, and the at least one first N-type epitaxial region form the parasitic NPN bipolar junction transistor; wherein the diode comprises: a second P-type well formed in the at least one second N-type epitaxial region; and a second N-type heavily-doped area and a third P-type heavily-doped area respectively formed in the at least one second N-type epitaxial region and the second P-type well, wherein the second N-type heavily-doped area is coupled to the second P-type heavily-doped area and the I/O port and the third P-type heavily-doped area is coupled to the second-voltage rail; wherein the clamping bipolar junction transistor comprises: a third P-type well formed in the third N-type epitaxial region; and a third N-type heavily-doped area and a fourth N-type heavily-doped area formed in the third P-type well and respectively coupled to the second-voltage rail and the first-voltage rail. Claim 10 is indicated as containing allowable subject matter based on its dependency on claim 9.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Cheng et la. U.S. Patent Application 2021/0249403 (hereinafter “Cheng”)(refer to figures 2 and 5) and Salcedo et al. U.S. Patent Application 2015/0076557 (hereinafter “Salcedo”)(refer to Figures 1A and 1B).
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/KEVIN J COMBER/Primary Examiner, Art Unit 2838