DETAILED ACTION
This action is in response to the 04/30/2026 amendment.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by US Pub. No. 2010/0026250; (hereinafter Petty).
Regarding claim 1, Petty [e.g. Figs. 1 and 3] discloses a voltage conversion device comprising: a first regulator [e.g. T101] configured to convert an input voltage of an input node [e.g. VDD] into a first output voltage [e.g. voltage at lower terminal of the pass transistor] in a first mode [e.g. Abstract recites “A multimode voltage regulator circuit includes a linear regulator sub-circuit configured to supply current to a load in a low-current mode”] and to provide the first output voltage to an output node [e.g. OUTPUT]; a second regulator [e.g. T102, T103, L135, C150, X110] configured to convert the input voltage of the input node into a second output voltage in a second mode [e.g. high-current mode; Abstract recites “a switching regulator sub-circuit configured to supply current to the load in a high-current mode”] and to provide the second output voltage to the output node [e.g. paragraph 07 recites “Combining a switching regulator, for use when a required load current is high, with a linear regulator, for use when the load current is low”]; a mode control circuit [e.g. mode control circuit (Fig. 3) providing MODE_CTRL] configured to, upon a request to enter the first mode from the second mode [e.g. paragraph 022 "Each change in operating mode may include the activation of a MODE_CTRL signal, by a microprocessor, microcontroller, or other digital hardware, to reconfigure the voltage regulator circuit for the new operating mode”], maintain a power stage of the first regulator in a power-off state [e.g. T101 OFF during high-current mode] by controlling a level of enable signal corresponding to the power stage [e.g. level of MODE_CTRL for low-current mode]; a first resistor and a second resistor [e.g. R140 and R142] connected in series between the output node and a ground node; and an error amplifier [e.g. A125] configured to receive a feedback voltage of a node between the first resistor and the second resistor [e.g. VFEEDBACK] and a reference voltage [e.g. Output of X130], to amplify [e.g. A125] a difference between the feedback voltage [e.g. at inverting input of A125] and the reference voltage [e.g. at non-inverting input of A125] to generate an error voltage [e.g. output of A125], to provide the error voltage to the first regulator in the first mode, and to provide the error voltage to the second regulator in the second mode [e.g. paragraph 021 recites “In low-current mode, i.e., when the load's current needs are below a pre-determined threshold, the error signal produced by error amplifier A125 is routed, via switch S160, to the control path for the linear regulator sub-circuit. In high-current mode, i.e., when the load requires an operating current above the threshold, the error signal is instead routed to the control path for the switching regulator”].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Petty in view of US Pub. No. 2007/0069703; (hereinafter Kokubun).
Regarding claim 2, Petty [e.g. Fig. 1] discloses wherein, in the first mode [e.g. low-current mode], the error amplifier is configured to amplify a value obtained by subtracting the feedback voltage from the reference voltage to generate the error voltage [e.g. output of A125], and wherein, in the second mode [e.g. high-current mode], the error amplifier is configured to amplify the value obtained by subtracting the feedback voltage from the reference voltage [e.g. at inputs of A125].
Petty fails to disclose to invert the amplified value to generate the error voltage.
Kokubun teaches a first mode (PWM mode) which operates as a switching regulator and a second mode corresponding to a linear mode, and an error amplifier 31 that invert [e.g. at output S1b] the amplified value [e.g. output of amplifier 31] to generate the error voltage [e.g. S1b] corresponding to the second mode [e.g. paragraph 038 recites “The second error signal S1b changes in an inverse manner with respect to the first error signal S1a.” Paragraph 064 recites “the DC-DC converter 12 operates as a linear regulator when the second error signal S1b output to the inverting output terminal of the error amplifier 31 is provided to the gate of the output transistor T1”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Petty by to invert the amplified value to generate the error voltage as taught by Kokubun in order of being able to provide different control operations with the same error signal.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Petty.
Regarding claim 4, Petty [e.g. Fig. 1] fails to disclose wherein the first regulator includes a switching regulator, and wherein the second regulator includes a linear regulator.
Petty [e.g. Fig. 2] discloses wherein the first regulator [e.g. T202] includes a switching regulator [e.g. T202 is included in the switching regulator (T202-T103)], and wherein the second regulator [e.g. T202-T102] includes a linear regulator [e.g. T202; paragraph 029 recites “FIG. 2 illustrates a multimode voltage regulator circuit 200 in which a transistor T202 is shared between the linear regulator sub-circuit and the switching regulator sub-circuit, transistor T202 acting as a variable-resistance pass transistor in the low-current mode and as a low-on-resistance switching transistor in the high-current mode”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Petty by wherein the first regulator includes a switching regulator, and wherein the second regulator includes a linear regulator as taught by Petty, Fig. 2 in order of being able to reduce the overall circuit size and/or cost, paragraph 029.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Petty in view of US Pub. No. 2017/0279359; (hereinafter Goncalves).
Regarding claim 5, Petty [e.g. Fig. 1] discloses wherein the first regulator includes: a voltage converter connected to the input node and the output node and including a plurality of switches [e.g. T102, T103], at least one inductor [e.g. L135], and at least one capacitor [e.g. C150]; a control circuit [e.g. X110] configured to generate control signals [e.g. output of X110] corresponding to the plurality of switches such that the input voltage of the input node is converted into the first output voltage, the first output voltage being transferred to the output node [e.g. paragraph 08 recites “a switching regulator sub-circuit configured to supply current to the load in a high-current mode, responsive to a second control signal from a second control path”].
Petty fails to disclose a power stage configured to control the plurality of switches based on the control signals.
Goncalves [e.g. Fig. 12A] teaches a power stage [e.g. 1242] configured to control the plurality of switches [e.g. 1204, 1206] based on the control signals [e.g. 1266, 1268].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Petty by a power stage configured to control the plurality of switches based on the control signals as taught by Goncalves in order of being able to provide proper control of the power switches of the voltage converter so as to improve efficiency, Abstract.
Examiner's Note
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on the previous ground of rejection. Specifically in the current rejection, the first regulator corresponds to the linear regulator, the first mode corresponds to the low-current mode, the second regulator corresponds to the switching regulator and the second mode corresponds to the high-current mode.
Allowable Subject Matter
Claims 17 – 20 are allowed.
Claims 3 and 6 – 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the indication of the allowability of claim 3 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “a second switch configured to transfer the error voltage to the second regulator in the second mode and to block the error voltage from being transferred to the second regulator in the first mode”.
The primary reason for the indication of the allowability of claim 6 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein, when a transition from the second mode to the first mode is made, the control circuit is configured to preset the error voltage and switching timings of the control signals based on the error voltage, the input voltage, and the first output voltage”.
The primary reason for the indication of the allowability of claim 12 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein, in the first mode, the control circuit is configured to: generate emulated duty signals based on the input voltage and the first output voltage; control a ramp signal based on the emulated duty signals; and control switching timings of the control signals based on the error voltage and the ramp signal, wherein the emulated duty signals include an emulated buck duty signal and an emulated boost duty signal, and wherein the control signals include a buck duty signal and a boost duty signal.
The primary reason for the indication of the allowability of claim 17 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein, in the first mode, the control circuit is configured to: generate emulated duty signals based on the input voltage and the first output voltage; control a ramp signal based on the emulated duty signals; and control switching timings of the control signals based on an error voltage and the ramp signal.”
The primary reason for the indication of the allowability of claim 20 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “when a transition from the second mode to the first mode is made, presetting switching timings while the output voltage is not provided by the switching regulator and is not provided by the linear regulator.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alex Torres-Rivera whose telephone number is (571)272-5261. The examiner can normally be reached M-F 9:00-5:30 ET.
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/ALEX TORRES-RIVERA/Primary Examiner, Art Unit 2838
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