Prosecution Insights
Last updated: April 19, 2026
Application No. 18/663,579

COMPUTATION SYSTEM

Non-Final OA §103
Filed
May 14, 2024
Examiner
COLEMAN, STEPHEN P
Art Unit
2675
Tech Center
2600 — Communications
Assignee
Mirise Technologies Corporation
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
96%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allow Rate
737 granted / 877 resolved
+22.0% vs TC avg
Moderate +12% lift
Without
With
+11.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
47 currently pending
Career history
924
Total Applications
across all art units

Statute-Specific Performance

§101
12.5%
-27.5% vs TC avg
§103
45.5%
+5.5% vs TC avg
§102
27.0%
-13.0% vs TC avg
§112
6.8%
-33.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 877 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION INFORMATION DISCLOSURE STATEMENT The information disclosure statement (IDS) submitted on 05/14/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. FOREIGN PRIORITY A claim for foreign priority under 35 U.S.C § 119 (a) - (d), which was contained in the Declaration and Power of Attorney filed on 05/14/2024 has been acknowledged. Acknowledgement of claimed foreign priority and receipt of priority documents is reflected in form PTO-326 Office Action Summary. CLAIM INTERPRETATIONS - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph: (A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function. Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function. Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure`, material or acts to entirely perform the recited function. Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “anomaly detection unit” “a computation allocation unit” in claim 1. ALLOWABLE SUBJECT MATTER Claims 7-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. CLAIM REJECTIONS - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-6 & 9 are rejected under 35 U.S.C. 103 as being unpatentable over Bose et al. (U.S. Publication 2019/0138903) in view of Chandra et al. (U.S. Publication 2019/0266015) As to claim 1, Bose discloses a computation system for performing a computation process using a neural network model (Fig. 1 & [0032] discloses “DNN models runs on various streams to create DNN workload.” [0035] discloses execution of DNN workloads on cores (system performing NN computations)), the computation system comprising: a plurality of processor cores that execute the computation process (Fig. 1 & [0035] discloses available cores 116A, 116B, 116C, and 116D. [0138] discloses the DNN workloads are executed on the assigned processing core); a computation allocation unit that determines a computation processor core, which is one of the plurality of processor cores and is to execute the computation process, according to a computation load of the computation process, and causes the computation processor core to execute the computation process (Fig. 1 & [0035] discloses framework include an allocator 106 to handle system resource allocation executed on available cores, [0054] allocator 106 assigns each DNN workload to a specific core based on CPU utilization. [0138] the DNN workloads are executed on the assigned processing core); Bose is silent to an anomaly detection unit that detects presence or absence of an anomaly in the computation processor core, wherein: the computation allocation unit causes at least a part of the plurality of processor cores different from the computation processor core to execute an anomaly detection computation prepared based on a basic computation, which is the computation process to be executed by the computation processor core, in parallel to the basic computation; when a difference between a first computation result, which is a computation result of the basic computation, and a second computation result, which is a computation result of the anomaly detection computation, satisfies a predetermined allowance condition, the anomaly detection unit determines that the computation processor core and an anomaly detection processor core that executes the anomaly detection computation are normal; and when the difference does not satisfy the allowance condition, the anomaly detection unit determines that at least a part of the computation processor core and the anomaly detection processor core has anomaly. However, Chandra discloses an anomaly detection unit that detects presence or absence of an anomaly in the computation processor core ([0021] discloses if a violation occurs the overall system indicates the possibility of a fault), wherein: the computation allocation unit causes at least a part of the plurality of processor cores different from the computation processor core to execute an anomaly detection computation prepared based on a basic computation, which is the computation process to be executed by the computation processor core, in parallel to the basic computation ([0021] discloses a neural network program and one or more checker neural networks execute on available computational hardware. [0026] discloses neural network program 201 is run on an accelerator-1 check neural network program on accelerator-2); when a difference between a first computation result, which is a computation result of the basic computation, and a second computation result, which is a computation result of the anomaly detection computation, satisfies a predetermined allowance condition, the anomaly detection unit determines that the computation processor core and an anomaly detection processor core that executes the anomaly detection computation are normal ([0021-0022] discloses expected correlation is determined. If a violation occurs indicates fault.); and when the difference does not satisfy the allowance condition, the anomaly detection unit determines that at least a part of the computation processor core and the anomaly detection processor core has anomaly ([0021-0022] discloses expected correlation is determined. If a violation occurs indicates fault.). It would have been obvious to one of ordinary skill in the art at the time of effective filing to modify Bose’s disclosure to include the above limitations in order to detect runtime anomalies/faults in the selected processing core while maintaining Chadra’s load based allocation efficiency and avoiding full N-way replication overhead. As to claim 2, Bose in view Chandra of discloses everything as disclosed in claim 1 but is silent to wherein: the anomaly detection unit detects the presence or absence of the anomaly by using the first computation result and the second computation result output in parallel with the first computation result. However, Chandra discloses wherein: the anomaly detection unit detects the presence or absence of the anomaly by using the first computation result and the second computation result output in parallel with the first computation result. ([0026] discloses two accelerators produce output 203 and checker output 204 with an accuracy recorder.) It would have been obvious to one of ordinary skill in the art at the time of effective filing to modify Bose in view Chandra’s disclosure to include the above limitations in order to detect anomalies/faults by comparing parallel results. As to claim 3, Bose in view Chandra of discloses everything as disclosed in claim 1. In addition, Bose discloses [0106] wherein the scheduler 108 may keep track of the results of previous inputs. [0140] wherein main memory 1204 and storage device 1216 with instructions stored. Bose in view Chandra is silent to a semiconductor memory device that stores the first computational result. Anomaly detection uses the first computation result read and the second computational result output after the first computation result. However, Chandra discloses single accelerator can be time multiplexed producing output 303 and checker output 304. [0027-0028] It would have been obvious to one of ordinary skill in the art at the time of effective filing to modify Bose in view Chandra’s disclosure to include the above limitations in order to enable anomaly detection even when the checker result is produced after the first result. As to claim 4, Bose in view Chandra of discloses everything as disclosed in claim 1. In addition, Bose discloses layers including convolutional layers and fully connected layers at the end. [0110-0115]. This supports that a DNN has multiple layers and final layers. Bose in view Chandra is silent to using final/intermediate layer computation results as first and second results for anomaly detection. However, Chandra discloses comparing output 203 vs. checker output 204 [0026]. [0028] discloses selective N-MR at neuron level; computations of a single neuron are repeated. It would have been obvious to one of ordinary skill in the art at the time of effective filing to modify Bose in view Chandra’s disclosure to include the above limitations in order to anomalies using final and/or intermediate layer results. As to claim 5, Bose in view Chandra of discloses everything as disclosed in claim 1 but is silent to wherein: the computation allocation unit causes the anomaly detection processor core to execute a computation process same as the basic computation as the anomaly detection computation; and the allowance condition includes a condition that the first computation result and the second computation result match each other. ([0026] discloses checker neural network runs on different accelerator while main network runs. [0029] discloses coalescer can be an equality checker that repeats the computations until equality is reached.) It would have been obvious to one of ordinary skill in the art at the time of effective filing to modify Bose in view Chandra’s disclosure to include the above limitations in order to ensure correctness by requiring matching results when running a duplicated computation as the anomaly detection computation. As to claim 6, Bose in view Chandra of discloses everything as disclosed in claim 1. In addition, Bose discloses [0045] discussing reduced precision lowering resource requirements. Bose in view Chandra is silent to a checker “light weight computation” trained in advanced for anomaly detection and thresholded difference for anomaly detection. However, Chandra discloses checker network is significantly smaller in terms of computational time [0025]. [0021] discloses during training, the expected correlation is determined. If a violation occurs. It would have been obvious to one of ordinary skill in the art at the time of effective filing to modify Bose in view Chandra’s disclosure to include the above limitations in order to detect anomalies with lower overhead by running a smaller checker computation and thresholding output differences. As to claim 9, Bose in view Chandra of discloses everything as disclosed in claim 1. In addition, Bose discloses [0140] hardware processor 102, main memory 1204. [0142] discloses storage media stored instructions and instructions reside within the main memory. [0035] discloses available cores 116A-116D and allocator. Bose in view Chandra is silent to describe the anomaly detection unit. However, Chandra discloses accuracy recorder indicates fault. [0021] It would have been obvious to one of ordinary skill in the art at the time of effective filing to modify Bose in view Chandra’s disclosure to include the above limitations in order to implement the anomaly detection unit alongside Bose’s core allocator. CONCLUSION No prior art has been found for claims 7-8 in their current form. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Stephen P Coleman whose telephone number is (571)270-5931. The examiner can normally be reached Monday-Thursday 8AM-5PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Moyer can be reached at (571) 272-9523. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. Stephen P. Coleman Primary Examiner Art Unit 2675 /STEPHEN P COLEMAN/Primary Examiner, Art Unit 2675
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Prosecution Timeline

May 14, 2024
Application Filed
Feb 11, 2026
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
96%
With Interview (+11.6%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 877 resolved cases by this examiner. Grant probability derived from career allow rate.

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