DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Giannini et al. (US 2008/0256396 A1) and further in view of KATO et al. (US 2024/0394168 A1).
As per claim 1, Kato et al. teaches the invention as claimed including, “A method for tracing a cyclic program execution of a processing circuit of an integrated circuit, the method comprising:
capturing, by a trace unit of the integrated circuit, trace snippets during respective occurrences of a hyper-period of the cyclic program execution of the processing circuit;
storing the trace snippets in a trace buffer of the integrated circuit; and”
Giannini et al. teaches an embedded trance microcell (ETM) unit of DSP 40 that captures in real-time detailed information about the software execution flow (0054). The ETM is configured to capture only select trace information and only after a specific sequence of conditions (0055). ETM generates an instruction trace as a recording of the full progression of the program counter for a thread over a given window of time. The timing of the program counter progression can also be included in an instruction trace (0060). The ETM monitors the DSP pipeline and performing filtering/triggering and compression/packetization. The compression/packetization unit takes the DSP execution information and efficiently forms it into packets that are sent out of ETM through the trace port into a trace repository that provides a large memory capacity for recording trace records and may be either off-chip or on-chip such as an embedded trace buffer (ETB). (0058). ETM generates instruction traces which are a record of the execution flow for a thread over a given window of time (0064). The execution of multiple instruction sequences occurring concurrently and during which DSP 40 may be viewed as several single-threaded processors operating independently. In ETM, program flow in broken into a sequence of packets and that include thread number fields to certain packets to identify which packet belongs to which thread (0072).
“reconstructing, by a processor coupled to the integrated circuit, the hyper-period by combining overlapping portions of the trace snippets from the trace buffer.”
Debug host takes the packet stream from the trace repository and along with the program image reconstructs the execution flow of DSP, giving the user a detailed visibility into the DSP pipeline (0058). After a trace session, the packets allow for reconstructing the thread execution (0073).
However, Giannini et al. does not explicitly appear to teach, “trace snippets during respective occurrences of a hyper-period of the cyclic program execution”
KATO et al. teaches, the calculation of a hyper period. The hyper period is the least common multiple of the execution cycle of the software operated in a device. This period/time can be measured in milliseconds (0160).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Giannini et al. with KATA et al. Giannini et al. teaches the ETM generates instruction traces which are a record of the execution flow for a thread over a given window of time (0064). KATA et al. teaches determining a hyper period as a time window. A hyper period is a well-known time period. Using this time period as the window of time for Giannini et al. is nothing more than a design choice and would have been obvious to try.
As per claim 2, Giannini et al. further teaches, “The method of claim 1, wherein the capturing comprises:
capturing the trace snippets at different time delays from starts of the respective occurrences of the hyper-period.”
ETM may be configured to capture only select trace information and only after a specific sequence of conditions (0055). ETM generates an instruction trace as a recording of the full progression of the program counter for a thread over a given window of time. The timing of the program counter progression can also be included in an instruction trace. The event resource mechanisms are used to define when to generate these instruction traces (0060). ETM generates instruction traces which are a record of the execution flow for a thread over a given window of time (time period) (0064). As can be seen in figure 8 there are 5 different traces t0-t4 of different threads that start at different times (delays). Also see paragraphs 0074-0075.
As per claim 3, Giannini et al. further teaches, “The method of claim 1, wherein the trace snippets comprise program flow information and/or task information.”
Giannini et al. teaches an embedded trace microcell (ETM) unit of DSPs 40 that captures in real-time detailed information about the software execution flow (0054). The ETM program flow is broken down into a sequence of packets that include their thread number fields, that identify which packet belongs to which thread (0072).
As per claim 4, Giannini et al. further teaches, “The method of claim 3, wherein the program flow information and/or task information comprises call information and/or return information.”
ETM generates instruction traces which are a record of the execution flow for a thread over a given window of time (0064). The ETM program flow is broken down into a sequence of packets that include their thread number fields that identify which packet belongs to which thread (0072). Inter-thread execution timing relationships at any given point for one thread is maintained. This gives the ability to observe operations and states of all threads for debugging and other important purposes (0074). Operations and state include thread initiation (call information) (0075). Also see figure 8.
As per claim 5, Giannini et al. further teaches, “The method of claim 1, wherein the trace snippets are associated with a same task.”
ETM generates instruction traces which are a record of the execution flow for a thread over a given window of time (0064). The ETM program flow is broken down into a sequence of packets that include their thread number fields that identify which packet belongs to which thread (0072). After a trace session, the packets allow for reconstructing the thread execution (0073).
As per claim 7, Giannini et al. further teaches, “The method of claim 1, wherein each of the trace snippets comprises a position of a task within the hyper-period.”
Giannini et al. teaches ETM generates an instruction trace as a recording of the full progression of the program counter for a thread over a given window of time. The timing of the program counter procession can also be included in an instruction trace (0060). A inter-thread trace alignment process is performed and time starts at T=0. For various threads, thread initiation may occur at different points in time (0075). The ETM program flow is broken down into a sequence of packets that include their thread number fields that identify which packet belongs to which thread. For identifying inter-thread timing relationships, the present disclosure establishes and maintains timing relationships between different threads (0072). Also see figure 8.
As per claim 8, Giannini et al. et al. further teaches, “The method of claim7, wherein the position of the task within the hyper-period is a time offset from a start of the hyper-period.
Teaches ETM generates an instruction trace as a recording of the full progression of the program counter for a thread over a given window of time. The timing of the program counter progression can also be included in an instruction trace (0060). The method and system establish the relative timing of the threads execution sequences by marking the offset between when a thread runs on tracing and when other threads have turned on and do subsequently turn on tracing. After a trace session, the packets allow for reconstructing the thread. Using offset-fields, the execution section sequence may be properly aligned among the threads (0072-0073). A inter-thread trace alignment process is further taught. Time starts at T=0. For various threads, thread initiation may occur at different points in time (0075). The ETM program flow is broken down into a sequence of packets that include their thread number fields that identify which packet belongs to which thread. For identifying inter-thread timing relationships, the present disclosure establishes and maintains timing relationships between different threads (0072). As can be seen in figure 8 there are 5 different traces t0-t4 of different threads, start at different times (offsets). Also see paragraphs 0074-0075.
As per claim 9, Giannini et al. et al. further teaches, “The method of claim 1, wherein the capturing comprises: capturing the trace snippets at random time delays from starts of the respective occurrences of the hyper-period.”
ETM may be configured to capture only select trace information and only after a specific sequence of conditions (0055). ETM generates an instruction trace as a recording of the full progression of the program counter for a thread over a given window of time. The timing of the program counter progression can also be included in an instruction trace. The event resource mechanisms are used to define when to generate these instruction traces (0060). ETM generates instruction traces which are a record of the execution flow for a thread over a given window of time (time period) (0064). As can be seen in figure 8 there are 5 different traces t0-t4 of different threads that start at different times (delays). Also see paragraphs 0074-0075. The method and system establish the relative timing of the threads execution sequences by marking the offset between when a thread turns on tracing and when other threads have turned on and do subsequently turn on tracing. After a trace session, the packets allow for reconstructing the thread. Using offset-fields, the execution section sequence may be properly aligned among the threads (0072-0073). A inter-thread trace alignment process is further taught. Time starts at T=0. For various threads, thread initiation may occur at different points in time (0075).
As per claim 10, claim 10 contains similar limitations as claim 1 and is rejected for similar reasons.
As per claim 11, Giannini et al. et al. further teaches, “The system of claim 10, wherein the trace unit comprises:
a coder operable to capture the trace snippets;”
Giannini et al. teaches an embedded trance microcell (ETM) unit of DSP 40 that captures in real-time detailed information about the software execution flow (0054). The ETM is configured to capture only select trace information and only after a specific sequence of conditions (0055).
“registers operable to store trace capture trigger information; and”
See figure 2.
“a timer operable to enable, based on the trace capture trigger information received from the registers, the coder to start the capture of each of the trace snippets.”
Giannini et al. teaches ETM generates an instruction trace as a recording of the full progression of the program counter for a thread over a given window of time. The timing of the program counter progression can also be included in an instruction trace (0060). The ETM monitors the DSP pipeline and performing filtering/triggering and compression/packetization. An embedded trace microcell (ETM) that is configured to capture only select trace information and only after a specific sequence of conditions (0055). The ETM monitors the DSP pipeline and performing filtering/triggering and compression/packetization. The compression/packetization unit takes the DSP execution information and efficiently forms it into packets that are sent out of ETM through the trace port into a trace repository that provides a large memory capacity for recording trace records and may be either off-chip or on-chip such as an embedded trace buffer (ETB). (0058). ETM generates instruction traces which are a record of the execution flow for a thread over a given window of time (0064). The execution of multiple instruction sequences occurring concurrently and during which DSP 40 may be viewed as several single-threaded processors operating independently. In ETM, program flow in broken into a sequence of packets and that include thread number fields to certain packets to identify which packet belongs to which thread (0072). Giannini et al. teaches the ETM may generate ISDB breakpoint trigger events, external trigger events and DSP interrupts (0059). Also see figure 2 and 8.
As per claim 12, Giannini et al. et al. further teaches, “The system of claim 11, wherein the trace capture trigger information is task identification information and/or time delays from starts of the respective occurrences of the hyper-period, and the processor is operable to write the trace capture trigger information into the registers.”
Giannini et al. teaches ETM generates an instruction trace as a recording of the full progression of the program counter for a thread over a given window of time. The timing of the program counter progression can also be included in an instruction trace (0060). The ETM monitors the DSP pipeline and performing filtering/triggering and compression/packetization. An embedded trace microcell (ETM) that is configured to capture only select trace information and only after a specific sequence of conditions (0055). The ETM monitors the DSP pipeline and performing filtering/triggering and compression/packetization. The compression/packetization unit takes the DSP execution information and efficiently forms it into packets that are sent out of ETM through the trace port into a trace repository that provides a large memory capacity for recording trace records and may be either off-chip or on-chip such as an embedded trace buffer (ETB). (0058). ETM generates instruction traces which are a record of the execution flow for a thread over a given window of time (0064). The execution of multiple instruction sequences occurring concurrently and during which DSP 40 may be viewed as several single-threaded processors operating independently. In ETM, program flow in broken into a sequence of packets and that include thread number fields to identify which packet belongs to which thread (0072). Giannini et al. teaches the ETM may generate ISDB breakpoint trigger events, external trigger events and DSP interrupts (0059). Also see figure 2 and 8.
As per claims 13-16 and 18-20, they contain similar limitations to claims 2-5 and 7-9 and are therefore rejected for similar reasons.
Claims 6 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Giannini et al. (US 2008/0256396 A1) and KATO et al. (US 2024/0394168 A1) as applied to claims 5 and 16 above and further in view of Horsnell et al. (US 2014/0013020 A1).
As per claim 6, Giannini et al. does not explicitly appear to teach, “The method of claim 5, wherein the capturing is paused during an interrupt that occurs during the same task.”
Horsnell et al. teaches a performance monitoring interrupt signal that can trigger a data processing apparatus to start or stop capturing the performance monitoring data. The performance monitoring data generated by the performance monitoring circuit may only be of interest when a performance-related problem is detected (0043).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Giannini et al. with Horsnell et al. Giannini et al. teaches an embedded trace microcell (ETM) that is configured to capture only select trace information and only after a specific sequence of conditions (0055). Giannini et al. teaches the ETM may generate ISDB breakpoint trigger events, external trigger events and DSP interrupts (0059). However, Giannini et al. does not explicitly appear to teach “wherein the capturing is paused during an interrupt that occurs during the same task”. Horsnell et al. teaches a performance monitoring interrupt signal that can trigger a data processing apparatus to start or stop (pause) capturing the performance monitoring data. The performance monitoring data generated by the performance monitoring circuit may only be of interest when a performance-related problem is detected (0043). Horsnell et al. will allow Giannini et al. to turn on or off its monitoring based on conditions/problem detection. Using this known technique will improve the monitoring of Giannini et al, allowing it to only collect data when necessary and would have been obvious to try.
As per claim 17, it contains similar limitations to claim 6 and is therefore rejected for similar reasons.
Conclusion
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/MARK A GOORAY/ Examiner, Art Unit 2199
/LEWIS A BULLOCK JR/ Supervisory Patent Examiner, Art Unit 2199
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