DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Non-Final communication in response to communication filed 5/14/24.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 11989050. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims are substantially similar and cover the same subject matter.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7-12, 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lim et al. [20190140647] in view of Arp et al. [20180331676].
With respect to claim 1, figures 4-7 of Lim et al. disclose a method for clock delay compensation in a multiple chiplet/sub-circuit system [102, 104], comprising:
distributing a clock signal [210] to a plurality of chiplets/sub-circuit [104, 102];
for a chiplet/sub-circuit [102] of the plurality of chiplets/sub-circuit, delaying propagation of the clock signal through a distribution tree of the chiplet/sub-circuit [fig. 4, 133, in 104], wherein the delaying is based on a delay offset [174, figs. 5-7] and a local delay offset [162, figs 5-7] that are based on phase measurements indicative of propagation speed of the clock signal through a plurality of paths of the distribution tree.
Lim et al. does not disclose specifically a chiplet.
However, Arp et al. discloses a multiple sub-circuit system [Fig. 1] with clocking system for skew reduction in Fig. 2.
It would have been obvious to one skilled in the art at the time the invention was made to use the clocking system of Lim et al. for a multiple chiplet/sub-circuit system.
With respect to claim 2, figures 4-7 of Lim et al. disclose the method of claim 1, wherein the distributing comprises distributing, by a clock generator [generates 210], of the clock signal, across distribution trees of the plurality of chiplets, wherein the distribution trees include the distribution tree of the chiplet.
With respect to claim 3, figures 4-7 of Lim et al. disclose the method of claim 1, further comprising: measuring, by a plurality of phase detectors [162,172] of the plurality of chiplets, a plurality of phase measurements including the phase measurement.
With respect to claim 4, figures 4-7 of Lim et al. disclose the method of claim 1, wherein the phase measurement is further indicative of a difference [174] in arrival times of the clock signal to a first sink point, which feeds a first logic unit[150D] of the chiplet, and to a second sink point, which feeds a second logic unit [150C] in a second chiplet [104].
With respect to claim 7, figures 4-7 of Lim et al. disclose the method of claim 1, further comprising: for each respective chiplet of the plurality of chiplets: determining, based on a respective phase measurement associated with the respective chiplet [162s], local delay offsets; and delaying, based on the local delay offsets, propagation of the clock signal through respective paths of a distribution tree of the respective chiplet.
With respect to claim 8, figures 4-7 of Lim et al. disclose the method of claim 1, wherein the delay offset comprises a global delay offset. [delays 174 provided to all branches of clock trees in 102, 104]
With respect to claim 9, the above combination discloses a system [50] comprising: at least one processor [Arp et al. paragraph 0108-0110]; and memory storing instructions that, when executed by the at least one processor, cause the system to: distribute the clock to: distribute a clock signal to a plurality of chiplets;
for a chiplet of the plurality of chiplets, delay propagation of the clock signal through a distribution tree of the chiplet, wherein the delaying is based on a delay offset and a local delay offset that are based on phase measurements indicative of propagation speed of the clock signal through a plurality of paths of the distribution tree.
With respect to claim 10, the above combination discloses the system of claim 9, wherein the distributing comprises distributing, by a clock generator, of the clock signal, across distribution trees of the plurality of chiplets, wherein the distribution trees include the distribution tree of the chiplet. [see claim 2]
With respect to claim 11, the above combination discloses the system of claim 9, wherein the instructions further cause the system to: measure, by a plurality of phase detectors of the plurality of chiplets, a plurality of phase measurements including the phase measurement. [see claim 3]
With respect to claim 12, the above combination discloses the system of claim 9, wherein the phase measurement is further indicative of a difference in arrival times of the clock signal to a first sink point, which feeds a first logic unit of the chiplet, and to a second sink point, which feeds a second logic unit in a second chiplet. [See claim 4]
With respect to claim 15, the above combination discloses the system of claim 9, wherein the instructions further cause the system to: for each respective chiplet of the plurality of chiplets: determining, based on a respective phase measurement associated with the respective chiplet, local delay offsets; and delaying, based on the local delay offsets, propagation of the clock signal through respective paths of a distribution tree of the respective chiplet. [see claim 7]
With respect to claim 16, the above combination discloses the system of claim 9, wherein the delay offset comprises a global delay offset. [see claim 8]
With respect to claim 17, the above combination discloses a non-transitory computer-readable medium storing instructions that, when executed by a processor, cause the processor to perform operations comprising: distributing a clock signal to a plurality of chiplets;
for a chiplet of the plurality of chiplets, delaying propagation of the clock signal through a distribution tree of the chiplet, wherein the delaying is based on a delay offset and a local delay offset that are based on phase measurements indicative of propagation speed of the clock signal through a plurality of paths of the distribution tree. [see claim 9]
With respect to claim 18, the above combination discloses the non-transitory computer-readable medium of claim 17, wherein the distributing comprises distributing, by a clock generator, of the clock signal, across distribution trees of the plurality of chiplets, wherein the distribution trees include the distribution tree of the chiplet. [see claim 10]
With respect to claim 19, the above combination discloses the non-transitory computer-readable medium of claim 17, wherein the operations further comprise: measuring, by a plurality of phase detectors of the plurality of chiplets, a plurality of phase measurements including the phase measurement. [see claim 11]
With respect to claim 20, the above combination discloses the non-transitory computer-readable medium of claim 17, wherein the phase measurement is further indicative of a difference in arrival times of the clock signal to a first sink point, which feeds a first logic unit of the chiplet, and to a second sink point, which feeds a second logic unit in a second chiplet. [see claim 12]
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN C JAGER whose telephone number is (571)272-7016. The examiner can normally be reached on 8:30 - 5:30 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lincoln Donovan can be reached on 571-272-7016. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RYAN JAGER/
Primary Examiner, Art Unit 2842
1/21/26