DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in the application.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement(s) (IDS), Form PTO-1449, filed 14 May 2024. The information therein was considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 2021/0257474) (hereinafter, “Lee”).
Re: independent claim 1, Lee discloses in figs. 1-4B an integrated circuit device comprising: a fin-type active region (AF1) extending in a first lateral direction (x-direction) on a substrate (100); a pair of insulating spacers (140) extending in a second lateral direction (y-direction) on the fin-type active region and the substrate, wherein the pair of insulating spacers defining a first space, and the second lateral direction intersects with the first lateral direction; a gate line (120) covering the fin-type active region in the first space and extending in the second lateral direction; a gate dielectric film (130) in contact with a bottom surface of the gate line and sidewalls of the gate line in the first space, the gate dielectric film (130) extending in the second lateral direction; a gate contact plug (180) having a conductive bottom surface in contact with a top contact portion of a top surface of the gate line (120) in the first space; and a capping insulating pattern (145) comprising an insulating bottom surface, a pair of first insulating sidewalls, and a second insulating sidewall, wherein the insulating bottom surface is in contact with a local top surface adjacent to the top contact portion of the top surface of the gate line (120) in the first space, the pair of first insulating sidewalls are in contact with the pair of insulating spacers (140), and the second insulating sidewall is in contact with the gate contact plug (180), and wherein an insulating top surface (145us) of the capping insulating pattern (145) and a conductive top surface (180us) of the gate contact plug (180) extend along one plane.
Re: claim 2, Lee discloses in figs. 1-4B the integrated circuit device of claim 1, wherein a constituent material of the gate contact plug (180) has a lower electrical resistance than a constituent material of at least a portion of the gate line (120) [0100].
Re: claim 3, Lee discloses in figs. 1-4B the integrated circuit device of claim 1, wherein a top surface of each of the pair of insulating spacers (140) extends along the one plane.
Re: claim 4, Lee discloses in figs. 1-4B the integrated circuit device of claim 1, wherein the conductive bottom surface of the gate contact plug (180) comprises a first end portion, and the conductive top surface of the gate contact plug (180) comprises a second end portion, and wherein the first end portion and the second end portion are in contact with the pair of insulating spacers (140).
Re: claim 5, Lee discloses in figs. 1-4B the integrated circuit device of claim 1, wherein the gate contact plug (180) comprises a single metal film (180b in fig. 13), and wherein a metal nitride film is not between the single metal film (180b) and the pair of insulating spacers (140).
Re: claim 6, Lee discloses in figs. 1-4B the integrated circuit device of claim 1, wherein the gate contact plug (180) is integrally connected to at least a portion of the gate line (120) (fig. 13).
Re: claim 7, Lee discloses in figs. 1-4B the integrated circuit device of claim 1, further comprising: a source/drain region (150) on the fin-type active region; an insulating structure (190) covering the source/drain region; a source/drain contact (170) passing through the insulating structure in a vertical direction, wherein the source/drain contact (170) is connected to the source/drain region (150); and a via contact (172) connected to the source/drain contact (171), wherein a top surface of the via contact extends along the one plane (fig. 5).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2021/0257474) (hereinafter, “Lee”) in view of Huang et al. (US 2022/0106666) (hereinafter, “Huang”).
Re: claim 8, Lee discloses in figs. 1-4B the integrated circuit device of claim 1, wherein the gate contact plug (180) comprises a metal selected from Mo, Ru, Cu, and W [0100].
Lee does not disclose expressly wherein the gate line comprises a metal-containing film portion and a metal film portion, wherein the metal-containing film portion comprises titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), titanium aluminum carbide (TiAlC), or a combination thereof, and the metal film portion comprises molybdenum (Mo), ruthenium (Ru), copper (Cu), tungsten (W), or a combination thereof.
Huang discloses in fig. 1B a gate line comprising a metal-containing film portion (126A) and a metal film portion (128A), wherein the metal-containing film portion comprises titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), titanium aluminum carbide (TiAlC), or a combination thereof [0029], and the metal film portion comprises molybdenum (Mo), ruthenium (Ru), copper (Cu), tungsten (W), or a combination thereof [0029].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a gate line comprising a metal containing film portion and a metal film portion as claimed for the purpose of controlling the threshold voltage as exemplified by Huang [0015].
Allowable Subject Matter
Claims 9-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record fails to teach the claimed limitations in combination namely, as recited in independent claim 9, an integrated circuit device comprising: a substrate comprising a first device region and a second device region; a fin-type active region on the substrate in the first device region, the fin-type active region extending in a first lateral direction; a first gate line extending in a second lateral direction on the fin-type active region and the substrate, the first gate line comprising a first width in the first lateral direction, wherein the first gate line is in the first device region, and the second lateral direction intersects with the first lateral direction; a first gate dielectric film covering a bottom surface of the first gate line and sidewalls of the first gate line, the first gate dielectric film extending in the second lateral direction; a gate contact plug comprising a conductive bottom surface in contact with a top contact portion of a top surface of the first gate line; a capping insulating pattern comprising an insulating bottom surface and an insulating sidewall, wherein the insulating bottom surface is in contact with a local top surface adjacent to the top contact portion of the top surface of the first gate line, and the insulating sidewall is in contact with the gate contact plug; a second gate line on an active region in the second device region, the second gate line comprising a second width in the first lateral direction, wherein the second gate line is in the second device region, and the second width is greater than the first width; and a second gate dielectric film between the second gate line and the active region, wherein, in the first device region, an insulating top surface of the capping insulating pattern and a conductive top surface of the gate contact plug extend along one plane, and wherein the conductive top surface of the gate contact plug in the first device region comprises a same material as a top surface of the second gate line in the second device region; and as recited in independent claim 18, an integrated circuit device comprising: a substrate comprising an N-type metal-oxide-semiconductor (NMOS) transistor region and a P-type metal-oxide-semiconductor (PMOS) transistor region; a fin-type active region extending in a first lateral direction in the NMOS transistor region or the PMOS transistor region; a nanosheet stack separate from a fin top surface of the fin-type active region in a vertical direction, wherein the nanosheet stack faces the fin top surface of the fin-type active region, and the nanosheet stack comprises at least one nanosheet; a pair of insulating spacers extending in a second lateral direction in a selected one of the NMOS transistor region and the PMOS transistor region corresponding to a location of the fin-type active region, the pair of insulating spacers defining a first space, wherein the second lateral direction intersects with the first lateral direction; a gate line surrounding the at least one nanosheet and extending in the second lateral direction in the first space; a gate dielectric film extending in the second lateral direction in the first space, the gate dielectric film comprising a portion in contact with a bottom surface and side surfaces of the gate line and each of the at least one nanosheet; a gate contact plug comprising a conductive bottom surface in contact with a top contact portion of the gate line in the first space; a capping insulating pattern comprising an insulating bottom surface, a pair of first insulating sidewalls, and a second insulating sidewall, wherein the insulating bottom surface is in contact with a local top surface adjacent to the top contact portion of the gate line in the first space, the pair of first insulating sidewalls are in contact with the pair of insulating spacers, and the second insulating sidewall is in contact with the gate contact plug, and wherein an insulating top surface of the capping insulating pattern and a conductive top surface of the gate contact plug extend along one plane.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yang et al. US 2023/0298945 teach an integrated circuit device including nanosheets and gate electrodes including inner and outer gate electrodes.
Jang et al. US 12,635,194 teach a semiconductor device including nanosheets and gate electrodes having different widths.
The examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. When responding to this office action, applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALLISON BERNSTEIN whose telephone number is (571)272-9011. The examiner can normally be reached M-F 8AM-5PM.
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/ALLISON BERNSTEIN/Primary Examiner, Art Unit 2824 6/18/2026
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