CTNF 18/664,060 CTNF 82855 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1-13, 17 and 18 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Lin et al. US 2023/0363182 . PNG media_image1.png 460 791 media_image1.png Greyscale Lin et al. US 2023/0363182 Regarding claim 1 , Lin et al. in Fig. 29 and [0398]-[0401] disclose a package comprising: a substrate 551 [0398]; a first integrated device 250(100) [0264] coupled to the substrate 551 through at least a first plurality of solder interconnects 563 [0400]; an underfill 564 [0400] or 92 [0390] located between the first integrated device 250 and the substrate 551; and a back side interconnect BISD 79 [0393] located over the underfill 564 and a back side of the first integrated device 250(100) [0264]. Regarding claim 2 , Lin et al. in Fig. 29 and [0398]-[0401] disclose the package of claim 1, wherein the back side interconnect BISD 79 [0393] is coupled to and touching a surface of the underfill 92 [0390] and a surface of the first integrated device 250(100) [0264]. Regarding claim 3 , Lin et al. in Fig. 29 and [0398]-[0401] disclose the package of claim 1, further comprising a back side dielectric layer 42 [0350] coupled to the underfill and 92 [0390] the first integrated device 250(100) [0264]. Regarding claim 4 , Lin et al. in Fig. 29 and [0398]-[0401] disclose the package of claim 3, wherein the back side interconnect BISD 79 [0393] is coupled to the back side dielectric layer 42 [0350]. Regarding claim 5 , Lin et al. in Fig. 29 and [0398]-[0401] disclose the package of claim 4, wherein a part of the back side dielectric layer 42 [0350] is located between the back side interconnect BISD 79 [0393] and the underfill 92 [0390]. Regarding claim 6 , Lin et al. in Fig. 29 and [0398]-[0401] disclose the package of claim 4, wherein a part of the back side dielectric layer 42 [0350] is located between the back side interconnect BISD 79 [0393] and the first integrated device 250(100) [0264]. Regarding claim 7 , Lin et al. in Fig. 29 and [0398]-[0401] disclose the package of claim 1, wherein the substrate 551 [0398] comprises: at least one dielectric layer 112 [0398]; and a plurality of interconnects 67 [0398], and wherein the back side interconnect BISD 79 [0393] is coupled to a first interconnect 67 [0398] and a second interconnect 67 [0398] from the plurality of interconnects 67 [0398] of the substrate 551 [0398]. Regarding claim 8 , Lin et al. in Fig. 29 and [0398]-[0401] disclose the package of claim 1, further comprising a second integrated device 200 or 400 [0400] coupled to the substrate 551 [0398] through at least a second plurality of solder interconnects 563 [0400], wherein the underfill 564 [0400] is located between the second integrated device 200 or 400 [0400] and the substrate 551 [0398]. Regarding claim 9 , Lin et al. in Fig. 29 and [0398]-[0401] disclose the package of claim 8, wherein the back side interconnect BISD 79 [0393] is further located over a back side of the second integrated device 200 or 400 [0400]. Regarding claim 10 , Lin et al. in Fig. 29 and [0398]-[0401] disclose the package of claim 9, wherein the underfill 564 [0400] or 92 [0390] is further located between the first integrated device 250(100) [0264] and the second integrated device 200 or 400 [0400]. Regarding claim 11 , Lin et al. in Fig. 29 and [0398]-[0401] disclose the package of claim 10, wherein the back side interconnect BISD 79 [0393] extends between a back side of the first integrated device 250(100) [0264] and a back side of the second integrated device 200 or 400 [0400]. Regarding claim 12 , Lin et al. in Fig. 29 and [0398]-[0401] disclose the package of claim 10, further comprising a back side dielectric layer 42 [0350] coupled to the underfill 564 [0400] or 92 [0390], a back side of the first integrated device 250(100) [0264] and a back side of the second integrated device 200 or 400 [0400]. Regarding claim 13 , Lin et al. in Fig. 29 and [0398]-[0401] disclose the package of claim 12, wherein a first part of the back side dielectric layer 42 [0350] is located between a first part of the back side interconnect BISD 79 [0393] and a back side of the first integrated device 250(100) [0264], and wherein a second part of the back side dielectric layer 42 [0350] is located between a second part of the back side interconnect BISD 79 [0393] and a back side of the second integrated device 200 or 400 [0400]. Regarding claim 15 , Lin et al. in Fig. 29 and [0398]-[0401] disclose the package of claim 12, wherein the back side dielectric layer 42 [0350] is coupled to the substrate 551 [0398] (i.e. 79 through 158 [0390]). Regarding claim 17 , Lin et al. in Fig. 29 and [0398]-[0401] disclose the package of claim 8, wherein the first integrated device 250(100) [0264] is coupled to the substrate 551 [0398] through a first plurality of pillar interconnects 34 [0350] and the first plurality of solder interconnects 563 [0400], and wherein the second integrated device is coupled to the substrate 551 [0398] through a second plurality of pillar interconnects 34 [0350] and the second plurality of solder interconnects 563 [0400]. Regarding claim 18 , Lin et al. in Fig. 29 and [0398]-[0401] disclose the package of claim 1, wherein the back side interconnect BISD 79 [0390] includes copper (Cu) 40 [0354]-or silver (Ag) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 16, 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. US 2023/0363182 . Regarding claim 16 , Lin et al. in Fig. 29 and [0398]-[0401] disclose the package of claim 12, wherein the back side dielectric layer 42 [0350] includes a polymer layer, or insulating dielectric layer, but do not expressly disclose silicon oxide. Although Lin et al. do not expressly disclose silicon oxide for the back side dielectric layer, the material differences are considered obvious design choices and are not patentable unless obvious or unexpected results are obtained from these changes. It appears that these changes produce no functional differences and therefore would have been obvious before the effective filing date of the invention. See, for example, MPEP § 2144.07. Regarding claim 19 , Lin et al. in Fig. 29 and [0398]-[0401] disclose the package of claim 1, but do not expressly disclose wherein the back side interconnect includes an inkjet printed interconnect. Inkjet printed interconnect is considered a process by which the product was formed and even though product by process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985) See, for example, MPEP § 2113.I. Regarding claim 20 , Lin et al. in Fig. 29 and [0398]-[0401] disclose the package of claim 1, but do not expressly disclose wherein the back side interconnect includes plated interconnects. Plated interconnects is considered a process by which the product was formed and even though product by process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985) See, for example, MPEP § 2113.I . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim 14 is objected to as being dependent upon a rejected base claim , but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: Claim 14 is allowed over the prior art because the prior art of record neither anticipates nor renders obvious, in the context of the claims, the positions of the first part and second part of the back side dielectric layer in reference to the back side interconnect and the integrated devices including wherein a third part of the back side dielectric layer is located between a third part of the back side interconnect and a surface of the underfill. Although various prior art references disclose several individual limitations in the claims, these references, and their combinations, neither anticipate nor render obvious the above identified limitation(s), as structured and interrelated in the context of the claims. For example, Shen et al. US 9,899,281; Kim US 11,699,642 ; Kim et al., DE10218111445 ; Chiang et al. US 2020/0006274 . Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SONYA D MCCALL-SHEPARD whose telephone number is (571)272-9801. The examiner can normally be reached M-F: 8:30 AM-5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Sonya McCall-Shepard/Primary Examiner, Art Unit 2898 Application/Control Number: 18/664,060 Page 2 Art Unit: 2898 Application/Control Number: 18/664,060 Page 3 Art Unit: 2898 Application/Control Number: 18/664,060 Page 4 Art Unit: 2898
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