DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
1. Applicant’s election without traverse of group II in the reply filed on 7/16/26 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim 13 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Application Publication No. 2019/0067455 Cho et al.
2. Referring to claim 13, Cho et al. teaches a semiconductor device comprising: a substrate, (Figure 20 #110); a gate structure, (Figure 20 #122), disposed on the substrate, (Figure 20 #110); a spacer, (Figure 20 #130), disposed on a sidewall of the gate structure, (Figure 20 #122); a nitride layer, (Figure 20 #152), covering the spacer, (Figure 20 #130), and the substrate, (Figure 20 #110); a carbonitride layer, (Figure 20 #156 and Paragraph 0044), covering and contacting the nitride layer, (Figure 20 #152 and Paragraph 0041); a protective layer, (Figure 20 #126), covering and contacting a top surface of the gate structure, (Figure 20 #122); an interlayer dielectric layer, (Figure 20 #158), disposed on, (the limitation disposed on is read in its broadest reasonable manner and not limited to disposed directly on), the protective layer, (Figure 20 #126), and the carbonitride layer, (Figure 20 #156); and a contact plug, (Figure 20 #162), disposed in the interlayer dielectric layer, (Figure 20 #158), the carbonitride layer, (Figure 20 #156), and the nitride layer, (Figure 20 #152).
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
3. Claims 14-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
4. The prior art teaches the claimed matter in the rejections above, but is silent with respect to the above teachings in combination with the semiconductor device of claim 13, wherein a material of the carbonitride layer is same as a material of the protective layer; the semiconductor device of claim 13, wherein the protective layer covers and contacts a top surface of the spacer; the semiconductor device of claim13, further comprising: a S/D region in the substrate; and a metal silicide layer on the S/D region, wherein a portion of the metal silicide layer is protruded from a surface of the substrate; the semiconductor device of claim 13, wherein the top surface of the gate structure and a top surface of the nitride layer and the carbonitride layer on the sidewall of the gate structure are coplanar; and/or the semiconductor device of claim 13, wherein a thickness of the carbonitride layer is thinner than a thickness of the nitride layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR A MANDALA whose telephone number is (571)272-1918. The examiner can normally be reached on M-Th 8-6:30 EST.
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/VICTOR A MANDALA/Primary Examiner, Art Unit 2899 8/4/26
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