DETAILED ACTION
1. It is hereby acknowledged that 18/664340 following papers have been received and placed of record in the file: Remark date 05/15/24
2. The present application, file on or after March 16, 2013, is being examiner under the first inventor to file provisions of the AIA .
3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Objections
4. Claims 1-20 are objected to because of the following informalities:
Claim 1 and 16 discloses… time-synchronization..,… clock synchronization…, … two-way time synchronization protocol…, These synchronizations has one of ordinary skill in the art guessing if there differences between them based on the way they are spelled out.
Further the claims disclose … two-way time synchronization protocol…. Is unclear since it is explained the two-way time synchronization protocol is Precision Time Protocol (PTP). (see specification paragraph [0020] claims 15 and 20). Is what is meant, in PTP the use of two-way time synchronization protocol or something else?
Claims 16 discloses , …. accelerator generation … it is unclear what is meant by this.
The specification does not seem to provide further clarification (See paragraph [0021]).
Claim Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained through the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
6. Claims 1-20 are rejected under 35 U.S.C. §103 as being unpatentable over AWEYA (US 2015/0092796) in view of LIU (CN203596827U) in further view of Sindhu et al(US 20190012278A1)
Regarding claim 1, Aweya teaches a system, comprising:
a hardware clock to maintain a clock time; (see Aweya Fig 1-3, paragraphs [0010], [0015] explains… The timing system includes a time server having a server clock for generating current timestamp information, and a time client having a client clock, the time client having a time estimation mechanism)
and a network device including:
to receive a first time-synchronization message from a clock synchronization leader as part of a two-way time synchronization protocol; (see Fig. 1-3 Aweya paragraph [0039] [0042],[0043] explains…. The following discussion describes a two-way time transfer protocol for the exchange of timestamp information between a time server 14 and a time client 16. This protocol forms a basis for the Network Time Protocol (NTP) and IEEE 1588 Precision Time Protocol (PTP). The underlying assumption of this protocol is that both forward and reverse paths of the client-server communication are symmetric in fixed communication delay..)
to: identify the first time-synchronization message; (see Fig. 1-3 Aweya paragraph [0039] [0042],[0043] explains…. The following discussion describes a two-way time transfer protocol for the exchange of timestamp information between a time server 14 and a time client 16. This protocol forms a basis for the Network Time Protocol (NTP) and IEEE 1588 Precision Time Protocol (PTP). The underlying assumption of this protocol is that both forward and reverse paths)
sending of a second time-synchronization message to the clock synchronization leader in response to identifying the first time synchronization message; (see Fig. 1-3 Aweya paragraphs [0038] explains sending response message [0039], [0043] explains…. The following discussion describes a two-way time transfer protocol for the exchange of timestamp information between a time server 14 and a time client 16. This protocol forms a basis for the Network Time Protocol (NTP) and IEEE 1588 Precision Time Protocol (PTP). The underlying assumption of this protocol is that both forward and reverse paths)
and provide timing information associated with the first time-synchronization message and the second time-synchronization message. (see Fig. 1-3 Aweya paragraph [0039] [0042],[0043] explains…. The following discussion describes a two-way time transfer protocol for the exchange of timestamp information between a time server 14 and a time client 16. This protocol forms a basis for the Network Time Protocol (NTP) and IEEE 1588 Precision Time Protocol (PTP). The underlying assumption of this protocol is that both forward and reverse paths)
While it can be understood Aweya explains this limitation, however to further clarify to time-synchronization software running on a host device to synchronize the hardware clock to the clock synchronization leader,
Analagous art LIU paragraph [0016] explains ….field device A sends a PTP packet to the field device B, and records the time, the timestamp of the data packet leaves the A is tl; (2) when the PTP packet reaches the field device B, a field device B and receives the timestamp of the data packet, the timestamp is ', (3) field device A sends a Follow Up message to the field apparatus B, the B time, (4) when the PTP packet leaves the field device B; and recording the data packet leaves B time is t2, (5) when the field device A receives the response packet, adding a new timestamp….see paragraph [0021] explains… the main clock communication device embedded GPS receiving device receives the main clock for the synchronization, the main communication device and embedded with clock synchronization protocol timestamp of device from the communication device, the main communication device and clock synchronization software device running on the communication device…)
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to combine Aweya with LIU. One of ordinary skill in the art would have been motivated to make this modification before the effective filling data of the claimed invention to improving time standards in a system as well as cost reduction,(See paragraph [0002],[0023])
Further Sindhu teaches a network interface and a hardware accelerator and cause generation (See paragraph [0025]…. The DPU may support one or more high-speed network interfaces, such as Ethernet ports, ….[0041], [0088] explains…. Hardware primitives may further accelerate work unit generation and delivery. DPU 150 may also provide low synchronization, in that the components thereof may operate according to a stream-processing model that encourages flow-through operation with low synchronization and inter-processor communication…)
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to combine the modified Aweya with Sindhu. One of ordinary skill in the art would have been motivated to make this modification before the effective filling data of the claimed invention to reduce processing load in a system (See paragraph [0007])
Regarding claim 2, the modified Aweya taught the system according to claim 1, as described above. The modified Aweya further teaches comprising a host device to execute the time-synchronization software to: receive the timing information; and synchronize the hardware clock to the clock synchronization leader based on the timing information.(see Aweya paragraphs Fig.1 [0038], [0039], [0042], see LIU paragraph [0021] explains… the main clock communication device embedded GPS receiving device receives the main clock for the synchronization, the main communication device and embedded with clock synchronization protocol timestamp of device from the communication device, the main communication device and clock synchronization software device running on the communication device…)
Regarding claim 3, the modified Aweya taught the system according to claim 2, , as described above. The modified Aweya further teaches wherein the timing information is indicative of a transmission and receive time of the first time-synchronization message and a transmission and receive time of the second time-synchronization message. (see Aweya paragraphs [0039], [0042], see LIU paragraph [0021] explains… the main clock communication device embedded GPS receiving device receives the main clock for the synchronization, the main communication device and embedded with clock synchronization protocol timestamp of device from the communication device, the main communication device and clock synchronization software device running on the communication device…)
Regarding claim 4, the modified Aweya taught the system according to claim 2, as described above. The modified Aweya further teaches wherein the time-synchronization software is to receive the timing information in response to any one or more of the following: receiving an interrupt from the network device; polling the network device; a completion queue entry; and detecting writing of the timing information in at least one memory location. . (see Aweya paragraphs [0039], [0042],[0170] see LIU paragraph [0021] explains… the main clock communication device embedded GPS receiving device receives the main clock for the synchronization, the main communication device and embedded with clock synchronization protocol timestamp of device from the communication device, the main communication device and clock synchronization software device running on the communication device…)
Regarding claim 5, the modified Aweya taught the system according to claim 1, as described above. The modified Aweya further teaches wherein the network device includes a data processing unit (DPU) including one or more microprocessors, the DPU is to act as the host device to execute the time-synchronization software to: receive the timing information; and synchronize the hardware clock to the clock synchronization leader based on the timing information.( see Aweya paragraphs [0039], [0042],[0170] see LIU paragraph [0021] explains… the main clock communication device embedded GPS receiving device receives the main clock for the synchronization, the main communication device and embedded with clock synchronization protocol timestamp of device from the communication device, the main communication device and clock synchronization software device running on the communication device…see Sindhu paragraph [0068] explains… Each of host units 146 may support one or more host interfaces, e.g., PCI-e ports, for connectivity to an application processor (e.g., an x86 processor of a server device or a local CPU or GPU of the device hosting DPU 130) or a storage device (e.g., an SSD). DPU 130 may also include one or more high bandwidth interfaces for connectivity to off-chip external memory (not illustrated in FIG. 2). Each of accelerators 148 may be configured to perform acceleration for various data-processing functions, such as look-ups, matrix multiplication, cryptography, compression, regular expressions, or the like.)
Regarding claim 6, the modified Aweya taught the system according to claim 1, as described above. The modified Aweya further teaches wherein the hardware accelerator includes packet processing circuitry to: identify the first time-synchronization message; cause generation and sending of the second time-synchronization message to the clock synchronization leader in response to identifying the first time-synchronization message; and provide timing information associated with the first time-synchronization message and the second time-synchronization message to the time-synchronization software running on the host device to synchronize the hardware clock to the clock synchronization leader. (see Aweya Fig.1-3 paragraphs [0039], [0042],[0170] see LIU paragraph [0016], [0021] explains… the main clock communication device embedded GPS receiving device receives the main clock for the synchronization, the main communication device and embedded with clock synchronization protocol timestamp of device from the communication device, the main communication device and clock synchronization software device running on the communication device…)
Regarding claim 7, the modified Aweya taught the system according to claim 6, as described above. The modified Aweya further teaches wherein the packet processing circuitry includes steering circuitry to identify the first time-synchronization message and cause generation and sending of the second time-synchronization message based on matching data from the first time-synchronization message with match-and-action tables. (see Aweya paragraphs [0038], 0039], [0042],[0170] see LIU paragraph [0021] explains… the main clock communication device embedded GPS receiving device receives the main clock for the synchronization, the main communication device and embedded with clock synchronization protocol timestamp of device from the communication device, the main communication device and clock synchronization software device running on the communication device…)
Regarding claim 8, the modified Aweya taught the system according to claim 7, as described above. The modified Aweya further teaches wherein the steering circuitry is to generate the second time-synchronization packet. (see Aweya paragraphs [0038], 0039], [0042],[0170] see LIU paragraph [0021] explains… the main clock communication device embedded GPS receiving device receives the main clock for the synchronization, the main communication device and embedded with clock synchronization protocol timestamp of device from the communication device, the main communication device and clock synchronization software device running on the communication device…)
Regarding claim 9, the modified Aweya taught the system according to claim 7, as described above. The modified Aweya further teaches wherein the network device includes a data processing unit (DPU) including one or more microprocessors, the DPU is to generate the second time-synchronization packet. (see Aweya paragraphs [0038], 0039], [0042],[0170] see LIU paragraph [0021] explains… the main clock communication device embedded GPS receiving device receives the main clock for the synchronization, the main communication device and embedded with clock synchronization protocol timestamp of device from the communication device, the main communication device and clock synchronization software device running on the communication device…)
Regarding claim 10, the modified Aweya taught the system according to claim 6, as described above. The modified Aweya further teaches wherein the packet processing circuitry is to: sample a receive time of the first time-synchronization message and a transmission time of the second time-synchronization message; and provide the sampled receive time and the sampled transmission time or a difference between the sampled transmission time and the sampled received time or another time value based on the sampled receive time and the sampled transmission time to the time-synchronization software running on the host device. (see Aweya paragraphs[0006] explains time stamps [0038], [0039], [0042],[0170] see LIU paragraph [0021] explains… the main clock communication device embedded GPS receiving device receives the main clock for the synchronization, the main communication device and embedded with clock synchronization protocol timestamp of device from the communication device, the main communication device and clock synchronization software device running on the communication device…)
Regarding claim 11, the modified Aweya taught the system according to claim 10, as described above. The modified Aweya further teaches wherein: the network interface is to receive a third time-synchronization message including the transmission time of the first time-synchronization message; and the network interface is to receive a fourth time-synchronization message including the receive time of the second time-synchronization message. (see Aweya paragraphs[0006] explains time stamps [0038], [0039], [0042],[0170] see LIU paragraph [0021] explains… the main clock communication device embedded GPS receiving device receives the main clock for the synchronization, the main communication device and embedded with clock synchronization protocol timestamp of device from the communication device, the main communication device and clock synchronization software device running on the communication device…)
Regarding claim 12, the modified Aweya taught the system according to claim 11, as described above. The modified Aweya further teaches wherein the packet processing circuitry is to: extract the transmission time of the first time-synchronization message and the receive time of the second time-synchronization message from the third time synchronization message and the fourth time-synchronization message, respectively; and provide the extracted transmission time and the extracted receive time or a difference between the extracted transmission time and the extracted receive time or another time value based on the extracted transmission time and the extracted receive time to the time-synchronization software running on the host device. (see Aweya paragraphs[0006] explains time stamps [0038], [0039], [0042],[0170] see LIU paragraph [0021] explains… the main clock communication device embedded GPS receiving device receives the main clock for the synchronization, the main communication device and embedded with clock synchronization protocol timestamp of device from the communication device, the main communication device and clock synchronization software device running on the communication device…)
Regarding claim 13, the modified Aweya taught the system according to claim 11, as described above. The modified Aweya further teaches wherein the packet processing circuitry is configured to provide the third time-synchronization message and the fourth time-synchronization message to the time-synchronization software running on the host device to synchronize the hardware clock to the clock synchronization leader based on the transmission time of the first time-synchronization message and the receive time of the second time-synchronization message included in the third time synchronization message and the fourth time-synchronization message, respectively. (see Aweya paragraphs[0006] explains time stamps [0038], [0039], [0042],[0170] see LIU paragraph [0021] explains… the main clock communication device embedded GPS receiving device receives the main clock for the synchronization, the main communication device and embedded with clock synchronization protocol timestamp of device from the communication device, the main communication device and clock synchronization software device running on the communication device…)
Regarding claim 14, the modified Aweya taught the system according to claim 1, as described above. The modified Aweya further teaches wherein a difference between: (a) a receive time of the first time-synchronization message; and (b) a transmission time of the second time-synchronization message, is a predefined fixed time-difference predefined by a configuration of the hardware accelerator. (see Aweya Fig.1-3 paragraphs [0039], [0042],[0170] see LIU paragraph [0016], [0021] explains… the main clock communication device embedded GPS receiving device receives the main clock for the synchronization, the main communication device and embedded with clock synchronization protocol timestamp of device from the communication device, the main communication device and clock synchronization software device running on the communication device…)
Regarding claim 15, the modified Aweya taught the system according to claim 1, as described above. The modified Aweya further teaches wherein: the two-way time synchronization protocol is Precision Time Protocol (PTP); the first-time synchronization message is a sync message; and the second-time synchronization message is a delay request message. (see Aweya Fig.1-3 paragraphs [0039], [0042],[0170] see LIU paragraph [0016], [0021] explains… the main clock communication device embedded GPS receiving device receives the main clock for the synchronization, the main communication device and embedded with clock synchronization protocol timestamp of device from the communication device, the main communication device and clock synchronization software device running on the communication device…)
Regarding claim 16. A method, comprising: maintaining a clock time; (see Aweya Fig 1-3, paragraph [0015] explains… The timing system includes a time server having a server clock for generating current timestamp information, and a time client having a client clock, the time client having a time estimation mechanism )receiving a first time-synchronization message from a clock synchronization leader as part of a two-way time synchronization protocol; (see Fig. 1-3 Aweya paragraph [0039] [0042],[0043] explains…. The following discussion describes a two-way time transfer protocol for the exchange of timestamp information between a time server 14 and a time client 16. This protocol forms a basis for the Network Time Protocol (NTP) and IEEE 1588 Precision Time Protocol (PTP). The underlying assumption of this protocol is that both forward and reverse paths of the client-server communication are symmetric in fixed communication delay..)
identifying by a hardware accelerator the first time-synchronization message; (see Fig. 1-3 Aweya paragraph [0039] [0042],[0043] explains…. The following discussion describes a two-way time transfer protocol for the exchange of timestamp information between a time server 14 and a time client 16. This protocol forms a basis for the Network Time Protocol (NTP) and IEEE 1588 Precision Time Protocol (PTP). The underlying assumption of this protocol is that both forward and reverse paths)
causing by the hardware accelerator generation and sending of a second time-synchronization message to the clock synchronization leader in response to identifying the first time-synchronization message; (see Fig. 1-3 Aweya paragraphs[0038], [0039] [0042],[0043] explains…. The following discussion describes a two-way time transfer protocol for the exchange of timestamp information between a time server 14 and a time client 16. This protocol forms a basis for the Network Time Protocol (NTP) and IEEE 1588 Precision Time Protocol (PTP). The underlying assumption of this protocol is that both forward and reverse paths)
and providing by the hardware accelerator timing information associated with the first time-synchronization message and the second time-synchronization message . (see Fig. 1-3 Aweya paragraph [0039] [0042],[0043] explains…. The following discussion describes a two-way time transfer protocol for the exchange of timestamp information between a time server 14 and a time client 16. This protocol forms a basis for the Network Time Protocol (NTP) and IEEE 1588 Precision Time Protocol (PTP). The underlying assumption of this protocol is that both forward and reverse paths)
While it can be understood Aweya explains this, however to further clarify LIU discloses time-synchronization software running on a host device to synchronize the hardware clock to the clock synchronization leader (see paragraph [0016] explains ….field device A sends a PTP packet to the field device B, and records the time, the timestamp of the data packet leaves the A is tl; (2) when the PTP packet reaches the field device B, a field device B and receives the timestamp of the data packet, the timestamp is ', (3) field device A sends a Follow Up message to the field apparatus B, the B time, (4) when the PTP packet leaves the field device B; and recording the data packet leaves B time is t2, (5) when the field device A receives the response packet, adding a new timestamp,…) to time-synchronization software running on a host device to synchronize the hardware clock to the clock synchronization leader.(see paragraph [0021] explains clock synchronization device running on the communication)
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to combine Aweya with LIU. One of ordinary skill in the art would have been motivated to make this modification before the effective filling data of the claimed invention to improving time standards in a system as well as cost reduction,,(See paragraph [0002],[0023])
Further Sindhu teaches hardware accelerator and cause generation (See paragraph [0025]…. The DPU may support one or more high-speed network interfaces, such as Ethernet ports, ….[0041], [0088] explains…. Hardware primitives may further accelerate work unit generation and delivery. DPU 150 may also provide low synchronization, in that the components thereof may operate according to a stream-processing model that encourages flow-through operation with low synchronization and inter-processor communication…)
It would have been obvious to one of ordinary skill in the art before the effective filling data of the claimed invention to combine the modified Aweya with Sindhu. One of ordinary skill in the art would have been motivated to make this modification before the effective filling data of the claimed invention to reduce processing load in a system(See paragraph [0007])
Regarding claim 17, the modified Aweya taught the method according to claim 16, as described above. The modified Aweya further teaches further comprising: receiving by the software the timing information; and synchronizing by the software the hardware clock to the clock synchronization leader based on the timing information. (see Aweya paragraphs Fig.1 [0038], [0039], [0042], see LIU paragraph [0021] explains… the main clock communication device embedded GPS receiving device receives the main clock for the synchronization, the main communication device and embedded with clock synchronization protocol timestamp of device from the communication device, the main communication device and clock synchronization software device running on the communication device…)
Regarding claim 18, the modified Aweya taught the method according to claim 17, as described above. The modified Aweya further teaches wherein the timing information is indicative of a transmission and receive time of the first time-synchronization message and a transmission and receive time of the second time-synchronization message. (see Aweya paragraphs Fig.1 [0038], [0039], [0042], see LIU paragraph [0021] explains… the main clock communication device embedded GPS receiving device receives the main clock for the synchronization, the main communication device and embedded with clock synchronization protocol timestamp of device from the communication device, the main communication device and clock synchronization software device running on the communication device…)
Regarding claim 19, the modified Aweya taught the method according to claim 16, as described above. The modified Aweya further teaches wherein a difference between: (a) a receive time of the first time-synchronization message; and (b) a transmission time of the second time-synchronization message, is a predefined fixed time-difference predefined by a configuration of the hardware accelerator. (see Aweya Fig.1-3 paragraphs [0039], [0042],[0170] see LIU paragraph [0016], [0021] explains… the main clock communication device embedded GPS receiving device receives the main clock for the synchronization, the main communication device and embedded with clock synchronization protocol timestamp of device from the communication device, the main communication device and clock synchronization software device running on the communication device…)
Regarding claim 20, the modified Aweya taught the method according to claim 16, as described above. The modified Aweya further teaches wherein: the two-way time synchronization protocol is Precision Time Protocol (PTP); the first-time synchronization message is a sync message; and the second-time synchronization message is a delay request message. (see Aweya Fig.1-3 paragraphs [0039], [0042],[0170] see LIU paragraph [0016], [0021] explains… the main clock communication device embedded GPS receiving device receives the main clock for the synchronization, the main communication device and embedded with clock synchronization protocol timestamp of device from the communication device, the main communication device and clock synchronization software device running on the communication device…)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Gerald Smarth whose telephone number is (571) 270-1923. The examiner can normally be reached on Monday-Thursday 6am-4:30pm ET. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joseph Avellino can be reached on 571-272-7784. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/GERALD A SMARTH/Primary Examiner, Art Unit 2478
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