DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDSes) were submitted on 05/31/2026 and 07/12/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Response to Arguments
Applicant’s Amendments and Arguments filed 06/22/2026 have been considered for examination.
With regard to the objections to Specification and Claims, Applicant’s arguments filed 06/22/2026 in view of the amendments have been fully considered and are persuasive. Thus, the objections to Specification and Claims have been withdrawn.
With regard to the double patenting rejections, Applicant’s arguments filed 06/22/2026 in view of the amendments have been fully considered but are moot because the arguments are not applied to any of the references being used in the current rejection.
With regard to the 102/103 rejections, Applicant’s arguments filed 06/22/2026 in view of the amendments have been fully considered but are moot because the arguments are not applied to any of the references being used in the current rejection.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1 and 13 are provisionally rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims of copending Application No. 18/631,095 (hereinafter, “Manevich”) in view of Tzeng et al (US Publication No 2023/0246723 A1). This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
It is noted that the applicant filing of the copending Application No. 18/631,095 is voluntary and not the direct, unmodified result of restriction requirement under U.S.C. 121 (i.e., without a restriction requirement by the examiner) and the claims of the second application are drawn to the “same invention” as the first application or patent.
Regarding claim 1, Manevich discloses, a network device [see claim 1, line 1, network device], comprising:
a network interface to share time synchronization packets with at least one remote device over a network [see claim 1, lines 8-10, a network interface to transmit the time synchronization messages to at least one clock synchronization follower according to the schedule data and the clock time];
a hardware clock to maintain a clock time [see claim 1, line 4, hardware clock to maintain a clock time]; and
packet processing circuitry to process the time synchronization packets according to a two-way time synchronization protocol [see claim 3, precision time protocol (PTP) is a two-way time synchronization protocol] in order to cause clock synchronization between the hardware clock and at least one clock of the at least one remote device [see claim 1, lines 5-7, scheduler circuitry to manage periodic transmission of the time synchronization messages according to the clock time and schedule data provided by the software].
Manevich does not explicitly disclose (see, italicized and bold limitations), the packet processing circuitry includes steering circuitry to identify received ones of the time synchronization packets using match and-action tables and to cause generation of response time synchronization packets based on actions defined in the match-and-action tables.
However, Tzeng discloses, steering circuit to identify received ones of the time synchronization packets using match and-action tables [abstract; ¶0068-0069, the processor 470 detects a type of packet, and determines a table of one or more actions according to the determined type of packet as well as the role and/or the operating mode of the device 400. In one approach, the communication interface determines 540 an action corresponding to a portion of the packet. For example, the communication interface obtains one or more bits in a predetermined field (e.g., reserved field 326). The communication interface may apply the obtained one or more bits to a corresponding table (e.g., table 480 or 490), and determine or identify one or more actions corresponding to the one or more bits] and to cause generation of response time synchronization packets based on actions defined in the match-and-action tables [abstract; ¶0070, the communication interface performs 550 the determined action. For example, the communication interface may add a timestamp value to a packet, or store a timestamp value by the memory 450, according to the table (e.g., table 480 or 490)].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the above-mentioned feature(s) as taught by Tzeng in the system of Manevich in order to cause the system to able to allow various efficient actions to perform or support time synchronization among different nodes according to PTP message types [e.g., ¶0071 of Tzeng].
Regarding claim 13, claim 13 recites similar features to claim 1 without additional features.
Thus, claim 13 is rejected at least based on a similar rationale applied to claim 1.
Claims 2-3, 10-11, 14-15 and 22-23 are provisionally rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims of copending Application No. 18/631,095 (hereinafter, “Manevich”) in view of Tzeng et al (US Publication No 2023/0246723 A1) and further in view of Aweya et al (US Publication No. 2013/0282875 A1).
Regarding claim 2, Manevich in view of Tzeng discloses, the device according to claim 1 as set forth above.
Manevich in view of Tzeng does not explicitly disclose (see, italicized limitations), but Aweya discloses, wherein the packet processing circuitry is to process the time synchronization packets as a time synchronization leader to synchronize the at least one clock of the at least one remote device to the hardware clock [FIGS. 1-3; their related descriptions; ¶0042-0044; abstract; claim 1, note that the time server acts a time synchronization leader].
It is noted that the above-mentioned feature is a known technique in the field Applicant's endeavor, e.g., telecommunication art.
It would have been obvious to one having ordinary skill in the art before the effective filing date to combine the system of Manevich in view of Tzeng with "the above-mentioned known feature(s)" taught by Aweya to reach the claimed invention as set forth above. Since one having ordinary skill in the art could have recognized that applying the known technique taught by Aweya into the system of Manevich in view of Tzeng would have yield predictable results and/or resulted in the improved system, such as e.g., improving time-synchronization precision between two network devices by allowing exchanges of timestamp information, such a modification (or application) would have involved the mere application of a known technique to a piece of prior art ready for improvement," the claim is unpatentable under 35 U.S.C. 103(a). Ex Parte Smith, 83 USPQ.2d 1509, 1518-19 (BPAI, 2007) (citing KSR v. Teleflex, 127 S.Ct. 1727, 1740, 82 USPQ2d 1385, 1396 (2007)).
Regarding claim 3, Manevich in view of Tzeng and Aweya discloses, the device according to claim 2 as set forth above.
Manevich further discloses, wherein the packet processing circuitry is to participate in multiple concurrent time synchronization processes with multiple time synchronization clients [see claim 8, lines 2-3].
Regarding claim 10, Manevich discloses, the device according to claim 1 as set forth above.
Manevich in view of Tzeng does not explicitly disclose (see, italicized limitations), but Aweya discloses,
the interface is to receive a first time-synchronization packet from a given remote device [FIG. 3; its related descriptions; ¶0042, the time client 16 initially sends a request message 20 to the time server 14 (note that the time server requires at least one network interface to receive the request message 20) that contains the timestamp T1 that the message is sent; see abstract; claims 1-3, “sending time transfer protocol messages from the time client to the time server over a packet network”];
the packet processing circuitry includes a parser to parse the first time-synchronization packet yielding parsed data [FIG. 3; its related descriptions; ¶0042, the server 14 notes the time T2 it receives this message and, at a later time, sends a response message 22 back to the client 16 containing the time T1 (note that it requires at least one parser to parse the request message 20 to obtain the timestamp T1) the client sent the first message/the request message 20, the time T2 the server received that message, and the time T3 that the server sends the current message 22];
the packet processing circuitry includes steering circuitry to cause generation of a second time-synchronization packet based on the parsed data and the first time-synchronization packet [FIG. 3; its related descriptions; ¶0042, the server 14 notes the time T2 it receives this message and, at a later time, sends a response message 22 (i.e., second time synchronization packet) back to the client 16 containing the time T1 the client sent the first message (i.e., based on the parsed data/timestamp T1 and the request message 20), the time T2 the server received that message, and the time T3 that the server sends the current message 22; see also claim 1, “receiving time transfer protocol messages from the time server”]; and
the interface is to send the second time-synchronization packet to the given remote device [FIG. 3; its related descriptions; ¶0042, the server 14 notes the time T2 it receives this message and, at a later time, sends a response message 22 (i.e., second time synchronization packet) back to the client 16; see also claim 1, “receiving time transfer protocol messages from the time server”].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the above-mentioned feature(s) as taught by Aweya in the system of Manevich in view of Tzeng for similar rationales set forth above in claim 2.
Regarding claim 11, Manevich in view of Tzeng and Aweya discloses, the device according to claim 10 as set forth above.
Manevich in view of Tzeng does not explicitly disclose (see, italicized limitations), but Aweya discloses,
the packet processing circuitry includes timestamping circuitry to sample a receive time of the first time-synchronization packet according to the clock time of the hardware clock [FIG. 3; its related descriptions; ¶0042, see, the server 14 notes the time T2 it receives this message and, at a later time, sends a response message 22 back to the client 16 containing the time T1 the client sent the first message the time T2 the server received (i.e., sample a receive time of the first time-synchronization) packet that message]; and
the steering circuitry is to insert the receive time into the second time-synchronization packet [FIG. 3; its related descriptions; ¶0042, the server 14 notes the time T2 it receives this message and, at a later time, sends a response message 22 (i.e., second time-synchronization packet) back to the client 16 containing the time T1 the client sent the first message, the time T2 the server received (i.e., insert the receive time into the second time-synchronization packet) that message, and the time T3 that the server sends the current message 22].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the above-mentioned feature(s) as taught by Aweya in the system of Manevich in view of Tzeng for similar rationales set forth above in claim 2.
Regarding claim 14, claim 14 is rejected at least based on a similar rationale applied to claim 2.
Regarding claim 15, claim 15 is rejected at least based on a similar rationale applied to claim 3.
Regarding claim 22, claim 22 is rejected at least based on a similar rationale applied to claim 10.
Regarding claim 23, claim 23 is rejected at least based on a similar rationale applied to claim 11.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 10-11, 13-15 and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Aweya et al (US Publication No. 2013/0282875 A1) in view of Tzeng et al (US Publication No 2023/0246723 A1).
Regarding claim 1, Aweya discloses, a network device [FIGS. 1-3; their related descriptions; abstract; claim 1, time server 14], comprising:
a network interface to share time synchronization packets with at least one remote device over a network [FIGS. 1-3; their related descriptions; ¶0042-0044; abstract; claim 1, time server (i.e., network device) exchanges of time transfer protocol messages with time client (i.e., remote device) over a network; see claim 1, sending time transfer protocol messages from the time client to the time server and receiving time transfer protocol messages from the time server; further see FIG. 3, client request message 20 and server response message exchanged between the time server and the time client; note that performing exchanges of the messages requires the time server to have a network interface];
a hardware clock to maintain a clock time [FIGS. 1-3; their related descriptions; ¶0015; abstract; claim 1, server clock for generating current timestamp information; which requires maintaining a clock time of the server clock]; and
packet processing circuitry [FIGS. 1-3; their related descriptions; abstract; claim 1, note that exchanging of the time transfer protocol messages requires the time server to have a processing unit to process the exchanging, which is considered as a packet processor] to process the time synchronization packets according to a two-way time synchronization protocol [see ¶0039, two-way time transfer protocol] in order to cause clock synchronization between the hardware clock and at least one clock of the at least one remote device [FIGS. 1-3; their related descriptions; abstract; claim 1, the time server exchanging the time transfer protocol messages with the time client to cause clock synchronization between the server clock and the client clock of the time client; see claim 1, “time synchronization over a packet network between a time server having a server clock and a time client having a client clock”; further see FIG. 3, client request message 20 and server response messages].
Although Aweya discloses, wherein the packet processing circuitry includes steering circuitry [FIG. 3; its related descriptions; ¶0042, the server 14 notes the time T2 it receives this message and, at a later time, sends a response message 22 (i.e., second time synchronization packet) back to the client 16 containing the time T1 the client sent the first message (i.e., based on the parsed data/timestamp T1 and the request message 20), the time T2 the server received that message, and the time T3 that the server sends the current message 22; see also claim 1, “receiving time transfer protocol messages from the time server”], Aweya does not explicitly disclose (see, italicized and bold limitations), the packet processing circuitry includes steering circuitry to identify received ones of the time synchronization packets using match and-action tables and to cause generation of response time synchronization packets based on actions defined in the match-and-action tables.
However, Tzeng discloses, identify received ones of the time synchronization packets using match and-action tables [abstract; ¶0068-0069, the processor 470 detects a type of packet, and determines a table of one or more actions according to the determined type of packet as well as the role and/or the operating mode of the device 400. In one approach, the communication interface determines 540 an action corresponding to a portion of the packet. For example, the communication interface obtains one or more bits in a predetermined field (e.g., reserved field 326). The communication interface may apply the obtained one or more bits to a corresponding table (e.g., table 480 or 490), and determine or identify one or more actions corresponding to the one or more bits] and to cause generation of response time synchronization packets based on actions defined in the match-and-action tables [abstract; ¶0070, the communication interface performs 550 the determined action. For example, the communication interface may add a timestamp value to a packet, or store a timestamp value by the memory 450, according to the table (e.g., table 480 or 490)].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the above-mentioned feature(s) as taught by Tzeng in the system of Aweya in order to cause the system to able to allow various efficient actions to perform or support time synchronization among different nodes according to PTP message types [e.g., ¶0071 of Tzeng].
Regarding claim 2, Aweya in view of Tzeng discloses, the device according to claim 1 as set forth above. Aweya further discloses, wherein the packet processing circuitry is to process the time synchronization packets as a time synchronization leader to synchronize the at least one clock of the at least one remote device to the hardware clock [FIGS. 1-3; their related descriptions; ¶0042-0044; abstract; claim 1, note that the time server acts a time synchronization leader].
Regarding claim 3, Aweya in view of Tzeng discloses, the device according to claim 2 as set forth above. Aweya further discloses, wherein the packet processing circuitry is to participate in multiple concurrent time synchronization processes with multiple time synchronization clients [FIGS. 1-3; their related descriptions; ¶0035; abstract; claim 1, note that the time server is to participate in multiple concurrent time synchronization processes with multiple time synchronization time clients].
Regarding claim 10, Aweya in view of Tzeng discloses, the device according to claim 1 as set forth above. Aweya further discloses,
the interface [see supra rejections as set forth above in claim 1] is to receive a first time-synchronization packet from a given remote device [FIG. 3; its related descriptions; ¶0042, the time client 16 initially sends a request message 20 to the time server 14 (note that the time server requires at least one network interface to receive the request message 20) that contains the timestamp T1 that the message is sent; see abstract; claims 1-3, “sending time transfer protocol messages from the time client to the time server over a packet network”];
the packet processing circuitry [see supra rejections as set forth above in claim 1] includes a parser to parse the first time-synchronization packet yielding parsed data [FIG. 3; its related descriptions; ¶0042, the server 14 notes the time T2 it receives this message and, at a later time, sends a response message 22 back to the client 16 containing the time T1 (note that it requires at least one parser to parse the request message 20 to obtain the timestamp T1) the client sent the first message/the request message 20, the time T2 the server received that message, and the time T3 that the server sends the current message 22];
the steering circuitry is to cause generation of a second time-synchronization packet based on the parsed data and the first time-synchronization packet [FIG. 3; its related descriptions; ¶0042, the server 14 notes the time T2 it receives this message and, at a later time, sends a response message 22 (i.e., second time synchronization packet) back to the client 16 containing the time T1 the client sent the first message (i.e., based on the parsed data/timestamp T1 and the request message 20), the time T2 the server received that message, and the time T3 that the server sends the current message 22; see also claim 1, “receiving time transfer protocol messages from the time server”]; and
the interface [see supra rejections as set forth above in claim 1] is to send the second time-synchronization packet to the given remote device [FIG. 3; its related descriptions; ¶0042, the server 14 notes the time T2 it receives this message and, at a later time, sends a response message 22 (i.e., second time synchronization packet) back to the client 16; see also claim 1, “receiving time transfer protocol messages from the time server”].
Regarding claim 11, Aweya in view of Tzeng discloses, the device according to claim 10 as set forth above. Aweya further discloses,
the packet processing circuitry [see supra rejections as set forth above in claim 1] includes timestamping circuitry [FIG. 3; its related descriptions; ¶0042, note that performing the timestamping requires at least one circuitry] to sample a receive time of the first time-synchronization packet [FIG. 3; its related descriptions; ¶0042, see, the server 14 notes the time T2 it receives this message and, at a later time, sends a response message 22 back to the client 16 containing the time T1 the client sent the first message the time T2 the server received (i.e., sample a receive time of the first time-synchronization) packet that message] according to the clock time of the hardware clock [¶0015, the timing system includes a time server having a server clock for generating current timestamp information; note that the timestamp is generated based on the server clock]; and
the steering circuitry [FIG. 3; its related descriptions; ¶0042, note that performing sending the response message containing the time T2 requires inserting the time T2 into the response message 22 and at least one corresponding circuitry/steering circuitry to insert the time T2 into the response message 22] is to insert the receive time into the second time-synchronization packet [FIG. 3; its related descriptions; ¶0042, the server 14 notes the time T2 it receives this message and, at a later time, sends a response message 22 (i.e., second time-synchronization packet) back to the client 16 containing the time T1 the client sent the first message, the time T2 the server received (i.e., insert the receive time into the second time-synchronization packet) that message, and the time T3 that the server sends the current message 22].
Regarding claim 13, claim 13 recites similar features to claim 1 without additional features. Thus, claim 13 is rejected at least based on a similar rationale applied to claim 1.
Regarding claim 14, claim 14 is rejected at least based on a similar rationale applied to claim 2.
Regarding claim 15, claim 15 is rejected at least based on a similar rationale applied to claim 3.
Regarding claim 22, claim 22 is rejected at least based on a similar rationale applied to claim 10.
Regarding claim 23, claim 23 is rejected at least based on a similar rationale applied to claim 11.
Claims 4-5, 7-9, 16-17 and 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over Aweya et al (US Publication No. 2013/0282875 A1) in view of Tzeng et al (US Publication No 2023/0246723 A1 and further in view of Levi et al (US Publication No. 2021/0243140 A1).
Regarding claim 4, Aweya in view of Tzeng discloses, the device according to claim 1 as set forth above.
Aweya in view of Tzeng does not explicitly disclose (see, italicized limitations), but Levi discloses, a network interface controller [FIG. 1; its related descriptions; ¶0021, network adapter 28 may be referred to, for example, as a Network Interface Controller (NIC)].
It is noted that the above-mentioned feature is a known technique in the field Applicant's endeavor, e.g., telecommunication art.
It would have been obvious to one having ordinary skill in the art before the effective filing date to combine the system of Aweya in view of Tzeng with "the above-mentioned known feature(s)" taught by Levi to reach the claimed invention as set forth above. Since one having ordinary skill in the art could have recognized that applying the known technique taught by Levi into the system of Aweya in view of Tzeng would have yield predictable results and/or resulted in the improved system, such as e.g., achieving high-speed and low-latency packet processing with reduced CPU load by offloading networking functions, such a modification (or application) would have involved the mere application of a known technique to a piece of prior art ready for improvement," the claim is unpatentable under 35 U.S.C. 103(a). Ex Parte Smith, 83 USPQ.2d 1509, 1518-19 (BPAI, 2007) (citing KSR v. Teleflex, 127 S.Ct. 1727, 1740, 82 USPQ2d 1385, 1396 (2007)).
Regarding claim 5, Aweya in view of Tzeng discloses, the device according to claim 1 as set forth above.
Although Aweya discloses, “perform time synchronization operations of the two-way time synchronization protocol as a clock synchronization leader“ as set forth above in claims 1-2, Aweya in view of Tzeng does not explicitly disclose (see, italicized limitations), but Levi discloses, a network interface controller (NIC) application-specific integrated circuit (ASIC) [FIG. 1; its related descriptions; ¶0021, network adapter 28 may be referred to, for example, as a Network Interface Controller (NIC); further see ¶0031, the various elements of host 24 and network adapter 28 may be implemented using suitable hardware, such as one or more Application-Specific integrated Circuits (ASIC) or Field-Programmable Gate Arrays (FPGA), using software, or using a combination of hardware and software elements].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the above-mentioned feature(s) as taught by Levi in the system of Aweya in view of Tzeng for similar rationales set forth above in claim 4.
Regarding claim 7, Aweya in view of Tzeng discloses, the device according to claim 1 as set forth above.
Although Aweya discloses, “the packet processing circuitry is to process the time synchronization packets according to the two-way time synchronization protocol” as set forth above, Aweya in view of Tzeng does not explicitly disclose (see, italicized limitations), but Leve discloses, wherein the packet processing circuitry is to process . . . packets without the . . . packets being processed by a central processing unit (CPU) of a host device connected to the network device [FIG. 1; its related descriptions; ¶0023, network adapter 28 comprises a packet processor 52 that processes packets received from host 24 via interface 44, and/or from network 32 via interface 48; further see ¶0022, the CPU 36 of host 24 connected to the network adapter 28; note that the processing of packets is not made by the CPU 36].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the above-mentioned feature(s) as taught by Levi in the system of Aweya in view of Tzeng for similar rationales set forth above in claim 4.
Regarding claim 8, Aweya in view of Tzeng and Levi discloses, the device according to claim 7 as set forth above.
Although Aweya discloses, “process the time synchronization packets according to the two-way time synchronization protocol” as set forth above, Aweya in view of Tzeng does not explicitly disclose (see, italicized limitations), but Levi discloses, wherein the packet processing circuitry is to be configured by the CPU of the host device [FIG. 1; its related descriptions; ¶0023, 0025 and 0029, the operations of packet processor are configured by the CPU 24 of the host 24].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the above-mentioned feature(s) as taught by Levi in the system of Aweya in view of Tzeng for similar rationales set forth above in claim 4.
Regarding claim 9, Aweya in view of Tzeng and Levi discloses, the device according to claim 7 as set forth above.
Aweya in view of Tzeng does not explicitly disclose (see, italicized limitations), but Levi discloses, wherein the packet processing circuitry is to be controlled and managed by the CPU of the host device [FIG. 1; its related descriptions; ¶0023, 0025 and 0029, the operations of packet processor are controlled and managed by the CPU 24 of the host 24].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the above-mentioned feature(s) as taught by Levi in the system of Aweya in view of Tzeng for similar rationales set forth above in claim 4.
Regarding claim 16, claim 16 is rejected at least based on a similar rationale applied to claim 4.
Regarding claim 17, claim 17 is rejected at least based on a similar rationale applied to claim 5.
Regarding claim 19, claim 19 is rejected at least based on a similar rationale applied to claim 7.
Regarding claim 20, claim 20 is rejected at least based on a similar rationale applied to claim 8.
Regarding claim 21, claim 21 is rejected at least based on a similar rationale applied to claim 9.
Claims 6 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Aweya et al (US Publication No. 2013/0282875 A1) in view of Tzeng et al (US Publication No 2023/0246723 A1 and further in view of Sun et al (US Publication No. 2023/0082780 A1).
Regarding claim 6, Aweya in view of Tzeng discloses, the device according to claim 1 as set forth above.
Although Aweya discloses, “the packet processing circuitry is to process the time synchronization packets according to the two-way time synchronization protocol” as set forth above, Aweya in view of Tzeng does not explicitly disclose (see, italicized limitations), but Sun discloses, process packets at a rate at which respective ones of the packets are received by the network interface [¶0027, load balancer 108 can adjust a number of processing units that process packets of a heavy flow and adjust a number of processing units that process packets of a light flow based on whether more or fewer processing units are needed to process the packets for a particular receive rate of packets].
It is noted that the above-mentioned feature is a known technique in the field Applicant's endeavor, e.g., telecommunication art.
It would have been obvious to one having ordinary skill in the art before the effective filing date to combine the system of Aweya in view of Tzengwith "the above-mentioned known feature(s)" taught by Sun to reach the claimed invention as set forth above. Since one having ordinary skill in the art could have recognized that applying the known technique taught by Sun into the system of Aweya in view of Tzeng would have yield predictable results and/or resulted in the improved system, such as e.g., ensuring low latency and sustained throughput at a rate, such a modification (or application) would have involved the mere application of a known technique to a piece of prior art ready for improvement," the claim is unpatentable under 35 U.S.C. 103(a). Ex Parte Smith, 83 USPQ.2d 1509, 1518-19 (BPAI, 2007) (citing KSR v. Teleflex, 127 S.Ct. 1727, 1740, 82 USPQ2d 1385, 1396 (2007)).
Regarding claim 18, claim 18 is rejected at least based on a similar rationale applied to claim 6.
Claims 12 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Aweya et al (US Publication No. 2013/0282875 A1) in view of Tzeng et al (US Publication No 2023/0246723 A1 and further in view of Matsumoto et al (US Publication No. 2022/0345290 A1).
Regarding claim 12, Aweya in view of Tzeng discloses, the device according to claim 11 as set forth above. Although Aweya further discloses,
the timestamping circuitry [see supra rejections as set forth above in claim 11] is to
sample a transmission time of the second time-synchronization packet [FIG. 3; its related descriptions; ¶0042, sends a response message 22 back to the client 16 containing the time T1 the client sent the first message, the time T2 the server received that message, and the time T3 that the server sends the current message 22] according to the clock time of the hardware clock [¶0015, the timing system includes a time server having a server clock for generating current timestamp information; note that the timestamp is generated based on the server clock];
the steering circuitry [see supra rejections as set forth above in claim 10] . . .; and
the interface [see supra rejections as set forth above in claim 1] . . ., Aweya in view of Tzeng does not explicitly disclose (see, italicized limitations), but Matsumoto discloses, sample a transmission time of the second time-synchronization packet, . . . to generate a third time-synchronization packet and insert the transmission time into the third time-synchronization packet [FIG. 3; its related descriptions; ¶0077, the time server 4 as a GMC leader device transmits a synchronization packet Follow_Up (i.e., third time-synchronization packet) carrying transmission timestamp information t1 (i.e., a transmission time of the second time-synchronization packet) about the transmission of the synchronization packet Sync (i.e., second time-synchronization packet) to the sensor system 3 serving as a PTP follower device; note that transmitting a packet requires generating the packet]; and to send the third time-synchronization packet to the given remote device [FIG. 3; its related descriptions; ¶0077, the time server 4 as a GMC leader device transmits a synchronization packet Follow up (i.e., third time-synchronization packet) to the sensor system 3 serving as a PTP follower device].
It is noted that the above-mentioned feature is a known technique in the field Applicant's endeavor, e.g., telecommunication art.
It would have been obvious to one having ordinary skill in the art before the effective filing date to combine the system of Aweya in view of Tzeng with "the above-mentioned known feature(s)" taught by Matsumoto to reach the claimed invention as set forth above. Since one having ordinary skill in the art could have recognized that applying the known technique taught by Matsumoto into the system of Aweya in view of Tzeng would have yield predictable results and/or resulted in the improved system, such as e.g., enabling accurate clock offset and delay measurements by correlating timestamps between the synch packet and follow-up packet, such a modification (or application) would have involved the mere application of a known technique to a piece of prior art ready for improvement," the claim is unpatentable under 35 U.S.C. 103(a). Ex Parte Smith, 83 USPQ.2d 1509, 1518-19 (BPAI, 2007) (citing KSR v. Teleflex, 127 S.Ct. 1727, 1740, 82 USPQ2d 1385, 1396 (2007)).
Regarding claim 24, claim 24 is rejected at least based on a similar rationale applied to claim 12.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUN JONG KIM whose telephone number is (571)270-3216. The examiner can normally be reached on 7:30am-5:30pm (M-T).
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/SUN JONG KIM/Primary Examiner, Art Unit 2469
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