Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-23 are pending.
Examiner Notes
Examiner cites particular paragraphs and/or columns and lines in the references as applied to Applicant’s claims for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the Applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. The prompt development of a clear issue requires that the replies of the Applicant meet the objections to and rejections of the claims. Applicant should also specifically point out the support for any amendments made to the disclosure. See MPEP § 2163.06.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Authorization for Internet Communications in a Patent Application
Applicant is encouraged to file an Authorization for Internet Communications in a Patent Application form (http://www.uspto.gov/sites/default/files/documents/sb0439.pdf) along with the response to this office action to facilitate and expedite future communication between Applicant and the examiner. If the form is submitted then Applicant is requested to provide a contact email address in the signature block at the conclusion of the official reply.
Allowable Subject Matter
Claims 4-10 and 19-22 are objected to as being dependent upon a rejected base claim, but would be allowable over the prior art of record if rewritten to overcome the applicable rejection(s) and/or objection(s) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims because the examiner found neither prior art cited in its entirety, nor based on the prior art, found any motivation to combine any of the said prior art.
The primary reason for allowance for claims 4-10 and 19-22 is provide the virtual counter value of the VM to the VM upon request of the VM based on a given relationship between the value of the CPU counter and the virtual counter value, wherein the transformation between the master clock time and the virtual counter value of the VM is based on (a) the given relationship between the value of the CPU counter and the master clock time; and (b) the given relationship between the value of the CPU counter and the virtual counter value in conjunction with the rest of the limitations set forth in the claims.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-23 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (an abstract idea) without significantly more.
Step 1: The claim is a process, machine, manufacture, or composition of matter:
Claim 1. A system, comprising a peripheral device, which includes.
Step 2A Prong One: The claim recites an abstract idea because it includes limitations that can be considered mental processes (concepts performed in the human mind including an observation, evaluation, judgment, and/or opinion). If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the human mind or via pen and paper, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea:
the host device maintaining a master clock time (abstract idea mental process);
a hardware clock to maintain a peripheral device clock time (abstract idea mental process); and
transform the master clock time to a frame of reference of the VM (abstract idea mental process).
Step 2A Prong Two: The abstract idea is not integrated into a practical application because the abstract idea is recited but for generically recited additional computer elements (i.e. data storage, processor, memory, computer readable medium, etc.) which do not add meaningful limitations to the abstract idea amounting to simply implementing the abstract idea on a generic computer using generic computing hardware and/or software (e.g. generally linking the use of the judicial exception to a particular technological environment or field of use (see MPEP 2106.05(h)). Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. The generic computing components are recited at a high-level of generality such that they amount to no more than mere instructions to apply the exception using the recited generic computer components. Accordingly, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea:
an interface (generic computing components) to receive from a virtual machine (VM) running on a host device (generic computing components), over a communication data bus (generic computing components), a request for timing data derived from a time measurement dialogue (generic computing components performing extra-solution activity of receiving data/information),
processing circuitry (generic computing components) to:
provide to the VM, over the communication data bus, the timing data based on the peripheral device clock time, and the master clock time transformed to the frame of reference of the VM (generic computing components performing extra-solution activity of sending/receiving data/information).
Step 2B: The claim includes limitations which can be considered extra-solution activity (see MPEP 2106.05(g)) insufficient to amount to significantly more than the abstract idea because the additional limitations only perform at least one of collecting, gathering, displaying, generating, modifying, updating, storing, retrieving, sending, and receiving data/information data which are well-understood, routine, conventional computer functions as recognized by the court decisions listed in MPEP § 2106.05(d)II. The claim further includes limitations that do not integrate the judicial exception into a practical application because they merely recite the words "apply it" (or an equivalent) with the judicial exception, or merely including instructions to implement an abstract idea on a computer, or merely using a computer as a tool to perform an abstract idea, as discussed in MPEP § 2106.05(f). Therefore, the claim, and its limitations when considered separately and in combination, is directed to patent ineligible subject matter:
an interface to receive from a virtual machine (VM) running on a host device, over a communication data bus, a request for timing data derived from a time measurement dialogue (extra-solution activity of receiving data/information),
provide to the VM, over the communication data bus, the timing data based on the peripheral device clock time, and the master clock time transformed to the frame of reference of the VM (extra-solution activity of sending/receiving data/information).
Claim 2. The system according to claim 1, wherein the processing circuitry is to:
retrieve the peripheral device clock time at time t (extra-solution activity of retrieving data/information);
compute the master clock time at time t (abstract idea mental process);
transform the master clock time at time t to the frame of reference of the VM (abstract idea mental process); and
provide to the VM, over the communication data bus, the timing data including a simultaneous snapshot of the master clock time at time t transformed to the frame of reference of the VM and the peripheral device clock time at time t (extra-solution activity of sending/receiving data/information).
Claim 3. The system according to claim 1, wherein the processing circuitry is to transform the master clock time to the frame of reference of the VM based on a transformation between the master clock time and a virtual counter value of the VM (abstract idea mental process).
Claim 4. The system according to claim 3, further comprising the host device including:
a master clock to maintain the master clock time (abstract idea mental process);
a CPU counter, wherein a value of the CPU counter has a given relationship with the master clock time (generic computing components);
a central processing unit (CPU) (generic computing components) to:
run a hypervisor to manage the VM (generic computing components);
provide the virtual counter value of the VM to the VM upon request of the VM based on a given relationship between the value of the CPU counter and the virtual counter value, wherein the transformation between the master clock time and the virtual counter value of the VM is based on (a) the given relationship between the value of the CPU counter and the master clock time; and (b) the given relationship between the value of the CPU counter and the virtual counter value (extra-solution activity of sending/transmitting data/information).
Claim 5. The system according to claim 4, wherein the hypervisor is to instruct the peripheral device to apply the transformation between the master clock time and the virtual counter value of the VM when providing the master clock time to the VM (extra-solution activity of sending/receiving data/information).
Claim 6. The system according to claim 4, wherein the processing circuitry is to run a virtual function of the peripheral device to transform the master clock time to the frame of reference of the VM based on the transformation between the master clock time and the virtual counter value of the VM (extra-solution activity of modifying/updating data/information).
Claim 7. The system according to claim 6, wherein the hypervisor is to configure the virtual function to apply the transformation between the master clock time and the virtual counter value of the VM when providing the master clock time to the VM (extra-solution activity of modifying/updating data/information).
Claim 8. The system according to claim 6, wherein the peripheral device includes a network device, and the virtual function of the peripheral device is a virtual network adapter of the VM (generic computing components).
Claim 9. The system according to claim 4, wherein the host device includes a root port, which includes the master clock (generic computing components).
Claim 10. The system according to claim 9, wherein the host device includes an oscillator to provide an output signal for use by the master clock and the CPU counter (generic computing components).
Claim 11. The system according to claim 1, wherein the processing circuitry is to run a virtual function of the peripheral device to transform the master clock time to the frame of reference of the VM based on a transformation between the master clock time and a virtual counter value of the VM (extra-solution activity of modifying/updating data/information).
Claim 12. The system according to claim 11, wherein the peripheral device includes a network device, and the virtual function of the peripheral device is a virtual network adapter of the VM (generic computing components).
Claim 13. The system according to claim 11, wherein the peripheral device includes a graphic processing unit (GPU), and the virtual function of the peripheral device is a virtual GPU of the VM (generic computing components).
Claim 14. The system according to claim 1, wherein the master clock of the host device is comprised in a root port of the host (generic computing components).
Claim 15. The system according to claim 1, wherein the processing circuitry is to compute the master clock time according to Precision Time Measurement (PTM) based on measurement messages exchanged by any two or more of the following: the host device; the peripheral device; and a switch device disposed in the communication data bus between the host device and the peripheral device (abstract idea mental process).
As per claim 16, it has similar limitations as claim 1 and is therefore rejected using the same rationale.
As per claim 17, it has similar limitations as claim 2 and is therefore rejected using the same rationale.
As per claim 18, it has similar limitations as claim 3 and is therefore rejected using the same rationale.
As per claim 19, it has similar limitations as claim 4 and is therefore rejected using the same rationale.
As per claim 20, it has similar limitations as claim 5 and is therefore rejected using the same rationale.
As per claim 21, it has similar limitations as claim 6 and is therefore rejected using the same rationale.
As per claim 22, it has similar limitations as claim 7 and is therefore rejected using the same rationale.
As per claim 23, it has similar limitations as claim 15 and is therefore rejected using the same rationale.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Karnes (US 2016/0112182) in view of Landers (US 9,459,652).
As per claim 1, Karnes primarily teaches the invention as claimed including a system, comprising, which includes:
an interface (fig. 9B, blocks 115 and 208 network interface card and virtual network interface cards) to receive from a virtual machine (VM) (fig. 9B, block 206A-C VM guest platform) running on a host device (fig. 9B, block 400 VM host hardware system), over a communication data bus (fig. 9B, blocks 108 and 905 interconnect bridge and communication link), a request for timing data derived from a time measurement dialogue ([0076] as with the transparent clock and the boundary clock, the VM master clock is configured to send time requests to the hardware and to receive time data from the hardware through request/data messages communicated through a communication link), the host device maintaining a master clock time ([0076] master clock);
a hardware clock to maintain a peripheral device clock time ([0076] hardware real time clock).
Karnes does not explicitly teach:
a peripheral device and processing circuitry to:
transform the master clock time to a frame of reference of the VM; and
provide to the VM, over the communication data bus, the timing data based on the peripheral device clock time, and the master clock time transformed to the frame of reference of the VM.
However, Landers teaches:
a peripheral device (col. 3, ll. 12 mouse and keyboard) and processing circuitry (col. 3, ll. 61-64 physical circuits) to:
transform the master clock time to a frame of reference of the VM (abstract virtual clock switch permits accurate transfer of reference time from a variety of different time sources, transforms the reference time representation into one of a collection of different formats, and makes the reference time available to guest operating system instances running as virtual machines and col. 2, ll. 22-32 transforming the reference time into a format suitable for the guest operating system, and supplying the transformed reference time to the guest operating system); and
provide to the VM, over the communication data bus, the timing data based on the peripheral device clock time, and the master clock time transformed to the frame of reference of the VM (col. 4, ll. 37-49 combine results of multiple reference time sources and distribute the reference time to any number of guest operating systems running in virtual machines. Distribute the reference time to virtual reference clocks and the reference time is supplied from there to the guest reference clocks of operating systems. It is to be understood that the virtual clock switch distributes the reference time to operating systems of any other virtual machines running in host computer system and col. 8, ll. 24-35 where the reference time reference time is computed from multiple timing sources by the virtual clock switch at periodic intervals and propagated up to the guest reference clocks of different virtual machines, the latency through the virtual clock switch and the multiple timing sources is propagated to the guest reference clocks along with the reference time. The guest reference clocks adjust the reference time based on this latency. In an alternative embodiment, the virtual clock switches adjust the reference time based on this latency and propagate the adjusted reference time to the guest reference clocks).
Landers and Karnes are both concerned with clocking in computing environments and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Karnes in view of Landers because it would provide for accurate transfer of reference time from a variety of different time sources, transformation the reference time representation into one of a collection of different formats, and availability of the reference time to guest operating system instances running as virtual machines. As a result, reference time accuracy is increased, security improved, and the opportunity for providing redundancy in the event of hardware or software failures. Also, the ability to morph time formats allows the concept to be applied to guest virtual machines without the need to modify the guest operating system.
As per claim 16, it has similar limitations as claim 1 and is therefore rejected using the same rationale.
Claims 2 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Karnes in view of Landers in view of Loukianov et al. (US 2005/0138455) (hereinafter Loukianov).
As per claim 2, Karnes in view of Landers teaches:
retrieve the peripheral device clock time at time t (Karnes [0076] hardware real time clock);
compute the master clock time at time t (Karnes [0076] master clock);
transform the master clock time at time t to the frame of reference of the VM (Landers abstract virtual clock switch permits accurate transfer of reference time from a variety of
different time sources, transforms the reference time representation into one of a collection of different formats, and makes the reference time available to guest operating system instances running as virtual machines and col. 2, ll. 22-32 transforming the reference time into a format suitable for the guest operating system, and supplying the transformed reference time to the guest operating system).
Karnes in view of Landers does not explicitly teach:
provide to the VM, over the communication data bus, the timing data including a simultaneous snapshot of the master clock time at time t transformed to the frame of reference of the VM and the peripheral device clock time at time t.
However, Loukianov teaches:
provide to the VM, over the communication data bus, the timing data including a simultaneous snapshot of the master clock time at time t transformed to the frame of reference of the VM and the peripheral device clock time at time t ([0031] additional logic around the counters may be designed to monitor when processors sample the counter values and generate a snapshot of program clock counters at the same time instance).
Loukianov and Karnes are both concerned with clocking in computing environments and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Karnes in view of Landers in view of Loukianov because it would provide a way to facilitate playback of media information at a receiver, by synchronizing program clocks in the presence of severe and unknown transport delays/jitter possible in computing networks.
As per claim 17, it has similar limitations as claim 2 and is therefore rejected using the same rationale.
Claims 3 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Karnes in view of Landers in view of Todd (US 2016/0087615).
As per claim 3, Karnes in view of Landers does not explicitly teach wherein the processing circuitry is to transform the master clock time to the frame of reference of the VM based on a transformation between the master clock time and a virtual counter value of the VM.
However, Todd teaches wherein the processing circuitry is to transform the master clock time to the frame of reference of the VM based on a transformation between the master clock time and a virtual counter value of the VM (abstract and [0013] debounce circuit includes a strobe generator that produces a strobe signal that is a submultiple of a master clock that is determined by the location of the physical counter within the virtual counter that is used to increment the physical counter within the virtual counter).
Todd and Karnes are both concerned with clocking in computing environments and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Karnes in view of Landers in view of Todd because it would provide circuits for eliminating noise, glitches, or transient signal variations resulting from mechanical bounce occurring at an initiation of a change of state of analog signals that supports a dynamic debounce period alteration and time base variation without loss of the current debounce state.
As per claim 18, it has similar limitations as claim 3 and is therefore rejected using the same rationale.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Karnes in view of Landers in view of Regniere et al. (US 2021/0049030) (hereinafter Regniere).
As per claim 11, Karnes in view of Landers does not explicitly teach wherein the processing circuitry is to run a virtual function of the peripheral device to transform the master clock time to the frame of reference of the VM based on a transformation between the master clock time and a virtual counter value of the VM.
However, Regniere teaches wherein the processing circuitry is to run a virtual function of the peripheral device to transform the master clock time to the frame of reference of the VM based on a transformation between the master clock time and a virtual counter value of the VM ([0009] allocating performance counters to virtual machines in response to requests obtained from a virtual function associated with the virtual machine; [0026] performance data associated with the respective performance counter allocated to the virtual function is retrieved from memory in response to the restore operation associated with the virtual function; [0030] virtual function being restored to operation on the virtual machine).
Regniere and Karnes are both concerned with clocking in computing environments and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Karnes in view of Landers in view of Regniere because it would facilitate techniques for allocating registers configured to be implemented as performance counters to virtual functions in response to a request from a respective one of the virtual functions associated with a virtual machine executing on the GPU.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Karnes in view of Landers in view of Regniere in view of Cao et al. (US 2021/0200573) (hereinafter Cao).
As per claim 12, Karnes in view of Landers in view of Regniere do not explicitly teach wherein the peripheral device includes a network device, and the virtual function of the peripheral device is a virtual network adapter of the VM.
However, Cao teaches wherein the peripheral device includes a network device, and the virtual function of the peripheral device is a virtual network adapter of the VM ([0087] the single-root input/output virtualization network adapter includes at least one physical function and at least one virtual function. In this embodiment, a virtual function of the single-root input/output virtualization network adapter is obtaining a virtual network adapter through virtualization).
Cao and Karnes are both concerned with timing in computing environments and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Karnes in view of Landers in view of Regniere in view of Cao because it would provide a way for each virtual machine to directly exchange network I/O data with one or more virtual network adapters corresponding to the virtual machine. Therefore, there is no need to use the virtual machine manager. This reduces I/O performance overheads in the virtual machine manager, and ensures I/O throughput efficiency of each VM.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Karnes in view of Landers in view of Regniere in view of Rogers et al. (US 2023/0094125) (hereinafter Rogers).
As per claim 13, Regniere teaches wherein the peripheral device includes a graphic processing unit (GPU) ([0011] GPU).
Karnes in view of Landers in view of Regniere do not explicitly teach and the virtual function of the peripheral device is a virtual GPU of the VM.
However, Rogers teaches and the virtual function of the peripheral device is a virtual GPU of the VM ([0064] virtual function associated with a virtual GPU and [0266] virtual machines).
Rogers and Karnes are both concerned with clocking in computing environments and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Karnes in view of Landers in view of Regniere in view of Rogers because it would provide a novel solution to provide secure execution environments that leverage parallel processing units such as graphics processing units (GPUs), to execute user code or perform other operations in a virtualized environment. In such environments, optimizations can be performed by a compiler to leverage execution streams and computing resources of the PPUs. In one example, an execution stream includes a sequence of operations that executes in order, where different execution streams are executed concurrently and can be executed out of order with respect to other execution streams. The use of these execution streams can improve performance by at least overlapping memory copies and kernel executions.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Karnes in view of Landers in view of Shima (US 6,718,476).
As per claim 14, Karnes in view of Landers do not explicitly teach wherein the master clock of the host device is comprised in a root port of the host.
However, Shima teaches wherein the master clock of the host device is comprised in a root port of the host (abstract local clock of the root node serves as the master clock for synchronizing the local clocks of the other nodes).
Shima and Karnes are both concerned with clocking in computing environments and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Karnes in view of Landers in view of Shima because it would provide a way to couple the output terminal of the clock source selection circuit to either the clock recovery circuit or the local clock generator to facilitate synchronization of the local clock to a master clock to reduce jitter in the cycle counter of the node and in the cycle counters of the other nodes when the cycle counters are updated with the value of the cycle counter of the root node.
Claims 15 and 23 are s rejected under 35 U.S.C. 103 as being unpatentable over Karnes in view of Landers in view of McGowan (US 2017/0286359).
As per claim 15, Karnes in view of Landers do not explicitly teach wherein the processing circuitry is to compute the master clock time according to Precision Time Measurement (PTM) based on measurement messages exchanged by any two or more of the following: the host device; the peripheral device; and a switch device disposed in the communication data bus between the host device and the peripheral device.
However, McGowan teaches wherein the processing circuitry is to compute the master clock time according to Precision Time Measurement (PTM) based on measurement messages exchanged by any two or more of the following: the host device; the peripheral device; and a switch device disposed in the communication data bus between the host device and the peripheral device ([0026] Precision Time Management based on host and peripherals connected via a hub and [0062] PTM allows the devices attached to a USB controller to maintain a master clock that is within 40 ns of the master clock maintained by other devices attached to the controller).
McGowan and Karnes are both concerned with clocking in computing environments and are therefore combinable/modifiable. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Karnes in view of Landers in view of McGowan because it would provide a highly accurate bus interval boundary timing for devices. Hub delay measurement may be used to improve device bus interval boundary timing accuracy even if link delay measurement timing information is not available, or vice versa. For example, USB SuperSpeedPlus hosts and hubs currently are required to support PTM. PTM support may be optional for peripheral devices and/or SuperSpeed only hosts and hubs. In one embodiment, PTM is supported by all components of a USB topology; e.g., PTM capable hubs are to improve the overall accuracy of a device's notion of the bus interval boundary timing.
As per claim 23, it has similar limitations as claim 15 and is therefore rejected using the same rationale.
Citation of Relevant Prior Art
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure:
Yuenyongsgool et al. (US 2014/0270253) disclose flexible clocking for audio sample rate converter in a USB system.
Wang (US 2022/0197850) disclose directly synchronizing time-base between generic timers and PCIE PTM protocol.
Thampi et al. (US 2020/0401434) disclose precision time control in a virtualized environment.
Nair et al. (US 2016/0146710) disclose time-stamping and synchronization for single-wire safety communication.
Hoffleit et al. (US 2021/0258136) disclose time synchronization.
De Amorim et al. (US 2014/0019793) disclose strictly increasing virtual clock for high-precision timing of programs in multiprocessing systems.
Bar Bracha (US 2016/0192302) disclose synchronizing between wireless communication devices.
Biederman et al. (US 2023/0370241) disclose time synchronization.
Bhandari et al. (US 2019/0087215) disclose hypervisor timer techniques.
Amorim et al. (US 2006/0212738) disclose distributed global clock for clusters of computers.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Adam Lee whose telephone number is (571) 270-3369. The examiner can normally be reached on M-TH 8AM-5PM.
If attempts to reach the above noted Examiner by telephone are unsuccessful, the Examiner’s supervisor, Pierre Vital, can be reached at the following telephone number: (571) 272-4215. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Adam Lee/Primary Examiner, Art Unit 2198 September 8, 2026
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