DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant has added new claim 21 without stating where support exists for new claim 21. Examiner notes Figure 10 provides support for new claim 21.
Response to Arguments
Applicant's arguments filed on 7/23/2026 have been fully considered but they are not persuasive. Applicant argues the combination of Lu’s diode 622, capacitor Cboot 624 and half-wave rectifier 630 do not represent a charge pump. Examiner respectfully disagrees and maintains circuit 622,624 and 630 form a boosting charge pump. Examiner reminds Applicant how a boosting charge pump operates. A charge pump uses a two phase cycle to perform charging of a capacitor in the first phase, then placing the capacitor in series with a voltage during the second phase. Clearly circuit 622,624,630 of Lu operates as a boosting charge pump; during the first phase node 610 is pulled low by switch 604 so Cboot 624 is charged to Vin through 622. During the second phase, node 610 is raised to the output Vbst by turning on switch 608, which raises the voltage at node 628 to the nominal voltage of Vin + Vbst. Circuit 630 can then be controlled to pass the boosted voltage at node 628 to node 636. Lu uses the pre-existing switching circuit CL3,CL4,604 and 608 to drive node 610 high and low and does not use a dedicated clock circuit to drive node 610, but nothing in the claim or Applicant’s disclosure requires a dedicated clock driving node 610 of the charge pump.
Applicant further argues Lu teaches away from the use of charge pumps. Firstly, Examiner reminds Applicant that the principle of teaching away applies to obviousness type rejections where there is an attempt to modify a feature in a manner that is taught away by the reference, while the present rejection is an anticipation rejection for which it is well established that teaching away has no bearing as the feature is already present and not modified. Secondly, it is more accurate to summarize that the Lu reference teaches away from using a dedicated charge pump, that is, dedicated circuitry to drive node 610. Lu teaches use of a charge pump, as Lu discloses use of charge pump 622,624,630, and teaches away from using a dedicated charge pump. Examiner points out that nothing in Applicant’s claim language or disclosure requires use of a dedicated charge pump or dedicated clock circuitry to drive node 610 of the charge pump. Likewise, nothing in the claim language or disclosure requires the charge pump to operate at extreme duty cycles of switching circuit switches CL3,CL4 or prevents the driving of node 610 from pre-existing switching structures. Examiner acknowledges Lu’s charge pump 622,624,630 is not a dedicated charge pump, but is a charge pump because it operates to pump the charge. Examiner concludes, at least in a broadest reasonable sense, Lu’s circuit 622,624,630 forms a charge pump because it pumps the charge of capacitor Cboot to boost the voltage.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 10-11 are rejected under 35 U.S.C. 102a1 as being anticipated by Lu (US 10,686,377).
With respect to claim 10, Lu discloses a voltage converter (Fig. 6 600), comprising: a boost converter (Fig. 6 602,604,608) having an input (Fig. 6 612) and an output (Fig. 6 614); a first transistor (Fig. 6 616; column 6, lines 30-31 “switch 616 may be implemented by a N-type transistor switch such as a N-type MOSFET switch.”) having a control input (Fig. 6 CL1), a first terminal (Fig. 6 612), and a second terminal (Fig. 6 610), the first terminal coupled to the input (Fig. 6 612) of the boost converter, the second terminal coupled (Fig. 6 610 coupled to 614 through 608) to the output of the boost converter; a driver (Fig. 6 620,626) having a first input (Fig. 6 636), a first output (Fig. 6 CL3), and a second output (Fig. 6 CL1), the first output coupled to the boost converter (Fig. 6 604), and the second output coupled to the control input (Fig. 6 CL1) of the first transistor; and a charge pump (Fig. 6 622,624,630) having an input (Fig. 6 6 Vbst in 630) and output (Fig. 6 636), the input of the charge pump coupled to the output (Fig. 6 614 Vbst) of the boost converter, and the output of the charge pump coupled to the first input (Fig. 6 input to 626) of the driver.
With respect to claim 11, Lu discloses the voltage converter of claim 10, wherein the first transistor is an n-channel field effect transistor (Fig. 6 616; column 6, lines 30-31 “switch 616 may be implemented by a N-type transistor switch such as a N-type MOSFET switch.”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10-12, 16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Oikarinen (US 2013/0249438) in view of Lu (US 10,686,377).
With respect to claim 10, Oikarinen discloses a voltage converter (Fig. 1 100), comprising: a boost converter (Fig. 1 L,111-112) having an input (Fig. 1 105) and an output (Fig. 1 106); a first transistor (Fig. 1 Q3) having a control input (Fig. 1 gate of Q3), a first terminal (Fig. 1 105), and a second terminal (Fig. 1 106), the first terminal coupled to the input of the boost converter, the second terminal coupled to the output of the boost converter. Oikarinen remains silent as to the details of the driver.
Lu discloses a driver (Fig. 6 626, Fig. 12 1206) having a first input (Fig. 6 636), a first output (Fig.6 626 to 608), and a second output (Fig. 12 1206 output), the first output coupled to the boost converter (Fig. 6 608), and the second output coupled to the control input (Fig. 12 gate 1202) of the first transistor; and a charge pump (Fig. 6 622,624,630) having an input and output, the input (Fig. 6 Vbst of 630) of the charge pump coupled to the output of the boost converter, and the output (Fig. 6 636) of the charge pump coupled to the first input of the driver. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement a driver having a first input, a first output, and a second output, the first output coupled to the boost converter, and the second output coupled to the control input of the first transistor; and a charge pump having an input and output, the input of the charge pump coupled to the output of the boost converter, and the output of the charge pump coupled to the first input of the driver, in order to raise the gate signal of the first transistor to a voltage higher than the output voltage in order to turn on the first transistor.
With respect to claim 11, Oikarinen in view of Lu make obvious the voltage converter of claim 10, wherein the first transistor is an n-channel field effect transistor (Fig. 1 Q3).
With respect to claim 12, Oikarinen in view of Lu make obvious the voltage converter of claim 10, wherein: the boost converter has a high side (HS) transistor (Fig. 1 Q2) and a low side (LS) transistor (Fig. 1 Q1), the HS transistor having a control input (Fig. 1 gate of Q2) coupled to the first output (Lu Fig. 6 output of 626) of the driver; the driver has a second input (as in Lu Fig. 20 CL4’ ; Fig. 12 CL1) and a third input (Fig. 1 BYPASS), the driver configured to: in response to a first control signal (Fig. 1 gate signal to Q2) at the second input being at a first logic state (Fig. 1 Q2 ON) and a second control signal (Fig. 1 BYPASS) at the third input being at a second logic state (Fig. 1 BYPASS OFF), turn on the HS transistor and turn off the first transistor; and in response to the first control signal being at a second logic state (Fig. 1 Q2 OFF) and the second control signal being at the first logic state (Fig. 1 BYPASS ON), turn on the first transistor and turn off the HS transistor.
With respect to claims 16 and 18, Oikarinen in view of Lu make obvious the voltage converter as set forth above. See claims 10,12 and 11, respectively, for additional details.
Claim(s) 13 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Oikarinen (US 2013/0249438) in view of Lu (US 10,686,377) and further in view of Oporta (US 11,606,031).
With respect to claim 13, Oikarinen in view of Lu make obvious the voltage converter of claim 12 as set forth above, and do not detail the driver at the transistor level, which was well known before the effective filing date of the claimed invention.
Oporta discloses wherein the driver comprises: a first transistor (Fig. 4 Q9) having a first terminal (Fig. 4 Q9 source) and a second terminal (Fig. 4 Q9 drain); a second transistor (Fig. 4 Q6) having a first terminal (Fig. 4 Q6 source) and a second terminal (Fig. 4 Q6 drain), the first terminal of the second transistor coupled to the first terminal of the first transistor; and a third transistor (Fig. 4 Q7) having a first terminal (Fig. 4 Q7 source) and a second terminal (Fig. 4 Q7 drain), the second terminal of the third transistor coupled to the second terminal of the second transistor. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement wherein the driver comprises: a first transistor having a first terminal and a second terminal; a second transistor having a first terminal and a second terminal, the first terminal of the second transistor coupled to the first terminal of the first transistor; and a third transistor having a first terminal and a second terminal, the second terminal of the third transistor coupled to the second terminal of the second transistor, in order to implement the driver with the required gate driving characteristics.
With respect to claim 19, Oikarinen in view of Lu and Oporta make obvious the voltage converter as set forth above. See claims 13 for additional details.
Allowable Subject Matter
Claims 14-15, 17 and 20-21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. See the action dated 4/29/2026 for the reasons for allowance for claims 14-15, 17 and 20. The following is a statement of reasons for the indication of allowable subject matter for claim 21:
With respect to claim 21, the prior art does not disclose or suggest, in combination with the limitations of the base claim and any intervening claims, primarily, wherein t
The aforementioned limitations in combination with all remaining limitations of the respective claims are believed to render the aforementioned indicated claim and any dependent claims thereof patentable over the art of record.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HARRY RAYMOND BEHM whose telephone number is (571)272-8929. The examiner can normally be reached M-F: 8-5 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu Tran can be reached at 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HARRY R BEHM/Primary Examiner, Art Unit 2838
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