Detailed Action
Summary
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1.This office action is in response to application filed on May 15,2024.
2. Claims 1-20 are pending and has been examined.
Drawings
3. Drawings submitted on 05/15/2024 are acceptable.
Claim Rejections - 35 USC § 112
4. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 14 recites “further comprising a comparator” are used in the claim is vague and unclear because claim 14 depend on claim 8 and claim 8 is already introduced a comparator in the claim language. Examiner best understood that there is no further comparator/another/other/second comparator are showing in Figs. 1-3 of the claimed invention. Therefore, it is not clear to the examiner “further comprising a comparator” is referring to another/ second comparator or the same comparator that introduced in claim 8. For the purpose of this examination, examiner understood that further comprising comparator is referring to the same comparator 114 of claim 8.
Rejections - 35 USC § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2,8,10,14-15 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Jovanovic “20230043741” in a view of Jovanovic “11552563”. Hereafter Jovanovic “3741” and “2563”.
In re to claim 1, Jovanovic “3741” discloses a circuit (Figs. 1-8 shows power converter circuit. Examiner note that Figs. 1-8 are considered as the same embodiments) comprising: an amplifier (Fig. 3: comparator 302 ) having a feedback input (voltage level of regulated power supply node 109 ) , a reference input (reference voltage node 105), and an error output (Fig.3: error signal 107) ;
a capacitor (Fig.3: capacitor 305) having a first capacitor terminal coupled to the error output (107) , and second capacitor terminal (second plate of capacitor 305 is coupled to 105);
a voltage controlled current source (VCCS) (Fig. 3: injection circuit 304, Fig.4 : injection circuit 204 comprises amplifier circuit 402, amplifier circuit 403 and current source 404 ) having a first terminal (Fig. 3: injection circuit 304 terminal) is coupled to the first capacitor terminal (Fig. 3: injection current (308) is coupled to first terminal of capacitor 305 thru diode 307), and
a VCCS input (Figs.3 and 4: regulated power supply node (109))
a differentiator circuit (Fig. 4: filter unit (401) :by comparing the filtered and unfiltered versions of the voltage level of regulated power supply node 109, filter circuit 401 can detect a drop in the voltage level of regulated power supply node 109 that occurs within a particular period of time., see prag. 0042), and an output coupled to the VCCS input (Fig.4: output of 401 generates filter signals 406 &407 are coupled 402 ).
Jovanovic “3741” fails to discloses a resistor having a first resistor terminal coupled to the second capacitor terminal, and a second resistor terminal and differential circuit coupled to a second terminal coupled to the second resistor terminal.
Whereas Jovanovic “2563” discloses a power converter ( Fig. 3A) discloses compensation circuit (Fig. 3A: compensation circuit (315) comprises resistor R3, resistor R4 and capacitor C4 are coupled in series and second resistor R4 is coupled to capacitor C4) and slope detector (305) which comprises a differentiator circuit comparing bandpass filter 314 voltage and an output is connected between resistor R3 and R4 to inject error signal V_error via compensation circuit network 315).
Therefore, it would have been obvious to one of ordinary skilled person in the art before the effective filing date of the claimed invention to have modified the filter capacitor C4 of Jovanovic “3741” to include a compensation network filter 315 as taught by Jovanovic “2563” because bandpass filter 315 may substantially reject signals outside of a frequency band defined by the respective component values of R1, C1, R2, and C2, thus provide the amount of current that is desired to be delivered to the output node, Vout, for a given operating condition which improve the efficiency of the power converter, see col. 6, lines 46-50 and col. 6, lines 7-9 .
In re to claim 2, Jovanovic “3741” as modified discloses (Figs.1-8) comprising a current limiter circuit (injection circuit 204 include amplifier 402 which comprise switch 504 and 508 is equivalent to current limiter. Examiner noted that the current needed to activation and deactivation of switches 504 and 508 are equivalent to the current limiter) coupled between the first terminal of the VCCS and the first terminal of the capacitor (305), and between the second terminal of the VCCS and the second terminal of the resistor (Jovanovic “2563” discloses the second terminal of resistor R4).
In re to claim 8, Jovanovic “3741” a circuit (Figs. 1-8) comprising: an amplifier (Fig. 3: comparator 302 ) having an amplifier output (output terminal 302 generate error signal 107), the amplifier configured to provide at the amplifier output (107) , an error signal representing a difference between a converter output voltage (voltage level of regulated power supply node 109) and a reference voltage (reference voltage node 105),; a comparator (comparator 303) coupled to the amplifier output (107), the comparator configured to compare the error signal (107) to a current sense signal (current sensor 301 generate inductor current 11); and
a compensation circuit (capacitor 305) coupled to the amplifier output (107) , the compensation circuit capacitor (305)
a differentiator circuit (Fig. 4: filter unit (401) : by comparing the filtered and unfiltered versions of the voltage level of regulated power supply node 109, filter circuit 401 can detect a drop in the voltage level of regulated power supply node 109 that occurs within a particular period of time, see prag. 0042) the differentiator circuit configured to sense a change in voltage across the resistor (comparing the filtered and unfiltered versions of the voltage level see parag.0041-0043) , and provide a sense signal representing the change in voltage (filtered signals 406 and 407); and
a voltage controlled current source (VCCS) (Fig. 3: injection circuit 304, Fig.4 : injection circuit 204 comprises amplifier circuit 402, amplifier circuit 403 and current source 404 ) coupled across the capacitor (Fig. 3: injection circuit 304 is coupled to capacitor 305), and having an input coupled to the differentiator circuit (Fig. 3: injection current (308) coupled to first terminal of capacitor 305 thru diode 307),
, the VCCS configured to provide a current to the capacitor responsive to the sense signal (output of 304 is configured to provide current to capacitor 305).
Jovanovic “3741” fails to discloses a resistor and a capacitor coupled in series and differentiator circuit coupled to the a resistor.
Whereas Jovanovic “2563” discloses a power converter ( Fig. 3A) discloses compensation circuit (Fig. 3A: compensation circuit (315)) having a resistor and a capacitor coupled in series (resistor R3, resistor R4 and capacitor C4 are coupled in series and second resistor R4 is coupled to capacitor C4) and differential circuit coupled to the resistor (slope detector (305) which comprises a differentiator circuit comparing bandpass filter 314 voltage and an output is connected between resistor R3 and R4 to inject error signal V_error via compensation circuit network 315).
Therefore, it would have been obvious to one of ordinary skilled person in the art before the effective filing date of the claimed invention to have modified the filter capacitor C4 of Jovanovic “3741” to include a resistor and a capacitor coupled in series and differentiator circuit coupled to R4 as taught by Jovanovic “2563” because bandpass filter 315 may substantially reject signals outside of a frequency band defined by the respective component values of R1, C1, R2, and C2, thus provide the amount of current that is desired to be delivered to the output node, Vout, for a given operating condition which improve the efficiency of the power converter, see col. 6, lines 46-50 and col. 6, lines 7-9 .
In re to claim 10, Jovanovic “3741” as modified discloses (Figs.1-8);
wherein the resistor includes a first resistor and a second resistor coupled in series (Jovanovic “2563” Fig. 3A shows a resistor R3,resistor R4 and capacitor C4 are coupled in series ).
In re to claim 14, Jovanovic “3741” as modified discloses (Figs.1-8)
further comprising a comparator (Fig: 3 comparator circuit 303. Examiner noted that claim 14 depend on claim 8 and claim 8 is introduced a comparator in the claim language. Examiner best understood that there is no further comparator/another/other/second comparator are showing in Figs. 1-3 of the invention, thus further comprising a comparator referring to the same comparator introduced in claim 8) having a first input coupled to the output of the amplifier (error signal 107), a second input coupled to a current sense resistor (sensor circuit 301), and an output coupled to a latch (Fig.3 :control signal 108 and fig. 2 logic control 203 configured to receive control signal 108).
In re to claim 15, Jovanovic “3741” discloses a switching converter (Figs. 1-8 shows a power converter) comprising: an output terminal (Figs. 1 and 3-4 shows a regulated power supply node 109) configured to provide a converter output voltage (Vout);
an amplifier (Fig. 3: comparator 302 ) having a feedback input coupled to the output terminal (node 109), a reference input (reference voltage 105) coupled to a voltage reference circuit (reference voltage 105) , and an error output (Fig.3: error signal 107) ;
a compensation circuit (capacitor 305) coupled to the error output (error signal 107) ; the compensation circuit (305) including: a capacitor having a first capacitor terminal coupled to the error output (305 is coupled to error single 107), and second capacitor terminal (second plate of capacitor 305); a resistor having a first resistor terminal coupled to second capacitor terminal,
a differentiator circuit (Fig. 4: filter unit (401) :by comparing the filtered and unfiltered versions of the voltage level of regulated power supply node 109, filter circuit 401 can detect a drop in the voltage level of regulated power supply node 109 that occurs within a particular period of time., see prag. 0042) and a differentiator output (Fig.4: output of 401 generates filter signals 406 &407 are coupled 402 );
a voltage controlled current source (VCCS) (Fig. 3: injection circuit 304, Fig.4 : injection circuit 204 comprises amplifier circuit 402, amplifier circuit 403 and current source 404 ) having a first terminal (Fig. 3: injection circuit 304 output terminal generated injection current 308), and a VCCS input coupled to the differentiator output (Fig. 4 ; amplifier circuit 402 is configured to receive filter signals 406 and 407) and
a current limiter circuit (injection circuit 204 include amplifier 402 which comprise switch 504 and 508. Examiner noted that the current needed to activation and deactivation of switches 504 and 508 are equivalent to the current limiter) coupled between the first terminal of the VCCS and the first terminal of the capacitor (injection circuit 304 is coupled to capacitor 305 thru diode 307).
Jovanovic “3741” fails to discloses a resistor having a resistor having a first resistor terminal coupled to the second capacitor terminal, and a second resistor terminal and differential circuit coupled to the second resistor terminal.
Whereas Jovanovic “2563” discloses a power converter ( Fig. 3A) discloses compensation circuit (Fig. 3A: compensation circuit (315) comprises resistor R3, resistor R4 and capacitor C4 are coupled in series and second resistor R4 is coupled to capacitor C4) and slope detector (305) which comprises a differentiator circuit input are connected to the resistors R1 and R2 and an output of 305 is connected to a voltage control current 310 resistor between R3 &R4 which inject error signal V_error via compensation circuit network 315).
Therefore, it would have been obvious to one of ordinary skilled person in the art before the effective filing date of the claimed invention to have modified the filter capacitor C4 of Jovanovic “3741” to include a compensation network filter 315 as taught by Jovanovic “2563” because bandpass filter 315 may substantially reject signals outside of a frequency band defined by the respective component values of R1, C1, R2, and C2, thus provide the amount of current that is desired to be delivered to the output node, Vout, for a given operating condition which improve the efficiency of the power converter, see col. 6, lines 46-50 and col. 6, lines 7-9 .
In re to claim 19, Jovanovic “3741” as modified discloses (Figs.1-8)
further comprising a comparator (Fig: 3 comparator circuit 303) having a first input coupled to the output of the amplifier (error signal 107), a second input coupled to a current sense resistor (sensor circuit 301), and an output coupled to a latch (Fig.3 :control signal 108 and fig. 2 logic control 203 configured to receive control signal 108).
6. Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Jovanovic “20230043741” in a view of Jovanovic “11552563” further in a view of Silva “11424672”.
In re to claim 6, Jovanovic “3741” as modified discloses (Figs.1-8)
a circuit (Fig. 3 : shows a generic circuit where comparator circuit 302 is configured to generate error signal 113 on node 306 using reference voltage 105 and a voltage level of regulated power supply node 109, see para.0035).
However, Jovanovic “3741”as modified fails to the resistor is a first resistor; the circuit includes a : a second resistor having a first terminal coupled to an output terminal of a switch mode power supply, and a second terminal coupled to the feedback input of the amplifier; and a third resistor having a first terminal coupled to the second terminal of the second resistor, and a second terminal coupled to a reference terminal.
Whereas, Silvas discloses a boost converter (Fig. 3) having a first resistor (current sensor resistor Rs) ; a second resistor having a first terminal coupled to an output terminal of a switch mode power supply (voltage divider circuit 304 comprises two resistor in series, wherein the top/first resistor is equivalent to a first resistor coupled to output terminal Vout), and a second terminal coupled to the feedback input of the amplifier (top/first resistor is coupled to 307); and a third resistor (bottom/second resistor of 304) having a first terminal coupled to the second terminal of the second resistor (bottom/second resistor of 304 is coupled to the top resistor of 304) , and a second terminal coupled to a reference terminal (second resistor is coupled to ground).
Therefore, it would have been obvious to one of ordinary skilled person in the art before the effective filing date of the claimed invention to have modified the reference circuit 105 and regulated power supply node 105 of Jovanovic “3741” to include voltage divider circuit 304 and reference circuit as taught Sivas because voltage divider circuit 304 is used to step down the voltage Vboost_out, thus to stabilize the feedback loop of the converter which leads to improve the efficiency overall, see col. 6, lined 28-31 .
In re to claim 7, Jovanovic “3741” as modified discloses (Figs.1-8)
further comprising a comparator (Fig: 3 comparator circuit 303) having a first input coupled to the output of the amplifier (error signal 107), a second input coupled to a current sense resistor (sensor circuit 301), and an output coupled to a latch (Fig.3 :control signal 108 and fig. 2 logic control 203 configured to receive control signal 108).
Allowable Subject Matter
7. Claims 3-5, 9, 11-13, 16-18 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 3 is objected because the prior art in the record fails to discloses or suggest a circuit including of “wherein the current limiter circuit is configured to disconnect the VCCS from the first terminal of the capacitor responsive to current flow from the VCCS being less than a threshold current. ”
Claim 4 is objected because the prior art in the record fails to discloses or suggest a circuit including of “the resistor is a first resistor; the input of the differentiator circuit is a first input, and the differentiator circuit has a second input; and the circuit includes a second resistor having a third resistor terminal coupled to the second resistor terminal, and a fourth resistor terminal coupled to the second input of the differentiator circuit. ”
Claim 9 is objected because the prior art in the record fails to discloses or suggest a circuit including of “a current limiter circuit coupled between an output of the VCCS and the capacitor, the current limiter circuit configured to disconnect the VCCS from the capacitor responsive to the current provided by the VCCS being less than a threshold current. ”
Claim 11 is objected because the prior art in the record fails to discloses or suggest a circuit including of “the VCCS has a first terminal coupled to a first terminal of the capacitor; a second terminal of the capacitor is coupled to a first terminal of the first resistor; and a second terminal of the VCCS is coupled to a second terminal of the first resistor. ”
Claim 13 is objected because the prior art in the record fails to discloses or suggest a circuit including of “the capacitor is a first capacitor; the amplifier is a first amplifier; and the differentiator circuit includes: a second capacitor having a first terminal coupled to second terminal of the resistor, and a second terminal; a second amplifier having a first input coupled to the second terminal of the second capacitor, a second input coupled to the second terminal of the second resistor, and an output coupled to the input of the VCCS; and a resistor coupled between the output of the second amplifier and the first input of the second amplifier. ”
Claim 16 is objected because the prior art in the record fails to discloses or suggest a circuit including of “wherein the current limiter circuit is configured to disconnect the VCCS from the first terminal of the capacitor responsive to current flow from the VCCS being less than a threshold current.”
Claim 17 is objected because the prior art in the record fails to discloses or suggest a circuit including of “the resistor is a first resistor; the input of the differentiator circuit is a first input, and the differentiator circuit has a second input; and the compensation circuit includes a second resistor having a third resistor terminal coupled to the second resistor terminal, and a fourth resistor terminal coupled to the second input of the differentiator circuit. ”
Claim 20 is objected because the prior art in the record fails to discloses or suggest a circuit including of “wherein the current limiter circuit includes: a current sensor having an input coupled to the first terminal of the VCCS, and an output; a current limiter control circuit having an input coupled to the output of the current sensor, and an output; and a switch having a first terminal coupled to the first terminal of the VCCS, a second terminal coupled to the first terminal of the capacitor, and a control input coupled to the output of the current limiter control circuit. ”
Claims 5 are depend on claim 4, thus is also objected because to its dependency.
Claims 12 are depend on claim 11, thus is also objected because to its dependency.
Claim 18 are depend on claim 17, thus is also objected because to its dependency.
Conclusion
8. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Quyang “20150155784” the present invention generally relates to electrical circuit, and more particularly but not exclusively relates to transient response control circuit and control method in switch mode power supply.
Wong “20240039405” the present invention relates to slope compensation induced offset error cancellation in a peak or valley current mode switching voltage regulator.
Huang “20240235366” the present disclosure relates to the technical field of switching power supply, and in particular to a switching converter and a control circuit thereof.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SISAY G TIKU whose telephone number is (571)272-6898. The examiner can normally be reached 8:30AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal L Hammond can be reached at (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SISAY G TIKU/
Primary Examiner, Art Unit 2838